DTCO Simulation Frameworks

Updated 15 April 2026

DTCO Simulation Frameworks are computational infrastructures that integrate device/process modeling with design to systematically optimize power, performance, and area (PPA).
They employ surrogate models, machine learning techniques, and multi-objective optimization loops to accelerate design iterations and reduce simulation runtimes.
They enable seamless integration from device, cell, to system-level evaluation, supporting advanced VLSI, robotics co-design, and emerging technology applications.

Design-Technology Co-Optimization (DTCO) Simulation Frameworks are computational infrastructures that tightly couple device/process technology and design (cell, circuit, block, and system) parameter spaces, enabling systematic exploration for optimal power, performance, and area (PPA) across realistic variability and process-constraint landscapes. DTCO simulation frameworks accelerate time-to-silicon by integrating device-level, cell-level, and system-level modeling, leveraging physical models, machine learning surrogates, and rigorous optimization loops. These platforms underpin modern VLSI development, emerging technology introduction, and robotics co-design, supporting both incremental technology evolution and disruptive architecture paradigms.

1. Architectural Principles of DTCO Simulation Frameworks

Fundamental DTCO simulation frameworks instantiate a closed-loop workflow bridging device/process modeling, standard-cell or block-level construction, and system-level PPA or objective evaluation. The canonical flow comprises:

Technology/device modeling (e.g., process corners, geometry, new material physics, compact models, or surrogate ML models)
Cell library characterization (timing, power, capacitance, layout parametrization)
Synthesis and system-level PPA/constraint evaluation (e.g., via RTL, netlists, placers/routers, circuit simulation)
Iterative feedback for design and/or technology adjustments

Recent frameworks have modularized this flow:

Layer	Model Type	Example Reference
Device Technology	TCAD, compact, or ML surrogate models	(Zhang et al., 2019, Fan et al., 26 Dec 2025)
Cell Library	Graph-based characterization, constraint-CP/SAT	(Ma et al., 2023, Cheng et al., 14 Mar 2026)
PPA Aggregation	Unified compact model, system-level estimation	(Ma et al., 2024)
Optimization/Feedback	RL, Bayesian, evolutionary, LLM agentic	(Ma et al., 2024, Fan et al., 26 Dec 2025)

Early approaches relied chiefly on SPICE and compact models; scalable frameworks now employ graph neural networks (GNNs), constraint-programming (CP), and machine learning surrogates, enabling orders-of-magnitude speedup and broader parametric coverage (Ma et al., 2023, Ma et al., 2024).

2. Surrogate Modeling and Machine Learning Integration

Increasing PVT (process-voltage-temperature) space, new devices (e.g., nanosheet FETs, CNTs, TFETs), and immense cell libraries make brute-force SPICE or TCAD infeasible. To address this:

Neural network surrogates (MLPs, GNNs, RelGATs) are trained on extensive TCAD/SPICE data, predicting device characteristics (I–V, Q–V), and replacing compact models inside simulation (Ma et al., 2023, Zhang et al., 2019, Ma et al., 2024).
- Inputs include bias (e.g., $V_G$ , $V_D$ , $V_S$ ), geometry, material flags.
- Outputs: terminal currents, charges, cell timing, power, capacitance.
- Example: Graph-based GNN yields delay, flip and non-flip power, input pin capacitance with mean absolute percentage error (MAPE) $\le$ 0.95%, and achieves 100X SPICE speedup (Ma et al., 2023).
Data flow: Training sets may cover $>10^5$ corners ( $V_{DD}$ , $V_{th}$ , temperature, load/slew), with test/validation on unseen grid points. Pre-processing employs normalization, log scaling for current/charge, and stratified bias-space splits.

Surrogate model selection and architecture are validated via device-level metrics (MSE, R $^2$ , mean/max error) and by circuit-level fidelity (timing, power estimation matching physical simulation) (Zhang et al., 2019).

3. Optimization Algorithms and Workflow Orchestration

Optimization engines in DTCO frameworks operationalize joint design-technology exploration via:

Multi-objective, multi-level search: Scalarization/weighting strategies are applied to trade off PPA sub-objectives; Pareto points approximate the objective surface (Unjhawala et al., 2 Feb 2026).
RL/Agentic Loops: Systems such as AgenticTCAD employ LLM-driven agents for code synthesis (TCAD scripting), simulation orchestration, post-processing, and parameter space navigation, targeting IRDS device constraints with closed feedback (Fan et al., 26 Dec 2025).
Evolutionary and Bayesian Optimization: Frameworks apply sample-efficient search (e.g., Gaussian processes, CMA-ES) over mixed discrete-continuous parameter spaces, including controller gains, device geometries, or layout parameters (Unjhawala et al., 2 Feb 2026, Mishra et al., 7 Apr 2026).

A typical simulation pseudocode for an agentic workflow is:

$V_D$ 1 (Fan et al., 26 Dec 2025)

4. Framework Components: Device, Cell, and System-Level Integration

Device Modeling

Physical device behavior is modeled by SPICE compact models (e.g., BSIM-CMG), analytic variability models (LER, MGG) (Patil et al., 2021), or ML surrogates. For new materials or architectures, GNN surrogates or LLM-synthesized TCAD scripts generalize what physics-based models cannot easily capture (Fan et al., 26 Dec 2025, Ma et al., 2024).

Cell Library Generation

Cell libraries are characterized by fast surrogate models (GNN/GCN) trained on SPICE-derived datasets, delivering predictions of timing/power/capacitance for unseen corners and enabling fast iteration (Ma et al., 2023). Constraint-programming methods (CPCell) provide globally optimal transistor placement and routing for arbitrary poly:metal pitch (gear ratio), supporting fine-grained DTCO studies (Cheng et al., 14 Mar 2026).

PPA Aggregation and System Evaluation

Unified compact models aggregate component characteristics into block/system PPA. Examples include mobility-dependent TFT models, where device and cell predictions are composed into system-level delay/power equations (Ma et al., 2024). Analytical and empirical models are calibrated to match SPICE and parasitic-extracted results for accuracy in physical silicon prediction (Vaidyanathan, 2015).

5. Application Domains and Case Studies

DTCO simulation frameworks have been instantiated in diverse technology and application domains:

Logic Design and Emerging Nodes: STCO/DTCO frameworks unify cell, device, and system modeling; GNN surrogates reduce system PPA estimation runtime by 1.9–14.1× over traditional flows (Ma et al., 2024).
Holistic, Memory-Intensive SoC Blocks: Holistic frameworks (e.g., SMSF) automate sub-20nm SRAM exploration, folding in micro-architecture, circuit/layout, and process constraints, achieving up to 25–50% area/energy reduction with full silicon validation (Vaidyanathan, 2015).
Robotic/Mechatronic Co-Design: Multistage DTCO frameworks optimize actuator technology, mechanics, and control for systems such as robotic jumpers and off-road vehicles. Combined surrogate modeling and sample-efficient optimization deliver orders-of-magnitude speedup in exploration while maintaining hardware fidelity (Unjhawala et al., 2 Feb 2026, Mishra et al., 7 Apr 2026).
Advanced Layout Co-Optimization: CPCell explores gear-ratio and M0 pin accessibility trade-offs in cell layout, demonstrating globally optimal results for up to 48 transistors and direct block-level IR-drop implications (Cheng et al., 14 Mar 2026).

6. Model Validation, Variability, and Best Practices

High-fidelity DTCO frameworks emphasize:

Variability Modeling: Compact LER/MGG-aware models enable accurate $\sigma/\mu$ estimation for circuit hold margins and dynamic/standby power, reducing pessimism and enabling aggressive node scaling (Patil et al., 2021).
Model Calibration and Feedback: Iterative calibration with extracted parasitics, SPICE, or silicon data feeds updated PPA, delay, and power tables, closing the optimization loop until performance and yield converge (Vaidyanathan, 2015).
Benchmarking: Framework effectiveness is empirically demonstrated by direct comparison to golden references, hardware measurements, or ablation studies.

Representative results include NNs achieving $<0.5\%$ error for device and circuit metrics (Zhang et al., 2019), and GNN-based characterization matching SPICE within $V_D$ 0 MAPE over more than one million test points (Ma et al., 2023).

7. Scalability, Limitations, and Outlook

Major strengths and trajectories:

Accelerated exploration: Order-of-magnitude reductions in TCAD/circuit simulation runtime unlock higher-dimensional parametric studies and rapid technology bring-up (Ma et al., 2024, Ma et al., 2023).
Generality: Surrogate models, agentic workflows, and constraint-programming-based methods readily extend across devices (FinFETs, nanosheets, CNTs, TFETs), emerging materials, and non-CMOS domains (robotics, mechatronics) (Zhang et al., 2019, Fan et al., 26 Dec 2025).
Automation and integration: Multi-agent frameworks (e.g., AgenticTCAD) demonstrate fully end-to-end automation from language-level design specification to PDK-compliant simulation with convergence guarantees for IRDS targets (Fan et al., 26 Dec 2025).

Limitations include large up-front data/cost for surrogate training, potential degradation outside training domains, and reliance on ML/agentic reasoning for convergence without strict formal guarantees. Future work is directed toward multi-fidelity surrogates, uncertainty quantification, RL-based optimization loops, and extension to full-flow digital/analog/mixed-signal blocks (Ma et al., 2024, Fan et al., 26 Dec 2025).

References: (Ma et al., 2023, Fan et al., 26 Dec 2025, Unjhawala et al., 2 Feb 2026, Patil et al., 2021, Ma et al., 2024, Mishra et al., 7 Apr 2026, Cheng et al., 14 Mar 2026, Vaidyanathan, 2015, Zhang et al., 2019)