Gate-Defined Electron Spin Qubits

• Gate-defined electron spin qubits are qubits encoded in the spin states of electrons confined in lithographically defined quantum dots, with designs ranging from single-spin to multi-electron exchange-only schemes.
• They utilize electrical control mechanisms such as electric-dipole spin resonance and tunable exchange interactions across various materials like GaAs, Si/SiGe, and Ge to achieve high-fidelity operations.
• Integration of gate-based dispersive readout and scalable architectures advances multi-qubit systems, although challenges from valley physics and charge noise persist.

Gate-defined electron spin qubits are qubits encoded in the spin state of one or more electrons electrostatically confined in lithographically defined quantum dots. In the most basic realization, the logical basis is the spin-$\tfrac12$ doublet $|\uparrow\rangle,|\downarrow\rangle$ of a single confined electron, while more elaborate encodings use two or three electrons in double or triple dots to define singlet-triplet or exchange-only logical subspaces. Across materials systems, the defining features are gate-controlled confinement, tunable tunnel barriers, electrical programmability of detuning and exchange, and spin-to-charge conversion for readout; the principal distinctions arise from host-band structure, valley structure, spin-orbit coupling, hyperfine environment, fabrication stack, and readout architecture (Kuemmeth et al., 2020, Kawakami et al., 2016, Mei et al., 13 May 2026).

1. Physical definition and qubit encodings

In gate-defined implementations, metallic gates shape an electrostatic potential that confines electrons within a semiconductor channel or two-dimensional electron gas. In GaAs/AlGaAs heterostructures, surface gates deplete a nearby 2DEG and create potential minima that trap electrons (Kuemmeth et al., 2020). In Si/SiGe heterostructures, vertical confinement is supplied by the heterostructure and lateral confinement by gate voltages, as in undoped Si/SiGe quantum dots controlled by accumulation, plunger, and barrier gates (Kawakami et al., 2016). In silicon nanowire CMOS devices, split gates induce corner quantum dots at opposite corners of a nanowire (Ciriano-Tejel et al., 2020). In germanium, the envisioned gate-defined electron platform uses a strained Ge/SiGe heterostructure in which source regions inject electrons into a Ge quantum-well channel and metallic barrier/plunger gates define the dot (Mei et al., 13 May 2026).

The most direct logical encoding uses a single confined electron spin,

$|\uparrow\rangle,\qquad |\downarrow\rangle,$

with Zeeman splitting set by a static magnetic field. This single-spin encoding underlies Si/SiGe micromagnet-driven qubits (Kawakami et al., 2016), CMOS silicon nanowire dots (Ciriano-Tejel et al., 2020), GaAs single-spin devices (Kuemmeth et al., 2020), and the exploratory gate-defined electron modality in germanium (Mei et al., 13 May 2026). A distinct but closely related gate-defined encoding is the $S$-$T_0$ qubit in a double dot with one electron per dot, where

$$\ket{0}\equiv \ket{S} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}-\ket{\downarrow\uparrow}),\qquad \ket{1}\equiv \ket{T_0} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}+\ket{\downarrow\uparrow}),$$

and the leakage states are $\ket{T_+}$ and $\ket{T_-}$ (Cerfontaine et al., 2016). Exchange-only encodings extend the same logic to three spins, with the logical basis embedded in the $S_{123}=1/2$ subspace of three exchange-coupled electrons (Weinstein et al., 2022).

The unifying control primitive for coupled gate-defined dots is the Heisenberg exchange interaction,

$$H_{\mathrm{ex}} = J\,\mathbf S_1 \cdot \mathbf S_2,$$

with electrically tunable $|\uparrow\rangle,|\downarrow\rangle$0. This interaction supports two-qubit gates, singlet-triplet splittings, exchange-only logic, mediated coupling schemes, and exchange-based transport and teleportation concepts (Kuemmeth et al., 2020, Weinstein et al., 2022). In practice, the choice between single-spin, two-spin, and three-spin encoding is a trade-off among control resources, leakage structure, hyperfine sensitivity, pulse complexity, and architectural density.

A common misconception is that “gate-defined electron spin qubit” denotes a single mature technology. The provided literature instead describes a family of platforms whose shared electrostatic confinement masks substantial diversity in valley structure, spin-orbit physics, confinement geometry, and readout modality. This is explicit in the germanium comparison, where gate-defined electron qubits are treated as conceptually familiar but underdeveloped because the electron occupies the multivalley $|\uparrow\rangle,|\downarrow\rangle$1-valley conduction band rather than a single-valley conduction minimum (Mei et al., 13 May 2026).

2. Materials platforms and band-structure constraints

The physical behavior of a gate-defined electron spin qubit is strongly host-material dependent. GaAs historically served as the pioneering platform because gate-defined dots are comparatively straightforward to build, the conduction band is single-valley, the effective mass is small, dopants are stable, and high-quality heterostructures were established through decades of molecular-beam-epitaxy development (Kuemmeth et al., 2020). Its major intrinsic drawback is that nuclear spins are unavoidable in natural GaAs, producing hyperfine-field fluctuations and an intrinsic inhomogeneous dephasing time $|\uparrow\rangle,|\downarrow\rangle$2 of about $|\uparrow\rangle,|\downarrow\rangle$3 ns (Kuemmeth et al., 2020).

Silicon gate-defined qubits are distinguished by a magnetically quiet host, CMOS compatibility, and the possibility of isotopic purification. In Si/SiGe, a single-electron spin qubit controlled by a micromagnet reached about $|\uparrow\rangle,|\downarrow\rangle$4 average single-qubit gate fidelity and coherence up to about $|\uparrow\rangle,|\downarrow\rangle$5s with $|\uparrow\rangle,|\downarrow\rangle$6 decoupling pulses, even without isotopic purification (Kawakami et al., 2016). In CMOS nanowire corner dots, excited-state spectroscopy yielded valley splittings in the range $|\uparrow\rangle,|\downarrow\rangle$7–$|\uparrow\rangle,|\downarrow\rangle$8 meV and a maximum measured spin relaxation time $|\uparrow\rangle,|\downarrow\rangle$9 s at $|\uparrow\rangle,\qquad |\downarrow\rangle,$0 T (Ciriano-Tejel et al., 2020). Foundry-fabricated silicon 2D arrays have also reached single-electron occupation in each dot of a $|\uparrow\rangle,\qquad |\downarrow\rangle,$1 array with pulsed-gate manipulation and gate-reflectometry-based single-shot charge readout (Ansaloni et al., 2020).

Germanium is presented in explicitly comparative terms. High-purity Ge combines mature materials processing, access to spin-free isotopes, high mobilities, small effective masses, and strong but engineerable spin-orbit coupling (Mei et al., 13 May 2026). For gate-defined electron qubits specifically, the central complication is the multivalley $|\uparrow\rangle,\qquad |\downarrow\rangle,$2-point conduction band with four equivalent minima, anisotropic masses $|\uparrow\rangle,\qquad |\downarrow\rangle,$3 and $|\uparrow\rangle,\qquad |\downarrow\rangle,$4, and averaged masses $|\uparrow\rangle,\qquad |\downarrow\rangle,$5 and $|\uparrow\rangle,\qquad |\downarrow\rangle,$6 (Mei et al., 13 May 2026). The paper stresses that valley splitting, intervalley mixing, and valley-orbit physics are central rather than perturbative features. Natural Ge already has more than $|\uparrow\rangle,\qquad |\downarrow\rangle,$7 spin-free nuclei, and enrichment can further suppress the $|\uparrow\rangle,\qquad |\downarrow\rangle,$8Ge nuclear bath, but gate-defined electron qubits would still remain sensitive to residual nuclei through direct wavefunction overlap with the host (Mei et al., 13 May 2026).

Other two-dimensional materials broaden the concept rather than replacing the semiconductor quantum-dot paradigm. In bilayer graphene, a gate-defined single-electron dot was formed electrostatically in an hBN-encapsulated van der Waals heterostructure, and transient-current spectroscopy extracted a lower bound $|\uparrow\rangle,\qquad |\downarrow\rangle,$9s for the first excited single-electron spin state (Banszerus et al., 2020). In a single-layer TMDC quantum dot, the logical basis can be a gate-defined spin-valley doublet,

$S$0

computed in a multi-million-atom tight-binding model (Altıntaş et al., 2021). This is still a gate-defined electron qubit, but it is not a pure-spin qubit in the GaAs or Si sense.

Platform	Salient feature	Constraint emphasized
GaAs	Single conduction-band valley; small effective mass	Nuclear spins give $S$1 about $S$2 ns
Si/SiGe and Si CMOS	Magnetically quiet host; CMOS-compatible fabrication	Valley physics and charge-noise sensitivity remain relevant
Ge/SiGe electrons	Strong isotopic purification potential; engineerable $S$3-tensor physics	Multivalley $S$4-band, valley-orbit mixing, interface sensitivity
BLG and TMDCs	Electrostatic confinement in atomically thin materials	Spin and valley are intertwined in the low-energy spectrum

These comparisons clarify that material choice is not reducible to a single scalar metric. A plausible implication is that the most successful implementations are those in which the dominant band-structure complications are either absent, as in single-valley GaAs, or sufficiently engineered, as in advanced silicon devices, to permit a complete control and readout stack.

3. Electrostatic confinement, Hamiltonians, and control mechanisms

The confinement potential of a gate-defined electron qubit is a lithographically set but electrically reconfigurable object. In conventional GaAs and Si dots, plunger and barrier gates tune occupancy, detuning, and tunnel rates. In silicon double dots, tunnel-gate widths and gate voltages tune interdot coupling, while common top gates in $S$5 arrays significantly increase tunnel couplings and reduce characteristic tunneling times (Ansaloni et al., 2020). In Si-MOS device modeling, TCAD-derived three-dimensional potentials produce strongly anisotropic confinement frequencies, with $S$6 THz and $S$7 THz for a single dot in the simulated geometry (Shehata et al., 2022).

For single-spin control, electric-dipole spin resonance driven by micromagnet gradients is a standard route. In a Si/SiGe quantum dot with two cobalt micromagnets, microwave bursts applied to a gate oscillate the electron wavefunction in a magnetic-field gradient, creating an artificial spin-orbit field that enables purely electrical control (Kawakami et al., 2016). The same paper emphasizes the trade-off: the micromagnet gradient enables fast electrical control but also converts charge noise into effective spin noise because fluctuations in dot position modulate the spin splitting.

For encoded $S$8-$S$9 qubits, the effective Hamiltonian in the logical basis is

$T_0$0

where $T_0$1 is the exchange splitting controlled electrically by detuning $T_0$2, and $T_0$3 is the magnetic-field gradient across the dots (Cerfontaine et al., 2016). In three-spin exchange-only qubits, all control is performed by pulsed exchange interactions, with calibrated gate angles given by

$T_0$4

This supports universal encoded logic using only baseband voltage pulses (Weinstein et al., 2022).

In Ge electron dots, the paper suggests that electrical manipulation would most likely come from engineered $T_0$5-tensor modulation or other confinement-induced spin-orbit effects rather than from a naturally strong hole-like EDSR mechanism (Mei et al., 13 May 2026). The qubit transition frequency is written as

$T_0$6

That formulation is modality-independent, but the microscopic coupling is not: in Ge electrons, phonons couple first to orbital, valley, and $T_0$7-tensor degrees of freedom, and only then to spin through spin-orbit admixture and valley repopulation (Mei et al., 13 May 2026).

A broader theoretical literature reinforces the same control logic. Long-distance coupling via floating metallic gates uses electrostatically mediated interactions between distant gate-defined quantum dots, with effective spin-spin coupling obtained by combining spin-orbit coupling and the floating-gate-induced electrostatic gradient (Trifunovic et al., 2011). In FinFET-based proposals, the common gate of a transistor-like structure simultaneously controls confinement and the channel Fermi level, while RKKY exchange through the channel mediates inter-qubit coupling (Tanamoto et al., 2020). These proposals remain distinct from the nearest-neighbor exchange-dominated mainstream, but they show that “gate-defined” need not imply only short-range coupling or only conventional multi-gate layouts.

4. Initialization, measurement, and dispersive readout

Readout in gate-defined electron spin qubits is usually based on spin-to-charge conversion followed by charge sensing. The most established mechanism is Pauli spin blockade in a double dot: singlet-like states can hybridize with a $T_0$8 charge configuration, whereas triplet-like states are blocked by the Pauli principle (West et al., 2018, Sen et al., 8 Mar 2026). This can be sensed either by a nearby electrometer or directly by gate reflectometry.

In silicon, gate-based dispersive sensing has been developed specifically to address the scaling problem created by separate charge sensors. In a SiMOS double dot, the gate impedance can be modeled as

$T_0$9

and at fixed probe frequency the phase shift is approximately

$$\ket{0}\equiv \ket{S} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}-\ket{\downarrow\uparrow}),\qquad \ket{1}\equiv \ket{T_0} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}+\ket{\downarrow\uparrow}),$$0

Using this mechanism, single electron tunnelling was detected and single-shot spin readout was achieved with average gate-based readout fidelity $$\ket{0}\equiv \ket{S} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}-\ket{\downarrow\uparrow}),\qquad \ket{1}\equiv \ket{T_0} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}+\ket{\downarrow\uparrow}),$$1 for $$\ket{0}\equiv \ket{S} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}-\ket{\downarrow\uparrow}),\qquad \ket{1}\equiv \ket{T_0} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}+\ket{\downarrow\uparrow}),$$2, while conventional SET readout in the same device reached $$\ket{0}\equiv \ket{S} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}-\ket{\downarrow\uparrow}),\qquad \ket{1}\equiv \ket{T_0} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}+\ket{\downarrow\uparrow}),$$3 for $$\ket{0}\equiv \ket{S} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}-\ket{\downarrow\uparrow}),\qquad \ket{1}\equiv \ket{T_0} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}+\ket{\downarrow\uparrow}),$$4 (West et al., 2018). The significance of that result is architectural rather than only metrological: the same gate that defines the dot participates in readout, reducing footprint and complexity.

Later CMOS work pushed gate-based readout substantially further. A triple-gate SOI CMOS nanowire transistor using gate-based RF reflectometry and a latched spin blockade mechanism achieved readout fidelity above $$\ket{0}\equiv \ket{S} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}-\ket{\downarrow\uparrow}),\qquad \ket{1}\equiv \ket{T_0} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}+\ket{\downarrow\uparrow}),$$5 for $$\ket{0}\equiv \ket{S} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}-\ket{\downarrow\uparrow}),\qquad \ket{1}\equiv \ket{T_0} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}+\ket{\downarrow\uparrow}),$$6 ms integration time, with visibility up to $$\ket{0}\equiv \ket{S} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}-\ket{\downarrow\uparrow}),\qquad \ket{1}\equiv \ket{T_0} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}+\ket{\downarrow\uparrow}),$$7 and singlet and triplet fidelities $$\ket{0}\equiv \ket{S} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}-\ket{\downarrow\uparrow}),\qquad \ket{1}\equiv \ket{T_0} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}+\ket{\downarrow\uparrow}),$$8 each (Urdampilleta et al., 2018). The readout remained fully preserved up to $$\ket{0}\equiv \ket{S} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}-\ket{\downarrow\uparrow}),\qquad \ket{1}\equiv \ket{T_0} = \frac{1}{\sqrt{2}}(\ket{\uparrow\downarrow}+\ket{\downarrow\uparrow}),$$9 K and still reached $\ket{T_+}$0 at $\ket{T_+}$1 K (Urdampilleta et al., 2018). A related CMOS nanowire implementation combined spin-dependent tunnelling with a low-footprint single-lead charge sensor quantum dot measured by RF gate reflectometry, obtaining valley splittings $\ket{T_+}$2 meV and $\ket{T_+}$3 meV in two devices and $\ket{T_+}$4 s at $\ket{T_+}$5 T in device B (Ciriano-Tejel et al., 2020).

Gate reflectometry has also been generalized beyond one-bit blockade readout. For a two-electron silicon double dot with a micromagnet, four-state discrimination can be achieved by exploiting distinct quantum capacitances $\ket{T_+}$6 for the four eigenstates near aligned singlet-triplet anticrossings, with the exact expression

$\ket{T_+}$7

The readout contrast is quantified by

$\ket{T_+}$8

and the assignment fidelity is determined by the ratio $\ket{T_+}$9, with $\ket{T_-}$0 (Sen et al., 8 Mar 2026). This is relevant because it shows that gate-based readout can, in principle, extract two bits of information in a single measurement rather than only a single parity bit.

A recurrent misconception is that scalable spin readout necessarily requires a proximal SET or QPC for every qubit. The silicon and donor literature here argues otherwise. Gate-based sensing can use the defining gate itself (West et al., 2018), a local ancilla-dot-plus-reservoir unit cell (Urdampilleta et al., 2018), or a single-lead quantum-dot sensor with extended sensing range (Hogg et al., 2022). The donor result is especially explicit in comparing sensor reach: a single SLQD sensor is estimated to read approximately $\ket{T_-}$1 donor qubits in a linear array, compared to $\ket{T_-}$2–$\ket{T_-}$3 qubits for a similar sensor in a gate-defined quantum dot device, due to the weaker screening of all-epitaxial donor structures (Hogg et al., 2022).

5. Relaxation, dephasing, and gate fidelity

The performance of gate-defined electron spin qubits is bounded by hyperfine noise, charge noise, spin-orbit-assisted relaxation, valley physics, and measurement backaction. The dominant mechanisms depend strongly on the host material and control method.

In GaAs, hyperfine coupling to host nuclear spins is the dominant source of fast dephasing, giving $\ket{T_-}$4 ns, although dynamical decoupling can extend coherence times into the millisecond range and single-qubit control fidelity of $\ket{T_-}$5 has been demonstrated, mainly for singlet-triplet qubits (Kuemmeth et al., 2020). High-fidelity all-electrical control of a GaAs $\ket{T_-}$6-$\ket{T_-}$7 qubit reached average gate fidelity

$\ket{T_-}$8

with leakage rate

$\ket{T_-}$9

using iterative feedback-tuned pulse optimization (Cerfontaine et al., 2016). The same work emphasizes that the main limitation in that experiment was charge noise rather than nuclear-spin noise.

In Si/SiGe single-spin qubits with micromagnet control, randomized benchmarking gave a Clifford fidelity $S_{123}=1/2$0 and a corresponding primitive single-gate fidelity $S_{123}=1/2$1 (Kawakami et al., 2016). Dynamical decoupling extended coherence to $S_{123}=1/2$2s for $S_{123}=1/2$3 pulses, with the decay fit yielding $S_{123}=1/2$4s and $S_{123}=1/2$5 (Kawakami et al., 2016). The paper identifies quasi-static $S_{123}=1/2$6Si noise as the low-frequency contribution and attributes the $S_{123}=1/2$7 kHz–$S_{123}=1/2$8 MHz band primarily to charge noise coupled through the micromagnet gradient.

For exchange-only encoded silicon qubits, the relevant performance metric shifts from primitive single-spin operations to long pulse sequences executed within the encoded subspace. In a six-dot SLEDGE device with isotopically enriched silicon containing residual $S_{123}=1/2$9Si at the $$H_{\mathrm{ex}} = J\,\mathbf S_1 \cdot \mathbf S_2,$$0 ppm level, the idle singlet dephasing time was $$H_{\mathrm{ex}} = J\,\mathbf S_1 \cdot \mathbf S_2,$$1s, blind randomized benchmarking gave average single-qubit Clifford error $$H_{\mathrm{ex}} = J\,\mathbf S_1 \cdot \mathbf S_2,$$2, and two-qubit randomized benchmarking gave average two-qubit Clifford fidelity $$H_{\mathrm{ex}} = J\,\mathbf S_1 \cdot \mathbf S_2,$$3, with interleaved fidelities $$H_{\mathrm{ex}} = J\,\mathbf S_1 \cdot \mathbf S_2,$$4 for FW-CNOT, $$H_{\mathrm{ex}} = J\,\mathbf S_1 \cdot \mathbf S_2,$$5 for SWAP, and $$H_{\mathrm{ex}} = J\,\mathbf S_1 \cdot \mathbf S_2,$$6 for LCCZ (Weinstein et al., 2022).

The comparative Ge paper contributes a modality-independent framework for phonon-mediated relaxation. It writes

$$H_{\mathrm{ex}} = J\,\mathbf S_1 \cdot \mathbf S_2,$$7

and defines a local strain-density-of-states suppression factor

$$H_{\mathrm{ex}} = J\,\mathbf S_1 \cdot \mathbf S_2,$$8

This leads to the estimate

$$H_{\mathrm{ex}} = J\,\mathbf S_1 \cdot \mathbf S_2,$$9

and to the measured-rate decomposition

$|\uparrow\rangle,|\downarrow\rangle$00

The paper is explicit that $|\uparrow\rangle,|\downarrow\rangle$01 is a matrix-element-weighted local strain spectral density, not merely a density of states (Mei et al., 13 May 2026).

A device-to-gate modeling study in Si-MOS further systematizes the role of charge noise. It reports $|\uparrow\rangle,|\downarrow\rangle$02-gate fidelities $|\uparrow\rangle,|\downarrow\rangle$03 in simulated Si-MOS devices at typical two-level-fluctuator densities, but exchange-driven SWAP fidelities down to $|\uparrow\rangle,|\downarrow\rangle$04 at the same density, and concludes that stronger confinement reduces gate errors while nearest fluctuators dominate yield variability (Shehata et al., 2022). This sharp asymmetry between one- and two-qubit sensitivity is consistent with the broader experimental literature, in which exchange is directly exposed to electrostatic disorder.

6. Architectures, scaling strategies, and current status

The scaling problem for gate-defined electron spin qubits is not solely one of coherence or gate fidelity; it is equally a problem of wiring density, sensor footprint, nearest-neighbor geometry, and fabrication yield. Several architectural responses appear in the literature.

One route is dense semiconductor integration. Foundry-fabricated silicon devices have demonstrated a $|\uparrow\rangle,|\downarrow\rangle$05 array operated in the few-electron regime, with single-electron occupation in each of four gate-defined dots, reconfigurable single-, double-, and triple-dot configurations, gate-reflectometry charge readout, and real-space exchange of two electrons in a 2D geometry (Ansaloni et al., 2020). The work explicitly frames the compact form factor as extendable to larger $|\uparrow\rangle,|\downarrow\rangle$06 arrays. A different route is CMOS nanowire integration, where the split-gate corner-dot geometry and gate-reflectometry-based readout are positioned as natural building blocks for $|\uparrow\rangle,|\downarrow\rangle$07 arrays (Ciriano-Tejel et al., 2020).

A second route is readout compaction. Gate-based sensing reduces the need for separate electrometers (West et al., 2018), while latched spin blockade embeds sensing into a compact local unit cell compatible with CMOS processing (Urdampilleta et al., 2018). Single-lead sensors extend this logic by minimizing sensor footprint and, in donor devices, increasing sensing range (Hogg et al., 2022). A plausible implication is that readout architecture may become a dominant differentiator between otherwise similar gate-defined platforms.

A third route is long-distance coupling. Floating metallic gates have been proposed to mediate selective electrostatic coupling over micron-scale distances between electron spins localized in quantum dots, with switching times on the order of nanoseconds and estimated fidelities above the surface-code threshold in the modeled regime (Trifunovic et al., 2011). FinFET-based “common-gate spin qubits” instead trade direct-exchange strength for drastic wiring reduction by using the same gate electrode to control multiple qubits and channel-mediated RKKY coupling for interaction (Tanamoto et al., 2020). These proposals are less mature than nearest-neighbor exchange arrays, but they directly target the wiring bottleneck that conventional multi-gate quantum-dot layouts face.

Within this broader landscape, the status of gate-defined electron qubits is highly uneven across materials. GaAs remains a workhorse for proof-of-concept experiments, automatic tuning, entanglement, teleportation, coherent exchange, and multi-dot arrays, despite intrinsic hyperfine noise (Kuemmeth et al., 2020). Silicon currently provides the strongest combination of foundry compatibility, long $|\uparrow\rangle,|\downarrow\rangle$08, mature gate-defined control, dispersive readout progress, and encoded multiqubit operation (Kawakami et al., 2016, Weinstein et al., 2022, Ansaloni et al., 2020). Germanium electron dots, by contrast, are explicitly described as exploratory: conduction electrons can be confined in Ge quantum wells and their $|\uparrow\rangle,|\downarrow\rangle$09 factor can be strongly tuned by confinement and strain, but a mature gate-defined Ge electron-qubit stack “has not yet emerged” (Mei et al., 13 May 2026).

This status difference is central to current interpretation. Conceptual familiarity does not imply systems-level maturity. The germanium assessment is unambiguous that gate-defined electron spin qubits there are “conceptually attractive” but “underdeveloped,” with no demonstrated systems-level advantage yet over the hole platform, and that their success depends on taming the $|\uparrow\rangle,|\downarrow\rangle$10-valley conduction band and demonstrating a full control stack (Mei et al., 13 May 2026). More generally, the literature here suggests that the future of gate-defined electron spin qubits will be determined less by the abstract viability of single-spin confinement than by whether each material system can assemble a complete stack—confinement, control, readout, coupling, yield, and architecture—without a dominant unresolved materials bottleneck.