Spin Shuttling in Semiconductor Qubits

• Spin shuttling is the coherent transport of a spin qubit’s quantum state by physically moving its carrier in semiconductor devices via adiabatic or traveling-wave potentials.
• It employs two main modalities—bucket brigade and conveyor-mode—to balance disorder tolerance with resource-efficient, dynamic quantum state transfer.
• Experimental and theoretical studies validate shuttling's role in scalable quantum architectures by enabling high-fidelity multi-hop transport and motion-enabled gate operations.

Spin shuttling is the coherent transport of a spin qubit’s quantum state by physically moving the carrier between sites in a semiconductor device, typically a single electron in silicon or a single hole in germanium quantum dots, while preserving spin population and, in the fully coherent regime, phase. In gate-defined semiconductor architectures, it functions as a hardware-native quantum link between spatially separated qubit registers, relieving the wiring bottleneck, enabling sparse and modular layouts, and providing an alternative to static exchange chains, resonator-mediated coupling, and surface-acoustic-wave transport (Zwerver et al., 2022). Two broad implementations dominate the literature: “bucket brigade” transport, in which the carrier is transferred stepwise through successive interdot anticrossings, and conveyor-mode shuttling, in which a traveling electrostatic minimum carries the carrier continuously along a channel (Nagai et al., 28 Feb 2025).

1. Physical principle and transport modalities

In the bucket-brigade mode, an electron is moved by sequentially adjusting electrochemical potentials so it adiabatically follows the ground state through successive interdot anticrossings. In a representative silicon implementation, each hop consists of an abrupt pulse to a point just before an interdot anticrossing in detuning $\epsilon$, a linear ramp through the anticrossing over $\Delta\epsilon \approx 300~\mu\mathrm{eV}$ in $\tau_{\mathrm{ramp}} = 2~\mu\mathrm{s}$, and an abrupt pulse well past the anticrossing to suppress back-tunneling (Zwerver et al., 2022). This mode is tolerant to local disorder and fits naturally into one-dimensional or two-dimensional dot arrays fabricated with standard Si/SiGe gate stacks (Zwerver et al., 2022).

In conveyor-mode shuttling, the confining potential itself is translated. A conventional implementation uses phase-shifted sinusoidal gate voltages, while later work introduced digitally synthesized near-sinusoidal waveforms and two-tone traveling-wave potentials (Nagai et al., 28 Feb 2025). In four-phase wiring with pitch $l_{\mathrm{pitch}}$, the traveling potential advances $4 l_{\mathrm{pitch}}$ per period, so $f = v_{\mathrm{avg}}/(4 l_{\mathrm{pitch}})$ and $f_{\mathrm{clk}} = 4 f$ in the cryogenic integrated implementation (Romero et al., 22 Apr 2026). Conveyor-mode is attractive when the objective is long, resource-efficient channels controlled by a small number of global phases (Zwerver et al., 2022).

The architectural motivation is consistent across platforms. Coherent links spanning tens of micrometers are expected to interconnect sparse clusters of spin qubits while leaving on-chip area between clusters for classical control electronics, including cryo-CMOS multiplexers, DACs, and resonators (Zwerver et al., 2022). This creates a routing primitive that can be concatenated over longer distances and reduces the number of off-chip interconnects required in large arrays (Zwerver et al., 2022).

2. Dynamical models, adiabaticity, and coherence

Near an interdot anticrossing, bucket-brigade shuttling is described by the standard two-level Hamiltonian

$H = (\epsilon/2)\sigma_z + t \sigma_x,$

with detuning $\epsilon$, tunnel coupling $t$, and anticrossing gap $\Delta\epsilon \approx 300~\mu\mathrm{eV}$0 (Zwerver et al., 2022). Charge-transfer adiabaticity is commonly analyzed with the Landau–Zener expression

$\Delta\epsilon \approx 300~\mu\mathrm{eV}$1

where $\Delta\epsilon \approx 300~\mu\mathrm{eV}$2 is half the minimum gap and $\Delta\epsilon \approx 300~\mu\mathrm{eV}$3 is the sweep rate (Zwerver et al., 2022). In the four-dot silicon array of (Zwerver et al., 2022), $\Delta\epsilon \approx 300~\mu\mathrm{eV}$4–$\Delta\epsilon \approx 300~\mu\mathrm{eV}$5 and $\Delta\epsilon \approx 300~\mu\mathrm{eV}$6 give $\Delta\epsilon \approx 300~\mu\mathrm{eV}$7 and thus $\Delta\epsilon \approx 300~\mu\mathrm{eV}$8, so charge transfer is overwhelmingly adiabatic.

Conveyor-mode silicon shuttling introduces a second adiabaticity problem associated with the valley degree of freedom. In a valley-aware description, the joint spin–valley dynamics is governed by

$\Delta\epsilon \approx 300~\mu\mathrm{eV}$9

with $\tau_{\mathrm{ramp}} = 2~\mu\mathrm{s}$0, $\tau_{\mathrm{ramp}} = 2~\mu\mathrm{s}$1, and $\tau_{\mathrm{ramp}} = 2~\mu\mathrm{s}$2 (Romero et al., 22 Apr 2026). Here the local valley splitting is $\tau_{\mathrm{ramp}} = 2~\mu\mathrm{s}$3, and small-$\tau_{\mathrm{ramp}} = 2~\mu\mathrm{s}$4 regions amplify non-adiabatic valley excitation and spin–valley entanglement (Romero et al., 22 Apr 2026). This is the dominant theoretical explanation for why long conveyor paths in disordered Si/SiGe require velocity shaping, path selection, or heterostructure engineering (Losert et al., 2024).

In germanium hole systems, strong spin–orbit interaction makes the local quantization axis itself dot-dependent. Experiments therefore distinguish ramps that are diabatic with respect to the spin quantization axis but adiabatic with respect to charge transfer from ramps that are adiabatic with respect to both (Riggelen-Doelman et al., 2023). In that setting, the relevant phase is

$\tau_{\mathrm{ramp}} = 2~\mu\mathrm{s}$5

so dot-to-dot $\tau_{\mathrm{ramp}} = 2~\mu\mathrm{s}$6-tensor variations directly produce phase shifts that must be calibrated or dynamically refocused (Riggelen-Doelman et al., 2023).

A third line of theory treats motion itself as a resource for decoupling. In planar germanium, temporal and spatial “breathing” protocols modulate the confinement potential during shuttling so that spin–orbit interaction generates a continuous resonant drive, implementing dressed-state transport and continuous dynamical decoupling (Nguyen et al., 1 May 2026). This does not change the definition of spin shuttling, but it broadens the control space from trajectory design alone to trajectory-plus-confinement design.

3. Experimental realizations and representative benchmarks

The experimental literature spans GaAs, Si/SiGe, Si MOS, and Ge/SiGe, with distinct trade-offs between hyperfine noise, spin–orbit interaction, valley physics, and control bandwidth.

Platform and modality	Representative result	Citation
GaAs quadruple-dot coherent shuttle	S–T$\tau_{\mathrm{ramp}} = 2~\mu\mathrm{s}$7 oscillations after shuttling to dot 2, 3, or 4 with $\tau_{\mathrm{ramp}} = 2~\mu\mathrm{s}$8, $\tau_{\mathrm{ramp}} = 2~\mu\mathrm{s}$9, and $l_{\mathrm{pitch}}$0	(Fujita et al., 2017)
Silicon four-dot bucket brigade	Up to $l_{\mathrm{pitch}}$1 hops ($l_{\mathrm{pitch}}$2) with spin-flip probability per hop well below $l_{\mathrm{pitch}}$3	(Zwerver et al., 2022)
Germanium hole-spin bucket brigade	Basis-state shuttling length $l_{\mathrm{pitch}}$4; coherent superposition length $l_{\mathrm{pitch}}$5 with echo	(Riggelen-Doelman et al., 2023)
Silicon conveyor-mode moving dot	Effective $l_{\mathrm{pitch}}$6 displacement in $l_{\mathrm{pitch}}$7 with $l_{\mathrm{pitch}}$8	(Smet et al., 2024)
Silicon MOS bucket brigade	Average shuttling fidelity $l_{\mathrm{pitch}}$9, consistent with a $4 l_{\mathrm{pitch}}$0 headline result	(Lin et al., 21 Jul 2025)

The GaAs work established the core coherence criterion: after separating one electron from a singlet and shuttling it to dots 2, 3, or 4, the separated state evolved periodically into $4 l_{\mathrm{pitch}}$1 and back, showing that relative spin phase survived spatial transport (Fujita et al., 2017). The silicon four-dot experiment then demonstrated repeated forward–backward shuttling up to $4 l_{\mathrm{pitch}}$2 rounds through three dots and $4 l_{\mathrm{pitch}}$3 rounds through four dots, with no detectable number-dependent accumulation of spin flips up to $4 l_{\mathrm{pitch}}$4 hops in the main dataset and $4 l_{\mathrm{pitch}}$5 hops in additional data (Zwerver et al., 2022).

The germanium study is notable because it achieved coherent shuttling despite strong spin–orbit interaction and large dot-to-dot quantization-axis changes, with at least $4 l_{\mathrm{pitch}}$6 tilt between QD2 and QD3 and at least $4 l_{\mathrm{pitch}}$7 between QD3 and QD4 (Riggelen-Doelman et al., 2023). The main limitation there was dephasing rather than shuttling-induced flips, and Hahn echo extended coherent transport from $4 l_{\mathrm{pitch}}$8 to $4 l_{\mathrm{pitch}}$9 (Riggelen-Doelman et al., 2023). This directly contradicts the common simplification that strong spin–orbit interaction is necessarily incompatible with coherent shuttling.

The silicon conveyor comparison in (Smet et al., 2024) sharpened the distinction between bucket-brigade and moving-dot transport. Bucket-brigade shuttling across dots 2 to 5 gave average per-hop return probability $f = v_{\mathrm{avg}}/(4 l_{\mathrm{pitch}})$0 in Ramsey and $f = v_{\mathrm{avg}}/(4 l_{\mathrm{pitch}})$1 in Hahn echo, but $f = v_{\mathrm{avg}}/(4 l_{\mathrm{pitch}})$2 degraded to $f = v_{\mathrm{avg}}/(4 l_{\mathrm{pitch}})$3 during hopping relative to static dots (Smet et al., 2024). Conveyor-mode transport, especially the two-tone conveyor, showed better spin coherence during motion and enabled the $f = v_{\mathrm{avg}}/(4 l_{\mathrm{pitch}})$4, $f = v_{\mathrm{avg}}/(4 l_{\mathrm{pitch}})$5 benchmark (Smet et al., 2024).

4. Error channels and fidelity-limiting mechanisms

In isotopically enriched silicon, the dominant observed decay in repeated bucket-brigade experiments is typically not spin-flip transport error but relaxation during waiting periods. In the four-dot Si/SiGe array, the measured $f = v_{\mathrm{avg}}/(4 l_{\mathrm{pitch}})$6 values at $f = v_{\mathrm{avg}}/(4 l_{\mathrm{pitch}})$7 were $f = v_{\mathrm{avg}}/(4 l_{\mathrm{pitch}})$8, $f = v_{\mathrm{avg}}/(4 l_{\mathrm{pitch}})$9, and $f_{\mathrm{clk}} = 4 f$0 for dots 1, 2, and 3, and the weighted three-dot value was $f_{\mathrm{clk}} = 4 f$1 (Zwerver et al., 2022). Exchange with reservoirs was suppressed by a dot–reservoir tunnel rate of $f_{\mathrm{clk}} = 4 f$2, hyperfine-induced flips by $f_{\mathrm{clk}} = 4 f$3Si enrichment with $f_{\mathrm{clk}} = 4 f$4 ppm residual $f_{\mathrm{clk}} = 4 f$5Si, and spin–orbit mediated flips by the absence of a micromagnet and the use of adiabatic ramps (Zwerver et al., 2022).

In silicon MOS bucket-brigade transport, the dominant residual error was instead dephasing during detuning sweeps near charge-transfer regions, and the error changed by up to a twenty-fold variation as the ratio $f_{\mathrm{clk}} = 4 f$6 was tuned across the crossover where $f_{\mathrm{clk}} = 4 f$7 (Lin et al., 21 Jul 2025). The underlying four-level model shows that when $f_{\mathrm{clk}} = 4 f$8 and $f_{\mathrm{clk}} = 4 f$9, the effective qubit splitting becomes flat in detuning near the transition and both charge-noise sensitivity and parasitic spin-flip channels are suppressed (Lin et al., 21 Jul 2025).

For long conveyor paths in Si/SiGe, valley disorder dominates. In the random-alloy-disorder picture, the intervalley coupling $H = (\epsilon/2)\sigma_z + t \sigma_x,$0 forms a random complex field, and contours where $H = (\epsilon/2)\sigma_z + t \sigma_x,$1 and $H = (\epsilon/2)\sigma_z + t \sigma_x,$2 intersect at points where $H = (\epsilon/2)\sigma_z + t \sigma_x,$3 (Losert et al., 2024). This means that in the disordered regime, pockets of very small valley splitting are unavoidable along sufficiently long paths (Losert et al., 2024). The mitigation strategies explicitly demonstrated are heterostructure modification, vertical electric-field tuning, shuttling-velocity modulation, dot elongation, and path planning via channel shifting (Losert et al., 2024). In $H = (\epsilon/2)\sigma_z + t \sigma_x,$4 and $H = (\epsilon/2)\sigma_z + t \sigma_x,$5 Ge quantum wells, the combination of channel shifting, velocity modulation, and dot elongation brought $H = (\epsilon/2)\sigma_z + t \sigma_x,$6 shuttling infidelities below $H = (\epsilon/2)\sigma_z + t \sigma_x,$7 for the majority of disorder realizations (Losert et al., 2024).

A complementary result is that strong mitigation need not require precise knowledge of every valley near-degeneracy. Few-parameter trajectory shaping with as few as $H = (\epsilon/2)\sigma_z + t \sigma_x,$8 Fourier components reduced the median infidelity for $H = (\epsilon/2)\sigma_z + t \sigma_x,$9 shuttling to approximately $\epsilon$0 at $\epsilon$1, while $\epsilon$2 components at $\epsilon$3 reached approximately $\epsilon$4 (David et al., 2024). This suggests that a low-dimensional control basis can capture the dominant disorder-averaged error mechanisms without full microscopic retargeting.

At the hardware level, the 2026 cryogenic-electronics study combined disorder-informed valley maps, transistor-level noise simulations, and a discrete resistor ladder controlling period-wise velocity modulation (Romero et al., 22 Apr 2026). At $\epsilon$5 over $\epsilon$6, the optimized protocol achieved an average shuttling fidelity of $\epsilon$7, compared with $\epsilon$8 for a constant-resistor baseline, with active analog power $\epsilon$9 (Romero et al., 22 Apr 2026).

5. Shuttling as a gate primitive and control resource

Spin shuttling is not only a transport primitive. It can also serve as the mechanism by which two-qubit interactions are switched on and off. In a silicon triple-dot device, one qubit remained local while the second was shuttled between a sparse state $t$0 and a coupled state $t$1, changing the exchange interaction from $t$2 to $t$3 and producing an on/off ratio exceeding $t$4 (Noiri et al., 2022). With this shuttling-mode exchange control, a controlled-phase gate of fidelity $t$5 was demonstrated by interleaved randomized benchmarking (Noiri et al., 2022).

A distinct theoretical direction uses non-adiabatic shuttling between dots with inhomogeneous Landé $t$6-tensors to generate single-qubit gates without high-frequency driving fields (Liu et al., 16 Feb 2026). There the spin deviation acquired during a transfer is deliberately converted into a gate resource, and multiple rounds of bidirectional shuttling are summarized by an operator matrix that can implement Pauli-$t$7, Pauli-$t$8, and a generalized Hadamard gate after suitable idling times (Liu et al., 16 Feb 2026). This is conceptually different from exchange-gated shuttling, because the motion itself is the gate.

An even stronger claim appears in mobile-electron architectures: shuttling-based single-qubit gates can significantly outperform static EDSR-type pulsing by using larger spatial mobility to generate larger Rabi frequencies at smaller magnetic-field gradients (Pazhedath et al., 2024). In that framework, fidelities are bottlenecked by spin–valley physics rather than charge-noise-induced magnetic detuning, and quantum optimal control restores gate fidelities to at least $t$9 across broad parameter regions and device ensembles (Pazhedath et al., 2024). A plausible implication is that the boundary between “transport” and “gate” operations becomes blurred once motion is used as a first-class control knob.

A common misconception is that spin shuttling must minimize Zeeman inhomogeneity at all costs. Theory for strongly spin–orbit-coupled systems argues the opposite in an important regime: a large inhomogeneity of the Zeeman field can stabilize the coherence of a moving spin state by filtering out the dominant low-frequency contributions of the charge noise (Bosco et al., 2023). That conclusion aligns qualitatively with dressed-state shuttling proposals based on confinement modulation in germanium hole qubits, where motion-induced continuous driving suppresses low-frequency magnetic and electric noise (Nguyen et al., 1 May 2026).

6. Architectural implications and fault-tolerant thresholds

The systems literature treats shuttling as an architectural primitive rather than a mere device capability. In silicon dot arrays, short quantum links on the order of $\Delta\epsilon \approx 300~\mu\mathrm{eV}$00–$\Delta\epsilon \approx 300~\mu\mathrm{eV}$01 free up area for on-chip classical electronics between qubit blocks and reduce the number of off-chip interconnects (Zwerver et al., 2022). Conveyor-mode and bucket-brigade approaches are therefore often framed as complementary: bucket brigade is more tolerant to local disorder, whereas conveyor belts promise resource-efficient long channels with few global phases (Zwerver et al., 2022).

Digital-control proposals make this compatibility explicit. A cryogenic switch matrix plus first-order RC low-pass filters can synthesize near-sinusoidal conveyor waveforms from a small number of DC voltage levels, with wiring that scales with $\Delta\epsilon \approx 300~\mu\mathrm{eV}$02 rather than with qubit number (Nagai et al., 28 Feb 2025). For favorable parameters, simulations yield per-hop leakage below $\Delta\epsilon \approx 300~\mu\mathrm{eV}$03 and show that local waveform synthesis can keep power in the few mW range even for $\Delta\epsilon \approx 300~\mu\mathrm{eV}$04 qubits (Nagai et al., 28 Feb 2025). This is not a demonstration of a processor-scale machine, but it is a concrete control-theory argument that shuttling need not be wiring-prohibitive.

Surface-code analyses further weaken the assumption that shuttle errors must already be at the $\Delta\epsilon \approx 300~\mu\mathrm{eV}$05 level to be useful. In a SpinBus-motivated circuit-level model, the shuttle noise is introduced as an extra “bus” error location on ancillas before each CZ (Yenilen et al., 13 Mar 2025). At a standard circuit error rate $\Delta\epsilon \approx 300~\mu\mathrm{eV}$06, the bus thresholds are approximately $\Delta\epsilon \approx 300~\mu\mathrm{eV}$07 for unbiased depolarizing shuttle noise and approximately $\Delta\epsilon \approx 300~\mu\mathrm{eV}$08 for fully biased dephasing shuttle noise (Yenilen et al., 13 Mar 2025). The teraquop overhead baseline is approximately $\Delta\epsilon \approx 300~\mu\mathrm{eV}$09 physical qubits per logical qubit at $\Delta\epsilon \approx 300~\mu\mathrm{eV}$10, and the overhead remains modest up to bus error rates of approximately $\Delta\epsilon \approx 300~\mu\mathrm{eV}$11 in the unbiased case and approximately $\Delta\epsilon \approx 300~\mu\mathrm{eV}$12 in the biased case (Yenilen et al., 13 Mar 2025). This suggests that dephasing-dominated shuttling is substantially more fault-tolerant than naive per-hop targets alone would imply.

At the architectural-synthesis level, a one-dimensional shuttling bus tailored to the rotated surface code has been optimized with a mixed-integer model and a linear-time Zig-Zag heuristic (Escofet et al., 20 Oct 2025). Under the stated noise model, the synthesized architecture reaches logical error rates as low as $\Delta\epsilon \approx 300~\mu\mathrm{eV}$13 per round at code distance $\Delta\epsilon \approx 300~\mu\mathrm{eV}$14 (Escofet et al., 20 Oct 2025). A different application, the Parity Architecture, uses a constant-depth four-step schedule of global vertical shuttles and horizontal nearest-neighbor interactions to implement Parity QAOA on a repeated unit-cell lattice (Ginzel et al., 2024). These studies do not prove that large-scale shuttle-connected processors are solved, but they show that shuttling has already been elevated from device transport to compilation, scheduling, and threshold analysis.

Spin shuttling is therefore best understood not as a single protocol but as a family of transport-and-control mechanisms spanning adiabatic interdot transfer, moving-dot conveyor channels, motion-enabled gates, and hardware-aware optimal control. Across that family, the central technical theme is consistent: the charge motion itself is relatively easy to make adiabatic, while high-fidelity operation is determined by how well spin, valley, Zeeman inhomogeneity, and noise are co-designed.