Qubit Mapping Problem (QMP) Overview

• Qubit Mapping Problem (QMP) is the task of mapping logical circuits to hardware by assigning virtual qubits to physical ones and adding routing operations when needed.
• It involves optimizing objectives such as minimizing SWAP count, circuit depth, and latency using heuristic, solver-based, and hardware-aware strategies.
• Research in QMP explores diverse paradigms and calibration-aware methods to improve mapping efficiency across various device topologies.

Qubit Mapping Problem (QMP) is the quantum-compilation task of transforming a logical circuit into a hardware-compliant circuit on a device with restricted qubit connectivity, by assigning logical or virtual qubits to physical qubits and inserting routing operations when required. In the standard formulation, a two-qubit gate is directly executable only when its mapped physical operands are adjacent in the device coupling graph; otherwise, additional operations such as SWAPs must be introduced. Across the literature, QMP is also described as the joint qubit assignment and qubit routing problem, and in more general formulations as an assignment–routing–scheduling problem whose objectives include minimizing SWAP count, circuit depth, latency, makespan, and sometimes fidelity loss (Benbetka et al., 31 Oct 2025, Luteberget et al., 29 Aug 2025, Li et al., 2018).

1. Formal model and core constraints

Most formulations distinguish logical, virtual, or pseudo qubits from physical qubits. A logical circuit acts on a set such as $Q_{\text{logical}}$ or $Q=\{q_1,\dots,q_n\}$, while the hardware is modeled by a coupling graph $G=(V,E)$ or an integer relation $R_{\mathrm{hw}}$ over physical qubits. A current mapping, written for example as $\varphi : Q_{\text{logical}} \to Q_{\text{phys}}$, $A:Q\rightarrow V$, or $M:Logic\to Phys$, assigns each logical qubit to a physical location. A two-qubit gate is hardware-feasible only if the mapped pair lies on an allowed hardware edge, e.g. $(\varphi(q_1),\varphi(q_2)) \in R_{\mathrm{hw}}$ or $(M_k(q),M_k(q'))\in Edges$ (Benbetka et al., 31 Oct 2025, Molavi et al., 2022).

When this adjacency constraint is violated, routing is required. In the dominant NISQ setting, routing is implemented with SWAP gates that exchange the states of adjacent physical qubits and thereby update the mapping over time. Several papers explicitly note that a SWAP is typically decomposed into three CNOTs, so every routing decision increases two-qubit gate count, execution time, and exposure to error (Benbetka et al., 31 Oct 2025, Li et al., 2018, Molavi et al., 2022).

The problem is commonly decomposed into two tightly coupled subproblems. The qubit assignment problem selects an initial injective mapping from logical to physical qubits. The qubit routing problem inserts SWAPs or other routing primitives so that subsequent two-qubit gates become executable under the evolving mapping. This separation is conceptually useful, but many modern approaches treat the two components jointly because the quality of the initial assignment strongly affects routing cost, and routing operations themselves redefine the current assignment (Luteberget et al., 29 Aug 2025, Niu et al., 2020).

2. Optimization objectives and cost models

The classical objective is to minimize routing overhead, usually measured by SWAP count or added two-qubit gates. This remains central because two-qubit operations dominate error and latency on NISQ hardware. However, multiple papers argue that minimizing SWAP count alone is insufficient, because the operationally relevant quantity is often circuit depth, critical-path length, weighted depth, or real makespan (Zhang et al., 2020, Zhang et al., 2020, Luteberget et al., 29 Aug 2025).

Several formulations therefore make timing explicit. In duration-aware models, a circuit is a sequence $\mathcal{C}=[\{g_1,d_1\},\dots,\{g_N,d_N\}]$ with gate durations $Q=\{q_1,\dots,q_n\}$0, and execution time is the maximal gate finish time. Codar defines the execution time as

$Q=\{q_1,\dots,q_n\}$1

and optimizes this weighted depth rather than unweighted layer count (Zhang et al., 2020). The generalized branch-and-bound formulation similarly treats QMP as a schedule-based optimization problem and allows objectives that minimize makespan, minimize SWAP count, or combine both via

$Q=\{q_1,\dots,q_n\}$2

(Luteberget et al., 29 Aug 2025).

A further extension is calibration-aware cost modeling. The hardware-aware heuristic defines a composite distance matrix

$Q=\{q_1,\dots,q_n\}$3

where $Q=\{q_1,\dots,q_n\}$4 is the SWAP-distance matrix, $Q=\{q_1,\dots,q_n\}$5 is the SWAP-error matrix, and $Q=\{q_1,\dots,q_n\}$6 is the SWAP execution-time matrix. This converts QMP from a purely geometric routing problem into a hardware-aware optimization that explicitly trades off topological distance, path error, and path time (Niu et al., 2020).

This diversity of objectives is a persistent source of methodological variation. One line of work treats QMP primarily as a gate-count problem; another emphasizes latency, weighted depth, or critical-path length; a third incorporates calibration data. A plausible implication is that algorithm rankings are inherently metric-dependent rather than absolute.

3. Layering, scheduling, and temporal structure

A recurring issue in QMP research is whether circuits should be treated as fixed sequences of layers. The layered formulation partitions the circuit into gate groups such that all gates in a layer are independent and may be executed in the same time slot, with SWAPs allowed only between consecutive layers (Luteberget et al., 29 Aug 2025). This simplification reduces the search space, but it also restricts reordering and interleaving opportunities.

The branch-and-bound study makes this controversy explicit by comparing layered and non-layered QMP. It reports that ignoring fixed layering can significantly improve key performance indicators of the compiled circuit. When minimizing depth on small hardware graphs, the average depth increase caused by layering is approximately 37 time units on the Y graph, approximately 2.22 on the Linear graph, and approximately 0.24 on the Grid graph. When minimizing SWAPs, layering increases SWAP count by more than 3 on average on the Y graph, approximately 0.46 on the Linear graph, and approximately 0.36 on the Grid graph (Luteberget et al., 29 Aug 2025). This directly challenges the common assumption that fixed layering is a benign abstraction.

A related line of work emphasizes temporal criticality within the circuit DAG. Qlosure models the circuit with affine abstractions using QRANE, constructs the direct dependence relation $Q=\{q_1,\dots,q_n\}$7, computes its transitive closure $Q=\{q_1,\dots,q_n\}$8 with ISL, and assigns each gate a dependence weight

$Q=\{q_1,\dots,q_n\}$9

This weight quantifies how many downstream gates depend transitively on a gate and is then used inside a layered look-ahead cost function for SWAP selection (Benbetka et al., 31 Oct 2025).

Other methods expose temporal structure differently. Codar uses per-qubit locks to track qubit occupancy and exploit gate-duration differences; SlackQ distinguishes fixed slack from flexible slack and selects SWAP candidates that minimize the increment in total circuit time; the depth-aware SWAP insertion scheme ranks candidate mappings by the critical path of the full transformed circuit rather than by SWAP count alone (Zhang et al., 2020, Zhang et al., 2020, Zhang et al., 2020). Collectively, these results support a broader interpretation of QMP as a temporal as well as spatial optimization problem.

4. Major algorithmic paradigms

Heuristic front-layer routing remains the dominant practical paradigm. SABRE introduced a SWAP-based bidirectional heuristic search that uses a front layer $G=(V,E)$0, an extended set $G=(V,E)$1, a distance matrix on the coupling graph, and a decay term to trade off gate count and depth (Li et al., 2018). Many later tools inherit this structure, including LightSABRE and several industrial compiler stacks. In QuMeld, LightSABRE appears in lookahead and decay configurations, reflecting the continuing importance of this family (Keibas et al., 2 Mar 2026).

Exact and solver-based methods form a second major paradigm. The generalized branch-and-bound algorithm can solve layered or non-layered QMP, with or without explicit gate durations, and can prove optimality for the chosen objective on small instances (Luteberget et al., 29 Aug 2025). MaxSAT-based mapping encodes mapping variables $G=(V,E)$2 and routing variables $G=(V,E)$3 as Boolean constraints, with soft clauses rewarding no-op SWAP choices. On a 160-benchmark study, ex-mqt solved 4 benchmarks, tb-olsq solved 38, and satmap solved 109; on the 109 solved benchmarks, average heuristic cost ratios relative to satmap were 5.2 for mqth, 7.0 for sabre, and 3.6 for tket (Molavi et al., 2022). MLQM preserves solver optimality while accelerating OLSQ2-style search through machine-learned global pruning and adaptive local pruning, reporting an average solving speed-up ratio of 1.79 and an average advantage of 22% in terms of space complexity (Sun et al., 2024).

Symbolic and combinatorial data structures constitute a third paradigm. ZDD-based mapping represents families of legal mappings and parallel SWAP layers symbolically, uses maximal partitions of the gate sequence, and leverages ZDD family algebra to avoid explicit enumeration of the mapping space (Smith et al., 2019).

A fourth paradigm integrates hardware structure, timing, or noise directly into the mapper. The hardware-aware approach uses calibration-derived path error and path time in the distance metric and dynamically chooses between SWAP and Bridge insertion (Niu et al., 2020). Duostra introduces double-source optimal routing with occupied-time costs and combines it with Limitedly-Exhausitive Search or Shortest-Path Estimation for scheduling (Cheng et al., 2022). SlackQ and the depth-aware scheme prioritize circuit depth rather than raw SWAP count (Zhang et al., 2020, Zhang et al., 2020).

A fifth paradigm changes the problem itself by enlarging the allowed transformation space. PAS+PAM decomposes a circuit into $G=(V,E)$4-qubit blocks, synthesizes each block under multiple input-output permutations and local sub-topologies, and then maps the blocks while choosing permutations that jointly optimize synthesis cost and inter-block communication (Liu et al., 2023). Teleportation-based mapping goes further by treating quantum teleportation as a routing primitive that adds virtual edges to the coupling graph and can complement SWAP and bridge operations (Hillmich et al., 2020).

Learning-based methods now span both optimization and direct policy learning. MLQM learns to predict good depth and SWAP bounds for solver acceleration (Sun et al., 2024). CO-MAP formulates the qubit allocation problem as a combinatorial optimization problem over a program graph and a coupling graph, trains an RL policy to construct allocations, and then applies local search post-processing (Kulshrestha et al., 13 May 2026).

5. Hardware topologies, calibration, and architecture dependence

QMP is inseparable from hardware topology. The coupling graph may be a heavy-hex lattice, a modular square lattice, a line, a grid, a Y graph, or a fully connected trapped-ion device, and algorithm behavior changes substantially across these regimes. Qlosure evaluates on IBM Sherbrooke, where the heavy-hex topology gives each qubit degree $G=(V,E)$5, on Rigetti Ankaa-3, where the modular square-lattice tiles give degree $G=(V,E)$6, and on Sherbrooke-2X, a synthetic 256-qubit backend composed of two Sherbrooke tiles plus bridge qubits (Benbetka et al., 31 Oct 2025). QuMeld broadens this perspective by benchmarking across sixteen topologies and six mapping algorithms, explicitly motivated by the fact that no single mapper is uniformly best across circuit-topology pairs (Keibas et al., 2 Mar 2026).

Calibration data can further alter the mapping objective. The hardware-aware heuristic computes three Floyd–Warshall-derived matrices—topological SWAP distance, SWAP error, and SWAP execution time—and combines them into a weighted distance metric. It therefore treats per-edge CNOT success rates and gate times as first-class inputs to mapping rather than as post hoc diagnostics (Niu et al., 2020). This suggests that the same logical circuit may induce different optimal or near-optimal mappings on the same graph topology if calibration drifts.

Architectural adaptation can also be achieved by changing the routing primitive. Teleportation-based mapping observes that a Bell-pair “transportation channel” introduces virtual edges, enabling constant-overhead state transfer in principle and providing an alternative to linear-distance SWAP chains (Hillmich et al., 2020). PAS+PAM instead changes the circuit structure so that local subcircuits are resynthesized to fit hardware connectivity more naturally (Liu et al., 2023).

6. Benchmarking, empirical trends, and open issues

Empirical evaluation across recent work points to several broad trends. Dependence-driven heuristics can improve routing quality without sacrificing practical runtime: on 41 QASMBench circuits, Qlosure improves over LightSABRE by 7.40% fewer SWAPs and 3.96% shorter depth on Sherbrooke, and by 10.36% fewer SWAPs and 5.59% shorter depth on Ankaa-3 (Benbetka et al., 31 Oct 2025). On larger solver-based studies, MaxSAT-based mapping substantially outperforms prior exact approaches in scalability while also providing much lower routing cost than heuristics (Molavi et al., 2022). On large circuits with more than 50 qubits, Duostra reports an average 21.75% reduction in mapping cost over the virtual best among QMAP, t|ket>, Qiskit, and SABRE (Cheng et al., 2022). PAS+PAM reports circuits shorter by up to 68% and 18% on average than Qiskit, up to 36% and 9% on average than TKET, and up to 67% and 21% on average than BQSKit (Liu et al., 2023). CO-MAP reports a 65–85% reduction in SWAP overhead when compared to existing quantum compilers on datasets such as MQTBench and Queko (Kulshrestha et al., 13 May 2026).

These results also clarify several limitations. Exact methods still scale poorly on unrestricted instances, even when improved by MaxSAT or branch-and-bound relaxations (Molavi et al., 2022, Luteberget et al., 29 Aug 2025). Connectivity-only models ignore qubit-specific noise, crosstalk, and pulse-level effects; hardware-aware methods mitigate this partially but typically remain heuristic (Niu et al., 2020). Qlosure relies on affine lifting via QRANE and therefore assumes exploitable affine structure, even though dependence analysis still applies more broadly (Benbetka et al., 31 Oct 2025). Learning-based methods depend on training distributions and hardware-specific policies, which may require retraining or adaptation on new topologies (Sun et al., 2024, Kulshrestha et al., 13 May 2026).

A recurring misconception is that QMP is only a placement-and-routing problem over a static circuit. The accumulated evidence suggests a broader view: QMP is often an assignment–routing–scheduling problem, and in some formulations also an overview problem. Another misconception is that minimizing SWAP count is always the correct proxy objective. The layered versus non-layered results, the slack-aware and duration-aware studies, and the dependence-driven formulations all indicate that temporal structure can dominate raw gate count in realistic NISQ settings (Luteberget et al., 29 Aug 2025, Zhang et al., 2020, Benbetka et al., 31 Oct 2025).

As the field diversifies, benchmarking becomes a research problem in its own right. QuMeld addresses this explicitly as a modular framework supporting six qubit mapping algorithms, sixteen quantum computer topologies, and multiple evaluation metrics, with the stated goal of systematic comparison across hardware and workload diversity (Keibas et al., 2 Mar 2026). This suggests that future QMP research will increasingly depend not only on new algorithms, but also on standardized evaluation across topology, circuit family, and objective function.