Routed Circuit Decomposition: Methods & Applications

• Routed circuit decomposition is the factorization of circuits under specific routing constraints, ensuring subcomponents are route-compatible.
• It integrates synthesis and routing by embedding hardware topology or causal structure directly into the decomposition process, enhancing performance.
• The method finds applications in quantum compilation, superconducting circuits, photonic layouts, and network switching, offering practical optimization insights.

Searching arXiv for the cited papers and topic variants to ground the response. In current research usage, routed circuit decomposition denotes a family of decomposition problems in which a circuit, unitary, process, or network is factored into simpler components while preserving, exploiting, or explicitly representing routing structure. In quantum compilation, this ranges from topology-agnostic synthesis passes whose outputs are later mapped and routed, to coupled decomposition-and-routing methods that optimize native-basis depth under sparse connectivity. In other literatures, closely related constructions describe route-constrained quantum processes built from direct sums and tensor products, pivot-based reduction of superconducting circuit topologies, uniquely routed path-length-matched photonic layouts, path decompositions obtained by cutting Eulerian routes, and sparse decompositions of circuit-switch schedules into permutations (Krol et al., 2021, McKinney et al., 2023, Vanrietvelde et al., 2020, Smitham et al., 2024, Charles et al., 2012, Tan, 2019, Valls et al., 2020).

1. Terminological scope

Across these literatures, the common invariant is that decomposition is not performed on an abstract algebraic object alone. The object is decomposed together with a routing constraint: qubit connectivity, direct-sum sector flow, branch topology, waveguide trajectories, graph traversal order, or switch configurations. The resulting subcomponents are therefore not merely smaller; they are also route-compatible.

Domain	Decomposition object	Route constraint
Quantum compilation	$U \in U(2^n)$ or logical circuits	Hardware graph, native basis, SWAP overhead
Routed quantum processes	Linear maps, channels, supermaps	Relations between direct-sum sectors
Superconducting circuits	Lumped-element models	Node-loop or edge-network topology
Integrated photonics	3D waveguide layouts	Unique trajectories, separation, path length
Graph theory	Eulerian circuits in quartic planar graphs	Local avoidance of short subcycles
Circuit switching	Traffic matrices	Permutation configurations over time

A useful distinction in the quantum-compilation literature is between decomposition before routing and decomposition with routing. Exact unitary synthesis methods such as QSD and block-ZXZ produce structured gate lists over $\{R_y,R_z,\mathrm{CNOT}\}$ or equivalent bases, but assume “perfect qubits” and leave topology to later compiler passes (Krol et al., 2021, Krol et al., 2024). By contrast, MIRAGE, TAP-plus-token-swapping routing, architecture-aware adaptive compression, and star-topology Cartan synthesis incorporate hardware structure directly into the decomposition objective or the decomposition algebra itself (McKinney et al., 2023, Wagner et al., 2022, Rakyta et al., 2022, Wang et al., 20 Jun 2025).

This breadth also explains why the term is not tied to a single mathematical formalism. In some papers, routing is a graph-theoretic adjacency constraint; in others it is a relation on sector labels; in others it is literally the geometry of routed waveguides or the sequence of switch permutations. A plausible implication is that routed circuit decomposition is best understood as a structural perspective rather than a single algorithmic family.

2. Exact unitary synthesis before routing

A foundational strand treats routed decomposition as a downstream consequence of exact unitary synthesis. In the OpenQL-integrated QSD implementation, an arbitrary $n$-qubit unitary $U \in U(2^n)$ is decomposed into single-qubit $R_y(\theta)$, $R_z(\theta)$, and two-qubit CNOT gates, intended as a mid-end synthesis pass before mapping, routing, and scheduling (Krol et al., 2021). The core recursion applies Cosine–Sine Decomposition and demultiplexing, yielding at each level a circuit pattern consisting of a multiplexed $R_z$, a multiplexed $R_y$, another multiplexed $R_z$, and four $(n-1)$-qubit unitaries. Multi-controlled rotations are then realized by Gray-code ladders: a $\{R_y,R_z,\mathrm{CNOT}\}$0-control rotation uses $\{R_y,R_z,\mathrm{CNOT}\}$1 CNOTs and $\{R_y,R_z,\mathrm{CNOT}\}$2 single-qubit $\{R_y,R_z,\mathrm{CNOT}\}$3 gates.

This structure is directly relevant to routed decomposition even though topology is ignored during synthesis. The output has a regular interaction pattern in which one pivot qubit repeatedly couples to many controls. The baseline QSD CNOT count is

$\{R_y,R_z,\mathrm{CNOT}\}$4

while the optimized variant that stops at two-qubit gates gives

$\{R_y,R_z,\mathrm{CNOT}\}$5

The same implementation reports that for $\{R_y,R_z,\mathrm{CNOT}\}$6, OpenQL produces about $\{R_y,R_z,\mathrm{CNOT}\}$7 CNOTs and about $\{R_y,R_z,\mathrm{CNOT}\}$8 million total gates, compared with about $\{R_y,R_z,\mathrm{CNOT}\}$9 million CNOTs and about $n$0 million total gates for Qubiter’s CSD-based flow; decomposition time is also $n$1–$n$2 faster up to $n$3 qubits (Krol et al., 2021). These numbers matter for routed decomposition because CNOT count is the main cost driver for later mapping and SWAP insertion.

The block-ZXZ program refines the same topology-agnostic paradigm. Its top-level factorization writes an $n$4-qubit unitary in terms of block-diagonal $n$5, a central block-ZXZ mixing term, and another block-diagonal factor, then demultiplexes each block into smaller unitaries plus uniformly controlled $n$6 gates (Krol et al., 2024). The recursion remains QSD-like—four $n$7-qubit unitaries and three multiplexors per level—but replaces the central uniformly controlled $n$8 by a block-ZXZ central multiplexor that absorbs more two-qubit gates. The resulting CNOT count is

$n$9

which improves on optimized QSD by

$U \in U(2^n)$0

CNOT gates, and gives a generic 3-qubit exact decomposition with $U \in U(2^n)$1 CNOT gates rather than $U \in U(2^n)$2 (Krol et al., 2024).

Both methods are therefore best viewed as topology-agnostic front ends to routed circuit decomposition. Their contribution is not hardware feasibility per se, but a recursively regular interaction skeleton—multiplexed rotations, Gray-code control ladders, and small exact leaf circuits—that later routing passes can exploit or, if necessary, must undo.

3. Coupled decomposition and routing on constrained quantum hardware

A second strand removes the separation between synthesis and routing. MIRAGE is explicit on this point: it treats transpilation as a collaborative design problem in which decomposition into native basis gates and connectivity-constrained routing are optimized together for iSWAP-family hardware (McKinney et al., 2023). Its key abstraction is the mirror gate $U \in U(2^n)$3, together with monodromy-polytope estimates of the minimum number of basis gates required for a two-qubit unitary. In the $U \in U(2^n)$4 basis, the paper emphasizes that CNOT and CNS $U \in U(2^n)$5 CNOT$U \in U(2^n)$6SWAP have the same circuit-depth cost; more generally, mirror gates can absorb SWAPs that would otherwise be explicit routing overhead. For $U \in U(2^n)$7 with $U \in U(2^n)$8, Haar-weighted Weyl-chamber coverage rises from $U \in U(2^n)$9 to $R_y(\theta)$0 when mirrors are allowed. On heavy-hex topologies, MIRAGE reports average depth reduction $R_y(\theta)$1, weighted depth reduction $R_y(\theta)$2, average SWAP reduction $R_y(\theta)$3, and weighted SWAP reduction $R_y(\theta)$4; on a $R_y(\theta)$5 square lattice, the corresponding figures are $R_y(\theta)$6, $R_y(\theta)$7, $R_y(\theta)$8, and $R_y(\theta)$9 (McKinney et al., 2023).

A related but distinct decomposition treats routing itself as a two-level problem. The TAP-plus-token-swapping framework decomposes qubit routing by SWAP insertion into a global allocation subproblem and a family of token-swapping subproblems (Wagner et al., 2022). The token allocation problem is solved as a binary program whose objective is a lower bound on the number of SWAPs, strengthened by subgraph-isomorphism inequalities; the transition between consecutive allocations is then realized by exact or approximate token swapping. On real IBM hardware for $R_z(\theta)$0 QAOA MaxCut on an 8-node ring, the routed circuit produced by this method uses $R_z(\theta)$1 two-qubit gates and depth $R_z(\theta)$2, compared with $R_z(\theta)$3 and $R_z(\theta)$4 for TKET and $R_z(\theta)$5 and $R_z(\theta)$6 for StochasticSwap, with measured approximation ratio $R_z(\theta)$7 versus $R_z(\theta)$8 and $R_z(\theta)$9 (Wagner et al., 2022). Here routed circuit decomposition is literally a decomposition of a compiler optimization problem into route planning and route realization.

Adaptive circuit compression provides a third architecture-aware route. SQUANDER replaces the discrete search over gate placements by continuous optimization over circuits built from controlled-$R_z$0 blocks and then sequentially removes two-qubit blocks while re-optimizing the remainder (Rakyta et al., 2022). Connectivity enters by restricting which qubit pairs may host two-qubit building blocks. This makes the method usable either as direct architecture-aware synthesis or as post-routing compression of an already routed circuit. On a 5-qubit linear chain, the example 4gt13_91 is reported at $R_z$1 CNOTs for SQUANDER, versus $R_z$2 for QSearch LEAP, $R_z$3 for QFAST, and $R_z$4 for Qiskit (Rakyta et al., 2022). The route constraint is therefore not enforced through SWAP templates alone, but through the admissible parameterized ansatz.

Hardware-specific routed decomposition can also be algebraic rather than graph-search-based. For a star-shaped NV-center-plus-nuclear-spin processor, Cartan decomposition is tailored to the Lie algebra generated by the hardware Hamiltonian, so that arbitrary logical unitaries are factored into nuclear single-qubit rotations and diagonal multi-qubit phase gates implemented through the central electron spin (Wang et al., 20 Jun 2025). In that architecture, there is no direct nuclear–nuclear coupling, and routed decomposition avoids explicit SWAP networks by using global diagonal control as a mediated interaction resource. The paper reports a $R_z$5 optimized $R_z$6 gate with fidelity $R_z$7, a CNOT between two nuclear spins with total time $R_z$8 and fidelity $R_z$9, and random-CNOT experiments in which the decomposed circuit depth is roughly independent of the logical circuit depth and scales mainly with circuit width (Wang et al., 20 Jun 2025).

Taken together, these approaches show that routed circuit decomposition can mean at least three different things in constrained quantum hardware: absorbing routing into basis selection, decomposing routing into optimization subproblems, or deriving a hardware-native factorization from the device’s control algebra.

4. Routed quantum processes and causal structure

A more formal meaning of routed circuit decomposition appears in the theory of routed linear maps and routed quantum circuits. Standard circuit formalisms handle subsystem composition through tensor products, but several process-theoretic settings require nontrivial blends of direct sums and tensor products, such as one-particle subspaces or causal decompositions of unitary channels (Vanrietvelde et al., 2020). The canonical example is

$R_y$0

which is the one-particle sector of two lines but not the full $R_y$1. Routed linear maps attach a relation $R_y$2 to a linear map $R_y$3, restricting which input sectors may connect to which output sectors. This yields practical domains and codomains, practical isometries and unitaries, and a consistent dagger symmetric monoidal category of routed maps. An important notion is the accessible space of a slice of a routed circuit: it is not simply the tensor product of the visible wires, but the subspace selected by all routes in the full diagram (Vanrietvelde et al., 2020).

Within this framework, routed circuit decomposition becomes a factorization of a process into routed components whose sector relations make direct-sum constraints explicit. The formalism accommodates superpositions of trajectories, superpositions of channels, and causal decompositions of unitaries that cannot be expressed as ordinary standard-circuit decompositions without enlarging Hilbert spaces or losing unitarity (Vanrietvelde et al., 2020). Extended circuit diagrams of Lorenz and Barrett are recovered as a special case in which routes are index matchings.

The 2025 QC-QC result turns this into a constructive existence theorem for indefinite causal order. For every $R_y$4, a single routed graph $R_y$5 suffices to obtain a routed circuit decomposition for any $R_y$6-party quantum circuit with quantum control of causal order (Grothus et al., 11 Jul 2025). The routed graph is built from agent nodes $R_y$7, internal nodes $R_y$8, and index sets $R_y$9 that encode which parties have already acted and which party acts next. Validity is established through bi-univocality and branch-graph analysis, and the associated skeletal supermap is then fleshed out by routed isometries corresponding to the QC-QC internal maps $R_z$0 and adapter supermaps at the agent nodes. The result is that every QC-QC, including the quantum switch and higher-party generalizations, admits a routed circuit decomposition on a universal template graph (Grothus et al., 11 Jul 2025).

This process-theoretic literature therefore uses “routing” in a stronger sense than hardware mapping. It refers to fine-grained information flow through direct-sum sectors, branch choices, and causal-control registers. A plausible implication is that routed circuit decomposition unifies hardware routing and causal routing only at a high level; technically, the two use different state spaces, different composition laws, and different notions of feasibility.

5. Physical-layout and network formulations

Outside quantum compilation proper, routed circuit decomposition often refers to extracting or designing physical topology under explicit routing constraints. In superconducting lumped-element models, the central object is the node–loop network matrix $R_z$1, whose entries encode how inductive loops are routed between capacitive nodes (Smitham et al., 2024). By passing to a tree–cotree basis and the edge network matrix

$R_z$2

the decomposition becomes a sequence of row and column pivoting operations. Row pivots correspond graphically to removing a capacitive tree edge from the tree and placing it in parallel with an inductive edge; column pivots contract an inductive cotree edge and place it in series with a capacitive edge. The resulting “fundamental form” isolates harmonic LC modes, removes free modes by Schur complements, and separates the nonlinear Josephson-junction and phase-slip sectors from auxiliary linear modes (Smitham et al., 2024). The same network-matrix machinery is then used for model extraction from full-wave electromagnetic simulation, because the DC block of the hybrid response matrix directly yields $R_z$3.

In three-dimensional integrated photonics, routed decomposition is geometric rather than algebraic. The path-length-matched 8-waveguide pupil-remapping beam combiner is decomposed into uniquely routed waveguides connecting a hexagonal input arrangement to a linear output array, subject to minimum separation, fabrication depth, and non-cross-through writing constraints (Charles et al., 2012). The design first used cubic splines, then piecewise circular arcs, and matched physical path lengths to within $R_z$4 in the design trajectories. Interferometric measurements on the fabricated device showed optical path-length matching to within $R_z$5. The optimized design used radii of curvature greater than $R_z$6, a minimum waveguide separation of $R_z$7, and a $R_z$8 chip length (Charles et al., 2012). Here routed decomposition means that the device-level circuit is decomposed into individual trajectories whose geometry simultaneously satisfies routing, loss, and phase constraints.

A network-scheduling variant appears in high-speed circuit switching. A normalized traffic demand matrix $R_z$9 is decomposed into a sparse sum of permutation matrices,

$(n-1)$0

where each permutation is a switch configuration and each $(n-1)$1 is its duration (Valls et al., 2020). Classical Birkhoff decomposition gives exact realizability but poor sparsity; the revisited theory establishes that with an admissible subset of permutations, Birkhoff-type algorithms achieve an $(n-1)$2-approximate decomposition with $(n-1)$3 permutations, and Birkhoff+ combines Frank–Wolfe direction selection with Birkhoff step sizing to obtain sparse decompositions using one LP per configuration (Valls et al., 2020). In circuit-switch performance experiments, Birkhoff+(10) achieves about $(n-1)$4 higher throughput than Eclipse at $(n-1)$5, while Birkhoff+ and Birkhoff+(10) are about an order of magnitude faster than Solstice and Eclipse for small $(n-1)$6 (Valls et al., 2020). The circuit here is not a quantum circuit, but the decomposition principle is the same: global demand is represented as a sparse sequence of routed configurations.

These physical-layout literatures show that routed circuit decomposition is not inherently computational. It can equally describe topological reduction, geometric embedding, or schedule sparsification, provided route compatibility is part of the decomposition itself.

6. Abstract graph models, complexity, and open problems

At a combinatorial extreme, routed circuit decomposition becomes decomposition of a route into prescribed segments. For connected quartic planar graphs, a 4-locally self-avoiding Eulerian circuit exists if and only if the graph does not contain $(n-1)$7 as a subgraph (Tan, 2019). This route can then be cut into paths of prescribed lengths: a quartic planar graph of order $(n-1)$8 admits a decomposition into $(n-1)$9 paths with $\{R_y,R_z,\mathrm{CNOT}\}$00 copies of $\{R_y,R_z,\mathrm{CNOT}\}$01 if and only if

$\{R_y,R_z,\mathrm{CNOT}\}$02

In particular, every connected quartic planar graph of even order admits a $\{R_y,R_z,\mathrm{CNOT}\}$03-decomposition (Tan, 2019). The same “route first, cut later” logic reappears in more concrete routed decomposition problems, although there the route is usually a sequence of hardware interactions, sector transitions, or switch configurations rather than an Eulerian traversal.

Across the surveyed literatures, the dominant limitations are different but structurally similar. Exact generic quantum synthesis scales exponentially in circuit width: QSD has gate counts $\{R_y,R_z,\mathrm{CNOT}\}$04 and decomposition time roughly $\{R_y,R_z,\mathrm{CNOT}\}$05, while block-ZXZ, though more CNOT-efficient, remains above the lower bound $\{R_y,R_z,\mathrm{CNOT}\}$06 and does not optimize depth or topology directly (Krol et al., 2021, Krol et al., 2024). MIRAGE’s monodromy analysis is limited to two-qubit blocks, and its routing-plus-decomposition decisions remain heuristic even though they are physically informed (McKinney et al., 2023). SQUANDER’s continuous optimization is powerful on 3–5 qubits but expensive for larger blocks (Rakyta et al., 2022). The NV-center Cartan approach is exponential in $\{R_y,R_z,\mathrm{CNOT}\}$07 in the generic case and is therefore suited primarily to few-qubit central-spin registers (Wang et al., 20 Jun 2025).

In the process-theoretic domain, routed circuits now cover all QC-QCs, but whether all purifiable process matrices admit routed circuit decompositions remains unresolved (Grothus et al., 11 Jul 2025, Vanrietvelde et al., 2020). In superconducting model extraction, the methods assume reciprocal, lossless linear parts and no ideal transformers (Smitham et al., 2024). In photonics, path-length matching remained highly manual and optical mismatches were still tens of microns despite sub-micron geometric matching (Charles et al., 2012). In graph theory, extensions beyond quartic planar graphs or beyond path lengths up to $\{R_y,R_z,\mathrm{CNOT}\}$08 edges remain open (Tan, 2019).

These recurrent limitations indicate that routed circuit decomposition is usually successful when route structure is regular enough to be represented explicitly—Gray-code ladders, mirror-gate choices, branch graphs, pivotable network matrices, uniquely parameterized waveguide paths, or Eulerian tours. When the route space is high-dimensional, noisy, or only weakly structured, decomposition remains possible but typically loses optimality guarantees, scalability, or both.