Quantum Circuit Routing

• Quantum circuit routing is the process of mapping high-level circuits to physical devices, ensuring qubit interactions occur only between adjacent qubits.
• It employs heuristic, analytical, and AI-driven methods to optimize key metrics such as SWAP count, circuit depth, and overall circuit fidelity.
• Recent advancements using reinforcement learning and structure-aware techniques have demonstrated 10–20% SWAP overhead reductions and scalable performance improvements.

Quantum circuit routing refers to the transformation of a high-level quantum circuit into an implementable form that respects the limited qubit connectivity of real hardware architectures. Since near-term devices restrict two-qubit operations to physically adjacent qubits, the routing process inserts SWAP gates or other qubit movement operations to ensure that all intended interactions become executable. The goal is typically to minimize the overhead in gate count, circuit depth, or hardware-specific cost metrics induced by these additional routing operations.

1. Foundations of the Qubit Routing Problem

Given a quantum circuit acting on $n$ logical qubits and a physical device described by a connectivity (coupling) graph $G = (V, E)$, the routing transformation enforces that every two-qubit operation in the compiled circuit acts only on physically adjacent qubits $(i,j)\in E$. The formal optimization objectives are:

• SWAP count minimization: Minimize the total number of SWAP gates inserted.
• Depth minimization: Minimize the (critical path) depth increment due to routing.
• Fidelity maximization: For noisy hardware, maximize expected circuit output fidelity, accounting for gate error rates and coherence limitations.

The problem is NP-hard for general circuits and device topologies (Childs et al., 2019, Kattemölle et al., 18 Mar 2025), motivating a breadth of heuristic, analytical, and optimal approaches.

2. Parallel Routing Principles and Analytical Bounds

Routing can be formulated as the problem of implementing a required (partial) permutation $\pi: V \to V$ of logical to physical qubits using hardware-native two-qubit gates (SWAPs). The routing via matchings framework (Childs et al., 2019) seeks to decompose $\pi$ into a minimal-depth sequence of edge-disjoint SWAP layers (matchings), with sharp bounds known for paths, grids, and their hierarchical products:

• For a path $P_n$, the routing number is $n$.
• For a two-dimensional $n_1 \times n_2$ grid, $P_{n_1} \times P_{n_2}$, the routing number is $n_1+2n_2$.
• General partial routing via matchings yields polynomial depth and computational complexity $G = (V, E)$0 for $G = (V, E)$1 qubits, lookahead $G = (V, E)$2, and $G = (V, E)$3 gates (Ren et al., 2021).

Depth-oriented placement and routing heuristics employ these parallel protocols to reduce makespan, while being interleaved with greedy or incremental mapping strategies for circuit layers (Childs et al., 2019, Ren et al., 2021).

3. Algorithmic and Heuristic Routing Methods

3.1 Layerwise Local Heuristics

Popular transpiler implementations (SABRE, t|ket〉, Qiskit) decompose circuits into layers and apply greedy minimization of the sum of distances between qubits targeted for immediate execution (Pina-Canelles et al., 6 Feb 2025, Ren et al., 2021). The SABRE family, for example, uses “basic+decay” to prioritize basic distance reduction for front-layer gates, penalizing repeated use of the same SWAP edges to encourage parallelism and depth efficiency. Depth scaling is asymptotically optimal: $G = (V, E)$4 in 1D, $G = (V, E)$5 in 2D. Advanced heuristics like Nuwa (Ren et al., 2021) employ finite-horizon reward functions and shallow Monte Carlo rollouts for more future-aware choices, further reducing CNOT count and increasing scalability.

3.2 Pruning and Approximation for Fidelity

Recent methods integrate routing cost into circuit pruning, omitting gates that incur more fidelity loss (via SWAPs and decoherence) than their utility justifies. The routing-aware pruning approach (Escofet et al., 19 Jan 2026) uses the fidelity loss from SWAPs (parameterized by error rates and physical distance) and prunes small-angle controlled rotations if their expected fidelity cost from routing exceeds the intrinsic gate fidelity: $G = (V, E)$6 This procedure can halve two-qubit gate counts and yield up to 48% fidelity improvement for large circuits.

3.3 Entanglement-Mediated and Nonlocal Routing

Resource state integration, e.g., Bell/EPR pairs, enables direct remote gates in addition to SWAP-based movement (Padda et al., 2023). Augmenting the coupling graph with “virtual” edges between data qubits connected via EPR ancilla provides a compile-time trade-off between local SWAP counts and the fixed cost of remote gates, with the optimal choice determined by comparing SWAP-chain cost to the nonlocal operation’s gate and error cost.

4. Reinforcement Learning and Tree-Search-Based Routing

Deep RL and MCTS methods have recently advanced quantum routing significantly. AlphaRouter (Tang et al., 2024) and RL-based transpiler passes (Kremer et al., 2024, Pozzi et al., 2020) treat circuit routing as an MDP, encoding the state as the current mapping and pending gates. Actions correspond to allowed SWAPs; rewards penalize SWAPs and reward execution progress: $G = (V, E)$7 Policy/value networks (typically Transformer or MLP architectures) predict SWAP choices with the lowest anticipated future cost. MCTS is used during training to refine the policy by exploring rollouts guided by a learned value function. Experimental results demonstrate 10–20% reductions in SWAP overhead and depth relative to SABRE/t|ket〉 on a variety of topologies and circuit families (Tang et al., 2024, Kremer et al., 2024). RL agents generalize effectively to unseen benchmarks and topologies and deliver practical inference times for circuits up to 133 qubits.

5. Structure-Aware, Analytical, and Optimal Routing

When the logical circuit or device has regularity, structure-aware methods can deliver substantial improvements. Examples include:

5.1 Standard-Cell and Layout-Aware Routing

For circuits built from regular, repeating gate patterns, a standard tile/cell framework (Dobbs et al., 2022) enables closed-form SWAP and depth resource counts. Arithmetic subcircuits are implemented in “cells” (e.g., cubes for Toffoli gates) that guarantee zero internal SWAPs and straightforward O(n) scheduling. Overall router complexity is O(n²) for $G = (V, E)$8-bit multipliers, with 3–4x reductions in depth and gate count over generic routers.

5.2 Spatiotemporally Periodic and SMT-Based Routing

For tileable, periodic circuits (common in Trotterized lattice and condensed matter simulations), the global routing problem decomposes into routing a single tile, formulated as an SMT optimization (Kattemölle et al., 18 Mar 2025). This produces optimal depth/SWAP solutions that scale independently of the overall circuit size, enabling SWAP-free circuits even for highly nontrivial lattices such as kagome and snub-square geometries.

$G = (V, E)$9

The per-tile approach outperforms black-box routers by several orders of magnitude for circuit size and runtime.

5.3 Line-Graph and Lattice-Specific Routing

When the logical circuit’s coupling graph is a line graph and the hardware coupling graph is a corresponding heavy graph, deterministic, structure-exploiting routing can be performed in O(|E|^2) time with a strict bound of at most 2 SWAPs per logical two-qubit gate (Kattemölle et al., 2023). Empirically, these routes outperform general-purpose routing in quantum simulation of planar lattices, reducing both SWAP count and classical routing time.

6. Routing for Quantum LDPC Codes and Error Correction

Syndrome extraction circuits for quantum LDPC codes often require nonlocal interactions. Universal strategies systematically reduce hardware connectivity requirements by leveraging the short loops inherent to the code’s Tanner graph (Zhao et al., 31 Aug 2025). Routings replace direct data–ancilla links by ancilla-mediated detours, e.g., mapping a connection to a 4-cycle path, at the cost of increased syndrome circuit depth but without loss of code distance. Tunable parameters enable $(i,j)\in E$0–$(i,j)\in E$1 reduction in long-range coupler count, making LDPC and high-rate codes more practical for near-term hardware.

7. Benchmarking, Metrics, and Hardware-Aware Trade-offs

Quantitative analyses of routing methods employ several metrics:

• SWAP count and depth overheads: Analytical and empirical studies reveal depth-scaling regimes and crossover points for various heuristics; parallel-aware “basic+decay” routing recovers optimal depth scaling in 1D/2D (Pina-Canelles et al., 6 Feb 2025).
• Circuit fidelity: End-to-end fidelity $(i,j)\in E$2 combines SWAP-induced error, idle time decoherence (via $(i,j)\in E$3), and device error models:

$(i,j)\in E$4

The optimum routing strategy depends critically on problem size, device parameters, and noise regime.

• Runtime and scalability: RL and structure-aware methods routinely achieve polynomial runtime and practical inference times for $(i,j)\in E$5 qubits, whereas exact methods scale only to $(i,j)\in E$6.

In summary, the quantum circuit routing literature encompasses a spectrum from analytical parallel scheduling, dynamic mapping algorithms, resource-state-enabled routing, and classical/AI-driven heuristic search, to optimal SMT-based tiling for regular problems. Method choice is dictated by circuit class, device topology, error budget, and required scalability, with the field continuing to evolve rapidly as hardware and algorithmic paradigms advance.