Neural-ART: Digital PIM Accelerator

• Neural-ART is a digital PIM accelerator that integrates storage and computing to minimize costly data movement during deep neural network training.
• It introduces a novel 1T-1R SOT-MRAM cell and a streamlined 4-step full adder, enabling precise floating-point operations in-memory.
• Evaluations on benchmarks like LeNet-5/MNIST show up to 3.3× energy and 1.8× latency improvements over FloatPIM, emphasizing its practical efficiency.

Neural-ART is a SOT-MRAM-based digital process-in-memory (PIM) accelerator for deep neural network training with floating-point precision. It is designed around a specific systems problem: in DNN training, the dominant cost is often not arithmetic alone but repeated movement of weights, activations, gradients, and intermediate values between memory and compute units. Neural-ART addresses that cost by executing logic and arithmetic directly in or near memory, while avoiding the limited precision of analog PIM and the procedural overhead of earlier digital PIM approaches. Its defining contributions are a new 1T-1R SOT-MRAM cell, a 4-step, 4-cell full adder, and explicit support for floating-point addition and multiplication within a digital in-memory execution flow (Wang et al., 2020).

1. Motivation and problem formulation

Neural-ART is motivated by the training cost of modern DNNs. The paper uses ResNet-50 as an illustrative case: a single forward pass requires about 4 GFLOPs, while full training can require around $10^{18}$ FLOPs, taking 14 days on an NVIDIA M40 GPU. In this setting, repeated memory traffic for weights and intermediate values can dominate the effective cost of training, which makes PIM attractive because it keeps computation close to stored data (Wang et al., 2020).

The design is positioned against two established limitations in prior PIM research. First, analog/mixed-signal PIM can reduce movement costs but typically suffers from limited precision, which is problematic for training. Second, digital PIM avoids analog precision issues, but many prior designs rely on memory technologies that support only a limited set of logic functions, forcing complicated multi-step procedures for arithmetic, especially floating-point arithmetic. The paper further notes that earlier SOT-MRAM or ReRAM training accelerators may require many intermediate cells and steps, may support only restricted logic, or may overwrite operands that must be preserved for later stages of training.

A common misconception in the area is that PIM training necessarily entails either analog approximation or reduced precision. Neural-ART is explicitly framed as a counterexample: it argues that floating-point-capable PIM is feasible if the memory technology provides sufficient logic expressiveness and sufficiently flexible cell-level control. This is central to the paper’s claim that training-oriented PIM should be evaluated not only by proximity to memory, but also by whether it preserves the numerical properties needed for training.

2. Architectural organization

At the architectural level, Neural-ART is built around a SOT-MRAM PIM array and three core innovations: a new 1T-1R SOT-MRAM cell, a new full adder design, and floating-point arithmetic support for training. The array stores network data and also executes logic in place, so the memory substrate functions simultaneously as storage, arithmetic substrate, and cache for intermediate values (Wang et al., 2020).

The execution model is explicitly in-/near-memory. Arithmetic proceeds by reading operands from MRAM cells, using cell write physics to realize Boolean logic, and writing results back into nearby MRAM cells that also serve as reusable caches. The paper emphasizes column-wise parallelism: operands and results may occupy different columns, and intermediate caches can be reused across sequential operations. This differs from designs that require operands, intermediate values, and final results to remain in the same row.

The broader training workflow maps naturally onto this organization. During forward propagation, weight-activation multiplies and accumulations are executed using in-memory floating-point multiplication and addition. During backpropagation, gradient calculations reuse the same arithmetic substrate. During weight updates, computed gradients are applied directly in memory, which reduces movement of weights between memory and a separate compute unit. The paper also states that memory locations can be flexibly reassigned, improving cell reuse and lowering the number of required intermediate storage cells.

This architectural organization suggests a design philosophy in which memory layout, temporary storage, and arithmetic sequencing are co-designed rather than treated as separate problems. A plausible implication is that Neural-ART’s contribution is as much about execution flexibility as about individual arithmetic primitives.

3. SOT-MRAM cell and logic substrate

The accelerator’s basic storage-and-logic primitive is a 1T-1R SOT-MRAM cell with four control terminals: WL, RBL, WBL, and SL. The paper introduces this cell as a hybrid of two prior approaches. A 2T-1R cell offers row-parallel writing flexibility but uses more transistors, whereas a single-MTJ cell is denser but has less flexible write-direction control and incurs extra write-step overhead. The proposed 1T-1R cell aims to preserve row-parallel writing flexibility, reduce transistor count, improve density and write speed, and maintain computation flexibility (Wang et al., 2020).

During read, WL is high, RBL is biased negatively, SL is grounded, and read current flows from SL to RBL. The paper gives $-100\ \text{mV}$ as an example negative read bias. This negative RBL bias raises the switching threshold and prevents accidental writes during read. During write/compute, WL is high, RBL is driven by $V_b$ or $0$, and WBL and SL are set to establish the required voltage difference and current direction. Under this control, the cell can realize logic functions such as AND, OR, and XOR during the write process.

This logic support is the basis of the paper’s improved full adder. The 1-bit full adder is defined as

$$S(R)=X\oplus Y\oplus Z,\qquad Z' = XY + Z(X\oplus Y).$$

Here $X$ and $Y$ are operands, $Z$ is the input carry, and $Z'$ is the output carry. The design preserves the original operands $X$ and $-100\ \text{mV}$0, uses only 4 steps, and requires only 4 memory cells. The sequence is: copy $-100\ \text{mV}$1, $-100\ \text{mV}$2, and $-100\ \text{mV}$3 into MRAM cache cells; compute $-100\ \text{mV}$4 and $-100\ \text{mV}$5 in parallel; copy $-100\ \text{mV}$6 next to $-100\ \text{mV}$7 and compute $-100\ \text{mV}$8; then compute both $-100\ \text{mV}$9 and $V_b$0. The paper contrasts this with FloatPIM, which requires 13 steps and 12 cells for a 1-bit full adder.

The significance of this full adder is not merely local gate reduction. It is the enabling primitive for larger floating-point operators, because the cost of in-memory digital arithmetic is strongly shaped by how efficiently intermediate carries and partial sums can be represented without destroying source operands.

4. Floating-point arithmetic support

A distinguishing feature of Neural-ART is explicit support for floating-point addition and floating-point multiplication inside a digital PIM flow. The paper identifies exponent alignment as the dominant cost in floating-point addition and introduces a search method to determine the required shift. If an input bit matches the stored exponent-difference bit, the read current is low; otherwise, it is high. This current-based sensing is used to determine alignment. The paper states that exponent alignment scales as $V_b$1 in the proposed design, compared with roughly $V_b$2 in FloatPIM (Wang et al., 2020).

The reported latency and energy models for floating-point addition are:

$V_b$3

Here $V_b$4 is the number of exponent bits and $V_b$5 is the number of mantissa bits.

For floating-point multiplication, the dominant cost is mantissa multiplication. Neural-ART implements this as an in-memory shift-and-add process: the multiplicand is multiplied by each bit of the multiplier, partial products are shifted, and the proposed full adder accumulates them. Other stages are implemented with in-memory AND, OR, and XOR operations. The reported models are:

$V_b$6

The practical importance of these arithmetic units lies in how they support the training loop. Forward propagation, backpropagation, and weight updates all reuse the same floating-point operations in place. This is precisely where Neural-ART differs from training accelerators that rely on low-precision approximation: it treats floating-point support as a first-class architectural requirement rather than as an external fallback.

5. Evaluation and reported results

Neural-ART is evaluated against FloatPIM, described as a state-of-the-art ReRAM-based PIM DNN training accelerator. The evaluation uses LeNet-5, MNIST, 32-bit floating point, and a $V_b$7 subarray. The authors use NVSim with SOT-MRAM parameters from prior work and a current sense amplifier model to estimate energy, latency, and area (Wang et al., 2020).

Aspect	Reported value	Context
Precision	32-bit floating point	Training evaluation
Baseline	FloatPIM	ReRAM-based PIM training accelerator
Subarray size	$V_b$8	Evaluation setup
Energy improvement	3.3×	MAC and full training
Latency improvement	1.8×	MAC and full training
Area improvement	2.5×	Compared with baseline

The paper reports that the proposed accelerator achieves 3.3× lower energy, 1.8× lower latency, and 2.5× lower area than FloatPIM, both at the MAC level and for end-to-end LeNet training. The paper attributes these gains to fewer cell-switching steps for arithmetic, fewer memory cells needed for intermediate values, more flexible placement and reuse of intermediate results, and lower write-current requirements of SOT-MRAM relative to the ReRAM baseline.

An additional implementation note is that latency is dominated by cell switching time. The paper therefore remarks that using an ultra-fast SOT-MRAM switch could reduce MAC latency by an additional 56.7%. This does not alter the evaluated headline results, but it clarifies where the remaining bottleneck lies.

These results should be interpreted with the stated scope of the evaluation. The benchmark is limited to LeNet-5/MNIST, and the hardware organization is chosen to be similar to FloatPIM for fairness. The reported gains therefore establish efficiency at a controlled operating point, not universal superiority across all training workloads.

6. Significance, limitations, and relation to adjacent PIM designs

Neural-ART is significant because it addresses a specific gap in PIM accelerator design: the combination of digital correctness, floating-point support, and training-oriented execution. Its central claim is that high-precision in-memory training is practical when the memory technology offers sufficiently expressive logic and flexible placement of intermediate values. In that sense, the accelerator is not merely an MRAM implementation of known arithmetic, but a proposal about what training-capable PIM should optimize (Wang et al., 2020).

The paper is also explicit about its limitations. The evaluation is performed on LeNet-5/MNIST, so scalability to larger models remains to be studied. The design depends on SOT-MRAM device parameters and switching characteristics taken from prior work. Performance is sensitive to cell switching latency, which dominates total MAC latency. The reported benefits are strongest when the workload is dominated by arithmetic that maps efficiently onto the SOT-MRAM logic primitives.

Within the broader PIM literature, Neural-ART occupies a distinct point in the design space. Later in-memory accelerators such as ATRIA emphasize bit-parallel stochastic arithmetic for CNN inference inside DRAM and report 16 MACs in 5 memory-operation cycles, with a 3.5% average inference accuracy drop (Shivanandamurthy et al., 2021). ARTEMIS combines stochastic multiplication and analog temporal accumulation for transformer inference and reports at least 3.0× speedup, 1.8× lower energy, and 1.9× better energy efficiency relative to several baselines (Afifi et al., 2024). By contrast, Neural-ART is oriented toward floating-point DNN training in a digital SOT-MRAM PIM setting. This suggests that its historical importance lies less in approximate in-memory MAC density than in demonstrating that training-oriented PIM can be both digital and floating-point-capable.

Taken together, Neural-ART remains a representative reference for memory-centric training architectures because it makes a precise argument: reducing data movement is necessary, but it is not sufficient unless the memory substrate can also express the logic structure of floating-point arithmetic efficiently.