SOT-MRAM: Fast, Energy-Efficient Memory

• SOT-MRAM is a non-volatile memory technology that uses spin–orbit effects to switch ferromagnetic layers, achieving high endurance and fast, nanosecond-scale operation.
• It employs heavy-metal layers to harness spin Hall and Rashba–Edelstein effects, enabling deterministic switching with sub-picojoule write energies and robust TMR performance.
• Advanced SOT-MRAM designs integrate into compute-in-memory architectures, offering scalable solutions for cache, embedded systems, and AI accelerators.

Spin-Orbit Torque Magnetic Random-Access Memory (SOT-MRAM) is a class of non-volatile magnetic memory based on manipulating the magnetization state of a ferromagnetic free layer via spin–orbit effects in a heavy-metal underlayer. SOT-MRAM combines high endurance, nanosecond-scale switching, low write energy, and separation of read and write paths, making it suitable for embedded systems, cache memory, and in-memory compute applications. The fundamental operation exploits the spin Hall and/or Rashba–Edelstein effects to generate a spin current orthogonal to a charge current, inducing deterministic or stochastic switching of perpendicular or in-plane magnetic tunnel junctions (MTJs), with no substantial current passing through the tunnel barrier. Recent wafer-scale fabrication results demonstrate mature metrics for relevant applications, with tunnel magnetoresistance ratios up to 170%, write times as low as 1–2 ns, and sub-picojoule write energies (Liu et al., 29 Oct 2025).

1. Spin–Orbit Torque Physics and MTJ Stack Architectures

The switching in SOT-MRAM relies on the spin Hall effect (SHE) or Rashba–Edelstein effect in a heavy-metal layer (e.g., β-W, Pt, Ta, Ir) to transform an in-plane charge current $J_c$ into a transverse spin accumulation $\boldsymbol\sigma$ at the interface with a ferromagnetic free layer (typically CoFeB). The magnetization dynamics of the free layer are governed by the Landau–Lifshitz–Gilbert (LLG) equation, augmented with a torque term:

$$\frac{d\mathbf{m}}{dt} = -\gamma\,\mathbf{m} \times \mathbf{H}_\mathrm{eff} + \alpha\,\mathbf{m} \times \frac{d\mathbf{m}}{dt} + \frac{\hbar}{2e} \frac{\theta_\mathrm{SH} J_c}{M_s t_F} \mathbf{m} \times (\boldsymbol{\sigma} \times \mathbf{m})$$

where:

• $\theta_\mathrm{SH}$ is the spin Hall angle
• $M_s$ is the saturation magnetization
• $t_F$ is the free-layer thickness
• $\alpha$ is the Gilbert damping
• $\mathbf{H}_\mathrm{eff}$ includes anisotropy, demagnetizing, and other fields

Stacks for advanced SOT-MRAM frequently employ β-W ($\theta_\mathrm{SH} \approx 0.6$) for high torque efficiency, in combination with CoFeB/MgO MTJs engineered for either in-plane or perpendicular anisotropy. Patterned bitcells with dimensions down to 75 nm × 230 nm are fabricated on 300-mm wafers by e-beam lithography and optimized etch/cleaning steps (Liu et al., 29 Oct 2025).

Deterministic field-free switching remains a critical challenge for perpendicular SOT-MRAM. Recent architectures exploit exchange-bias fields introduced by Ir layers (Liu et al., 2019), engineered shape anisotropy (Chouhan et al., 2 Apr 2025), interlayer Dzyaloshinskii–Moriya interaction (He et al., 2022), or toggle mechanisms based on pulse sequencing (Hassan et al., 2019) to remove the need for external assist fields.

2. Performance Metrics: Endurance, Speed, Energy, Variability

SOT-MRAM achieves a distinct combination of speed, endurance, and energy metrics compared to other emerging memories:

Metric	Typical Value	Reference
Tunnel magnetoresistance (TMR)	150–170% (β-W stacks)	(Liu et al., 29 Oct 2025)
Write voltage ($V_\mathrm{write}$)	<$\boldsymbol\sigma$0 V	(Liu et al., 29 Oct 2025)
Switching time ($\boldsymbol\sigma$1)	1–2 ns (β-W), sub-ns demonstrated in others	(Liu et al., 29 Oct 2025, Liu et al., 2019)
Write energy ($\boldsymbol\sigma$2)	~350 fJ/bit ($\boldsymbol\sigma$310–30 pJ at 50–150 nm MTJs)	(Liu et al., 29 Oct 2025, Liu et al., 2019)
Endurance	>$\boldsymbol\sigma$4 cycles	(Liu et al., 29 Oct 2025, Sato et al., 2018)
Device-to-device variation ($\boldsymbol\sigma$5)	~10% on wafer scale	(Liu et al., 29 Oct 2025)
Write noise	0.1% (cycle-to-cycle R jitter)	(Liu et al., 29 Oct 2025)

Switching probability curves are well described by sigmoid fits, with the broadening parameter $\boldsymbol\sigma$6 increasing at shorter pulses; e.g., $\boldsymbol\sigma$7 V at 10 ns, $\boldsymbol\sigma$8 V at 2 ns (Liu et al., 29 Oct 2025). Endurance above $\boldsymbol\sigma$9 writes is observed without measurable degradation in MTJ resistance (Liu et al., 29 Oct 2025). Write error rates below $$\frac{d\mathbf{m}}{dt} = -\gamma\,\mathbf{m} \times \mathbf{H}_\mathrm{eff} + \alpha\,\mathbf{m} \times \frac{d\mathbf{m}}{dt} + \frac{\hbar}{2e} \frac{\theta_\mathrm{SH} J_c}{M_s t_F} \mathbf{m} \times (\boldsymbol{\sigma} \times \mathbf{m})$$0 at sub-ns switching have been demonstrated with low-resistivity Au$$\frac{d\mathbf{m}}{dt} = -\gamma\,\mathbf{m} \times \mathbf{H}_\mathrm{eff} + \alpha\,\mathbf{m} \times \frac{d\mathbf{m}}{dt} + \frac{\hbar}{2e} \frac{\theta_\mathrm{SH} J_c}{M_s t_F} \mathbf{m} \times (\boldsymbol{\sigma} \times \mathbf{m})$$1Pt$$\frac{d\mathbf{m}}{dt} = -\gamma\,\mathbf{m} \times \mathbf{H}_\mathrm{eff} + \alpha\,\mathbf{m} \times \frac{d\mathbf{m}}{dt} + \frac{\hbar}{2e} \frac{\theta_\mathrm{SH} J_c}{M_s t_F} \mathbf{m} \times (\boldsymbol{\sigma} \times \mathbf{m})$$2 channels (Zhu et al., 2019).

3. Array Architectures and Integration for Compute-In-Memory

SOT-MRAM crossbar arrays are used for analog and neuromorphic vector-matrix-multiplication (VMM) accelerators, benefiting from high endurance, multi-level storage, and decoupled read-write paths (Liu et al., 29 Oct 2025, Yu et al., 5 Nov 2025). Arrays are implemented in multiple configurations:

• 2-bit Quantized Inference: Each synaptic weight is encoded with two differential SOT-MTJs, enabling signed multi-level weights (Liu et al., 29 Oct 2025).
• Binary Neural Networks (BNN): Use a single MTJ per weight with a reference column for thresholding.
• Spiking Compute-In-Memory (Event-Driven): Hybrid series-parallel cell structures, spike coding for energy-efficient MVM, and circuit techniques for time-domain summation (Yu et al., 5 Nov 2025).

Key crossbar challenges include conductance noise, device-to-device variation, and limited TMR on-off ratios. Mitigations involve quantization-aware and noise-injection training in neural applications, use of high-TMR (≥150%) stacks, and high-quality wafer-scale processing to ensure low D2D variation (Liu et al., 29 Oct 2025). In the event-driven spiking macro, measured energy efficiency achieves up to 243.6 TOPS/W, with read/inference energy per 8-bit MAC operation as low as 4.1 fJ (Yu et al., 5 Nov 2025).

4. Advanced Switching Mechanisms and Scaling

Achieving deterministic field-free switching in perpendicular SOT-MRAM is a central objective to enable dense, low-power arrays. Multiple solutions have been implemented:

• Ir-based Field-Free Bias: An Ir layer both supplies spin Hall torque and mediates in-plane exchange bias up to $$\frac{d\mathbf{m}}{dt} = -\gamma\,\mathbf{m} \times \mathbf{H}_\mathrm{eff} + \alpha\,\mathbf{m} \times \frac{d\mathbf{m}}{dt} + \frac{\hbar}{2e} \frac{\theta_\mathrm{SH} J_c}{M_s t_F} \mathbf{m} \times (\boldsymbol{\sigma} \times \mathbf{m})$$3 Oe, allowing field-free, nanosecond switching for MTJs down to $$\frac{d\mathbf{m}}{dt} = -\gamma\,\mathbf{m} \times \mathbf{H}_\mathrm{eff} + \alpha\,\mathbf{m} \times \frac{d\mathbf{m}}{dt} + \frac{\hbar}{2e} \frac{\theta_\mathrm{SH} J_c}{M_s t_F} \mathbf{m} \times (\boldsymbol{\sigma} \times \mathbf{m})$$4 nm (Liu et al., 2019).
• Interlayer DMI: Synthetic SAF or Pt/Co multilayers display intrinsic interlayer Dzyaloshinskii–Moriya interaction, introducing a chiral exchange energy $$\frac{d\mathbf{m}}{dt} = -\gamma\,\mathbf{m} \times \mathbf{H}_\mathrm{eff} + \alpha\,\mathbf{m} \times \frac{d\mathbf{m}}{dt} + \frac{\hbar}{2e} \frac{\theta_\mathrm{SH} J_c}{M_s t_F} \mathbf{m} \times (\boldsymbol{\sigma} \times \mathbf{m})$$5, breaking inversion symmetry and enabling field-free SOT switching with $$\frac{d\mathbf{m}}{dt} = -\gamma\,\mathbf{m} \times \mathbf{H}_\mathrm{eff} + \alpha\,\mathbf{m} \times \frac{d\mathbf{m}}{dt} + \frac{\hbar}{2e} \frac{\theta_\mathrm{SH} J_c}{M_s t_F} \mathbf{m} \times (\boldsymbol{\sigma} \times \mathbf{m})$$6 A/cm$$\frac{d\mathbf{m}}{dt} = -\gamma\,\mathbf{m} \times \mathbf{H}_\mathrm{eff} + \alpha\,\mathbf{m} \times \frac{d\mathbf{m}}{dt} + \frac{\hbar}{2e} \frac{\theta_\mathrm{SH} J_c}{M_s t_F} \mathbf{m} \times (\boldsymbol{\sigma} \times \mathbf{m})$$7 (He et al., 2022).
• Toggle or Interlaced Currents: Pulse sequencing—either toggle (precessional) switching or sequential interlaced current application—realizes deterministic bi-stable switching with strict control over the final magnetization, without need for static bias (Hassan et al., 2019, Wang et al., 2020).
• Shape Anisotropy: Engineering the ferromagnet as an asymmetric (e.g., triangular) element produces a deterministic internal field upon injection of SOT current, achieving field-free operation (Chouhan et al., 2 Apr 2025).

Scaling analyses indicate that switching current and energy can be further reduced by exploiting materials with large spin Hall angles, optimizing device geometry, and introducing multi-level or probabilistic cell operation. Aggressive scaling to 20–30 nm lateral dimension with novel out-of-plane SOT materials can, for $$\frac{d\mathbf{m}}{dt} = -\gamma\,\mathbf{m} \times \mathbf{H}_\mathrm{eff} + \alpha\,\mathbf{m} \times \frac{d\mathbf{m}}{dt} + \frac{\hbar}{2e} \frac{\theta_\mathrm{SH} J_c}{M_s t_F} \mathbf{m} \times (\boldsymbol{\sigma} \times \mathbf{m})$$8, enable write energies near SRAM-class ($$\frac{d\mathbf{m}}{dt} = -\gamma\,\mathbf{m} \times \mathbf{H}_\mathrm{eff} + \alpha\,\mathbf{m} \times \frac{d\mathbf{m}}{dt} + \frac{\hbar}{2e} \frac{\theta_\mathrm{SH} J_c}{M_s t_F} \mathbf{m} \times (\boldsymbol{\sigma} \times \mathbf{m})$$920–30 fJ) (Shazon et al., 5 Dec 2025).

5. Materials Landscape and Optimization Strategies

The SOT efficiency and write energy critically depend on the heavy-metal material, its resistivity, spin Hall (or orbital Hall) angle, and the interface properties. Materials with high spin Hall conductivity and moderate sheet resistance are optimal (Li et al., 2020). Benchmark figures:

Material	$\theta_\mathrm{SH}$0	Resistivity (μΩ·cm)	Write energy per cell (fJ)	Reference
Pt	0.17	50	~51	(Li et al., 2020)
β–W	0.30	260	~33	(Li et al., 2020)
Au$\theta_\mathrm{SH}$1Pt$\theta_\mathrm{SH}$2	0.30	80	$\theta_\mathrm{SH}$31 (projected, 1 ns)	(Zhu et al., 2019)
Ru/Pt (OHE-assisted)	(OHC$\theta_\mathrm{SH}$4Pt)	(see text)	–20% $\theta_\mathrm{SH}$5, –60% $\theta_\mathrm{SH}$6	(Gupta et al., 2024)

Orbital Hall effect layers (e.g., Ru, Nb, Cr) demonstrate further enhancement of damping-like torque efficiency, reducing switching current and power by up to 20% and 60% compared to pure Pt, respectively (Gupta et al., 2024).

Stack engineering options include partial oxidation to tune anisotropy, careful control of CoFeB/MgO interfaces, and half-fixed layer device designs to direct spin current flow (Nath et al., 2021, Shazon et al., 5 Dec 2025). Voltage-controlled magnetic anisotropy (VCMA) assistance can further lower switching current, with device-scaling analyses supporting sub-nanosecond, fJ-write operation at advanced nodes for PMA SOT-MRAM (Wu et al., 2021).

6. Neural and In-Memory Computing Applications

SOT-MRAM is favorable for analog and stochastic neural network accelerators, providing unique advantages:

• Low Device Variation and Write Noise: Enables reliable 2-bit inference (95% MNIST accuracy) with quantization-aware training; noise-injection during training mitigates D2D-induced error (Liu et al., 29 Oct 2025).
• Probabilistic and Stochastic Training: Bi-stable anisotropy and built-in stochastic switching curves are leveraged for probabilistic computing and noise-robust binary neural network training, with measured accuracies exceeding 97% and significant hardware acceleration in training speed (Liu et al., 29 Oct 2025, Huang et al., 2023).
• Analog and Spiking Compute-In-Memory: Series-parallel SOT-MRAM cells, with event-driven spiking signal coding, support high-efficiency MVM with single-digit fJ/MAC energy and area-efficient, digital-compatible periphery (e.g., spike modulation/decoding units, capacitive charge integration) (Yu et al., 5 Nov 2025).
• Sigmoidal Activation and Hybrid Neurons: SOT-MRAM elements function as the core of mixed-signal neurons, in both purely binary and analog-mixed MLPs; simulation yields only 1% accuracy loss versus floating-point baselines and >10× reduction in power-area product (Reidy et al., 2020).

7. Outlook and Roadmap for SOT-MRAM Technology

Continued SOT-MRAM progress is linked to innovations in both materials and device engineering:

• Materials Discovery: Low-symmetry and Weyl semimetal films for higher out-of-plane SOT efficiency, and OHE-enhanced channels to reduce $\theta_\mathrm{SH}$7 and $\theta_\mathrm{SH}$8 (Shazon et al., 5 Dec 2025, Gupta et al., 2024).
• Scalable Field-Free Switching: Techniques using exchange bias, DMI, shape anisotropy, and layered spintronic engineering to enable fully deterministic, field-free operation down to 20 nm (Liu et al., 2019, He et al., 2022, Chouhan et al., 2 Apr 2025).
• Aggressive Device Scaling: Sub-30 nm MTJs, half-fixed layer structures, and co-optimization of access devices for SRAM-competitive write energy at advanced (e.g., 7 nm, 5 nm) technology nodes (Shazon et al., 5 Dec 2025, Wu et al., 2021).
• Monolithic 3D Integration: Prospects for MRAM stacking above logic, in-memory compute platforms, and SOT-MRAM-accelerated AI kernels (Yu et al., 5 Nov 2025).
• Robust Compute-in-Memory: Sub-3 ns, sub-100 fJ stateful logic (NOR) directly embedded in MRAM arrays with non-volatility, endurance > 10$\theta_\mathrm{SH}$9, and high compatibility with emerging PIM architectures (Hoffer et al., 2022).

SOT-MRAM is thus positioned as a foundational building block for next-generation non-volatile memory, AI accelerators, and high-endurance in-memory processing (Liu et al., 29 Oct 2025, Shazon et al., 5 Dec 2025).