Analog In-Memory Computing (AIMC)

• AIMC is an architectural paradigm that directly executes vector-matrix multiplications in memory arrays using analog physics, achieving energy efficiency and low latency.
• It employs hardware-aware training and robust programming schemes to mitigate nonidealities like noise, drift, and IR drops, ensuring resilient performance.
• The integration of analog cores with digital peripherals in AIMC enables scalable deep learning inference and training by balancing trade-offs in energy, area, and precision.

Analog In-Memory Computing (AIMC) is an architectural paradigm that enables direct execution of vector-matrix multiplications and related tensor operations inside densely integrated memory arrays using analog domain physics. By mapping neural network weights to the conductances of crossbar memory cells (e.g., ReRAM, PCM, or SRAM-based), and applying analog voltages that encode input activations, AIMC yields massively parallel, energy-efficient, and low-latency computation of the key kernels underlying deep learning inference and, in some architectures, training. AIMC stands in contrast to digital In-Memory Computing (DIMC) and conventional von Neumann architectures, fundamentally altering system-level energy, throughput, and area trade-offs by eliminating memory-data-motion and exploiting analog charge or current accumulation as the primitive for the multiply-accumulate (MAC) operation (Sun et al., 2024).

1. Fundamental Principles and Hardware Architecture

AIMC systems are typically organized as grids of crossbar arrays (or "tiles"), each comprising $M\times N$ memory cells whose state (conductance $G_{ij}$) encodes the weight matrix elements $W_{ij}$. For inference, an analog input vector $V\in\mathbb{R}^N$ is applied—through analog voltage or pulse-width modulation—across columns or rows. By Ohm's and Kirchhoff's laws, the output is an analog vector–matrix multiplication,

$I_i = \sum_{j=1}^N G_{ij} V_j$

where $I_i$ is the summed output current on word-line $i$ (Hamzaoui et al., 2024, Klein et al., 2022). Readout is typically performed by per-column analog-to-digital converters (ADCs); input vectors are set by digital-to-analog converters (DACs). In mixed-signal designs, follow-on digital units may apply nonlinear activation, normalization, or pooling; in full analog pathways, neuron nonlinearities can also be implemented by logic-in-memory subcircuits (e.g., Gilbert-cell neurons, spintronic tanh/sigmoid circuits) (Amin et al., 2022). Device non-idealities—resistance drift, cycle-to-cycle variability, IR drops, 1/f (read) noise, and DAC/ADC quantization—are intrinsic and require both architectural and algorithmic mitigation (Luquin et al., 5 May 2025, Gallo et al., 2022).

2. Device Nonidealities, Noise, and Reliability Considerations

AIMC accuracy is fundamentally limited by analog imperfections. Device conductances are subject to programming noise (statistically modeled as $$G_{ij} = G_{ij}^0 + \Delta G_{ij}, \Delta G_{ij}\sim \mathcal{N}(0, \sigma^2_G)$$) and cycle-to-cycle read noise. Circuit-level nonidealities (such as IR drop) are modeled by distributed-resistance networks—a deterministic, yet input- and weight-dependent, effect that is not well-approximated by additive Gaussian noise (Luquin et al., 5 May 2025). Peripheral nonidealities, especially DAC/ADC quantization (typically in the 6–8 bit range), introduce further error.

Reliability degrades quadratically with array dimension due to increased line resistance and concomitant SNR loss. Thus, large matrices are partitioned into $N_{\max}\times N_{\max}$ subarrays using a binary splitting scheme, optimizing the mapping to maximize worst-case SNR subject to area and power constraints (Amin et al., 2022). Parasitic noise and IR drop can be mitigated by partitioning, per-column calibration, and selection of high $R_{off}/R_{on}$ device technologies (e.g., CBRAM rather than MRAM, PCM intermediate) (Amin et al., 2022, Luquin et al., 5 May 2025).

AIMC platforms demonstrate high inherent adversarial robustness due to the irreducible, input-independent stochastic output noise that "randomizes" internal activations, raising the attack success threshold in white-box and hardware-in-the-loop settings (Lammie et al., 2024). The magnitude and type of noise (recurrent/non-recurrent, output vs. weight) dominate robustness.

3. Algorithmic and Training Methodologies for AIMC

To maintain high DNN accuracy despite analog errors, AIMC deployment relies on Hardware-Aware (HWA) training. The forward pass is replaced by the physical hardware model, encompassing device/circuit noise, drift, quantization, and IR drop. Additive Gaussian noise or more detailed non-linear circuit models are injected during both forward and backward passes (Rasch et al., 2023, Luquin et al., 5 May 2025). In situ noise-aware training selects weight distributions and scaling factors that produce robust, flat minima resilient to noise (Hamzaoui et al., 2024). Losses may incorporate sensitivity regularization

$$\mathcal{L}_{total} = \mathcal{L}_{seg} + \lambda \left\| \frac{\partial y_{pred}}{\partial W} \right\|_2^2$$

as part of analog-robust model design (Hamzaoui et al., 2024).

For training on AIMC hardware (not merely inference), pipeline parallelism—partitioning large models over multiple analog tiles and forwarding microbatches in synchronous or asynchronous fashion—is used to maximize hardware utilization and parallelism, with proven convergence guarantees despite update asymmetry caused by device physics (Wu et al., 2024).

Programming schemes for accurate weight instantiation include global gradient-descent programming (GDP), which directly minimizes the end-to-end MVM error via synthetic random input probes and batchwise gradient steps—substantially reducing MVM error and improving network accuracy versus traditional per-cell iterative programming, while eliminating the need for high-resolution ADCs on every cell (Büchel et al., 2023).

4. Digital-Analog Co-Design and System Integration

While the core MVM is performed in analog, digital near-memory or periphery circuits are essential for error correction, activation functions, and high-level operator flexibility. Fixed-point near-memory processors (e.g., NMPU) are custom-designed to remap and correct ADC outputs via affine transformations (scale and offset), incorporate BatchNorm and ReLU, and achieve drastic reductions in area and post-processing latency relative to FP16 designs (7.8× less area, 139× lower latency, sub-pJ/MAC energy), while preserving near-baseline accuracy for standard benchmarks (Ferro et al., 2024).

Heterogeneous and hybrid system architectures tightly couple AIMC tiles with multicore CPUs or integrate digital RISC-V clusters for non-MVM DNN operations. Examples include 64–512 core multi-tile chips fully supporting large CNNs, LSTMs, and even full transformer models; cluster interconnects are realized via high-bandwidth meshes or, for scalability, via wireless-on-chip transceivers for low-latency multicast communication (Klein et al., 2022, Gallo et al., 2022, Bruschi et al., 2022). Full-system simulators (e.g., gem5-X) allow accurate benchmarking and design-space co-exploration (Klein et al., 2022).

Analog in-memory computing platforms have been demonstrated at >60 TOPS and ~10 TOPS/W (e.g., IBM HERMES). Energy per MAC is minimized by increasing array size (to exploit more spatial unrolling), but array utilization and ADC precision become critical limiting factors at large macro sizes (Sun et al., 2024, Gallo et al., 2022). For some workloads (e.g., convolutions/pointwise with large arrays and high spatial unrolling), AIMC energy efficiency exceeds DIMC up to 2–4×; for depthwise or small FC layers, DIMC may be preferable due to underutilization.

5. Application Domains, Robustness, and Performance Benchmarks

AIMC is especially suited to deep learning inference at the edge, medical imaging (e.g., brain/spleen/nuclei segmentation), natural language processing (transformers, LLMs), and kernelized attention or random feature methods for non-linear ML. In medical imaging segmentation tasks, AIMC with isotropic transformer-derived backbones (e.g., Swin U-Net) demonstrates minimal accuracy drop under analog-aware training (<0.04 dice) versus significant drop in noise-amplifying, pyramidal CNNs (up to 0.15–0.22 dice) (Hamzaoui et al., 2024). These results highlight the role of architectural co-design between network topology and AIMC error resilience. For transformer networks, methods such as freezing analog weights and adapting only digital low-rank adapters provide drift and nonideality robustness with minimal memory and chip overhead across multi-task deployments (Li et al., 2024).

Quantitatively, multi-core PCM-based platforms achieve near-software-equivalent accuracy (<1% accuracy drop) for ResNet and LSTM inference, with measured throughput of up to 63.1 TOPS at 9.76 TOPS/W for 8-bit input/output MVMs (Gallo et al., 2022). Kernel-approximation workloads (random Fourier features, structured orthogonal random features, kernel attention) can be mapped efficiently to AIMC—achieving less than 1% accuracy degradation and 6–12× energy efficiency over state-of-the-art INT8 digital accelerators (Büchel et al., 2024).

Robustness to device and circuit noise is enhanced via hardware-aware training, architectural selection (favoring RNNs/transformers with dense MVMs), and, in adversarial settings, by harnessing the irreducible stochasticity of analog noise as a built-in defense (Rasch et al., 2023, Lammie et al., 2024). Retrieval, calibration, and resilience to drift are supported by programming schemes, per-column digital correction, and on-chip adaptation layers.

6. Design Trade-offs, Limitations, and Outlook

Optimization of AIMC architectures necessitates joint consideration of hardware (array size, DAC/ADC precision, device selection), system-level mapping (tiling, pipeline parallelism, heterogeneity), and network co-design (topology, quantization, analog-aware regularization). Key trade-offs include:

• Array dimension vs. SNR: Larger arrays amortize peripheral energy, but degrade SNR and require more calibration.
• Macro utilization: Layer shape and workload determine whether AIMC or DIMC is optimal for any given network (Sun et al., 2024).
• Precision and area: Reducing ADC bit-width (e.g., via CSNR-optimal design with CACTUS) yields up to 3-bit savings and 4× energy per bit reduction without compromising compute accuracy (Kavishwar et al., 13 Jul 2025).
• Mixed-signal vs. full analog: Full analog pathways can eliminate >90% of digital conversion energy but demand highly reliable circuit design and may be more sensitive to parasitics (Amin et al., 2022).

Promising directions noted in the literature include circuit-aware backpropagation, adaptive tile partitioning, runtime calibration for process/temperature drift, neural-architecture search constrained by analog robustness, device-in-the-loop training, and hybrid analog–digital error correction. The field is progressing toward resilient, scalable, and energy-efficient deployment of large and diverse neural models, including transformers and mixture-of-expert LLMs, onto analog in-memory computing hardware (Chowdhury et al., 3 Mar 2026, Li et al., 2024).

7. Summary Table: Key Characteristics of AIMC Architectures

Domain	Design Feature	Typical Metric / Result
Inference Speed/Energy	Core analog MVMs	>60 TOPS, <1 pJ/MAC (Gallo et al., 2022, Xuan et al., 2023)
System Integration	Multi-core topology	64–512 tiles w/ RISC-V clusters (Gallo et al., 2022)
Non-idealities	Noise, drift, IR-drop	Accuracy drop <1% w/ HWA; robust to drift (Rasch et al., 2023, Luquin et al., 5 May 2025)
Digital/Analog Balance	Periphery NMPU, digital activation	Area ×7.8 and latency ×139 over FP16 (Ferro et al., 2024)
Calibration	Per-column affine, gradient programming	1.26% acc. gain vs. iterative (Büchel et al., 2023)
Robustness (adv attacks)	Output noise harnessed	Up to 30% ASR reduction (Lammie et al., 2024)
Flexible adaptation	LoRA modules in transformers	<2 pt. (GLUE) avg. drift over 10 y, 4× fewer params (Li et al., 2024)
Energy scaling	CSNR-optimal ADC (CACTUS)	3 bit reduction, 4× per-ADC E reduction (Kavishwar et al., 13 Jul 2025)

AIMC thus realizes a practical path toward real-time, low-power, and robust deployment of complex deep learning models on highly parallel memory-centric digital/analog hardware platforms. The paradigm is characterized by device-model-aware software stacks, architectural co-optimization, and a deep interplay between hardware, algorithms, and applications spanning edge intelligence, scientific computing, and next-generation AI accelerators.