Flexible RISC-V Processors

• Mechanically flexible RISC-V processors are built on thin polymer substrates using IGZO TFTs for low-cost, ultra-conformal, edge and wearable applications.
• The design leverages an instruction-as-block methodology, assembling pre-verified RTL blocks into a single-cycle, in-order pipeline tailored to specific application needs.
• Empirical results demonstrate significant efficiency gains, including up to 30% area reduction and 21× speedup with integrated ML co-processors under flexible IC constraints.

Mechanically flexible RISC-V denotes a class of processors fabricated on thin, conformal substrates using low-temperature transistor technologies (notably IGZO TFTs), departing from traditional rigid silicon CMOS. These architectures are optimized for extreme-edge and wearable applications requiring ultra-low cost, sub-milliwatt power, and mechanical stretchability while maintaining compatibility with the RISC-V open instruction set. Research in this field is driven by the constraints and opportunities of flexible electronics—large feature sizes, nMOS-only logic, bending stresses—and is characterized by both customized instruction subset cores and co-processor acceleration for edge computation in resource-constrained, physically dynamic environments (Raisiardali et al., 7 May 2025, Vergos et al., 27 Aug 2025, Vergos et al., 8 Nov 2025).

1. RISC-V Instruction Subset Processor (RISP) Generation and Verification

Mechanically flexible RISC-V design introduces the RISC-V Instruction Subset Processor (“RISP”, Editor's term) methodology, addressing the cost and verification challenges in flexible IC (FlexIC) workflows (Raisiardali et al., 7 May 2025). The core principle is the instruction-as-block paradigm:

• Each RV32I/E instruction is implemented once as a discrete, self-contained, pre-verified RTL hardware block.
• Formal verification leverages SystemVerilog Assertions and mutation testing against the official RISC-V Foundation suite.

Application-tailored cores are synthesized by:

1. Profiling code (e.g., compiling with –O2 to RV32E) to identify the minimal instruction subset exercised (typically 6–32 distinct instructions).
2. Extracting corresponding pre-verified blocks from the hardware library.
3. Stitching blocks into a single-cycle, in-order pipeline with a modular execute (“ModularEX”) stage and a small switch/decoder that selects among blocks per opcode+funct3+funct7.
4. Completing integration with register file, fetch and memory logic.

Verification is integration-centric (RISCOF conformance against Spike, plus custom application-level microbenchmarks), benefiting from the fact that individual instructions are verified once and reused. This approach drastically reduces both verification effort and design cycle time for flexible edge-optimized designs.

2. Microarchitectural Techniques and Single-Cycle Operation

The “stitching” of application-tailored instruction blocks yields a single-cycle processor microarchitecture with the following canonical structure (Raisiardali et al., 7 May 2025):

• Fetch: Program counter to instruction memory.
• Decode/Switch: Activates a single instruction-specific block.
• Execute: ModularEX block evaluates ALU or memory operations.
• Writeback: Returns results to register file or memory.

Control involves a compact FSM managing PC updates (incl. branches, JALR). Notably, no pipeline stages exist between instructions, so hazards (RAW/WAR/WAW) are eliminated—each instruction completes state update before the next fetch. This organization minimizes both gate count and control complexity, appropriate for the large feature, slow devices of IGZO-based FlexIC technology.

3. Flexible Integrated Circuit Fabrication and Mechanical Metrics

Mechanically flexible RISC-V processors exploit the FlexIC process:

• Substrate: 200 mm (or 300 mm) polyimide wafer, final thickness 30 μm, capable of large-area roll-to-roll production.
• Transistors: IGZO (Indium-Gallium-Zinc-Oxide) TFTs, minimum 0.6 μm channel length, n-mos only.
• Interconnect/Backend: Printed metals, vias, and low-modulus dielectrics (to prevent cracking).
• Mechanical reliability: Minimum bend radius ≈ 3–5 mm (no device failure, <5% timing drift after 10,000 cycles at 10 mm bend).
• Process temperature: ≤ 150 °C, enabling polymer compatibility and embedded passive integration.

Layout and floorplanning leverage meandered interconnects and low-modulus stackup for stretchability and tensile reliability. No brittle passives are permitted in the flex stack.

4. Quantitative Performance, Area, and Power Metrics

Mechanically flexible RISC-V implementations (0.6 μm FlexIC, Vdd=3 V):

Core Type	Area (mm²)	Power (mW)	CPI	Energy/instr (nJ)	Nominal fmax (kHz)
RISP-RV32E (full ISA)	1.15	0.98	1	~2.3	300
SERV (bit-serial, CPI=32)	0.83	1.07	32	~114	300
Extreme-Edge RISP (subset)	0.66–0.83	0.69–0.91	1	~2.3	300
Bespoke MAC co-proc (MLP/SVM)	0.16–0.19	0.13–0.16	—	—	≤150

Area and power reductions versus full-ISA cores are substantial: a 30% area and 26% power decrease (subset RISP vs. full RV32E), ∼30× energy per instruction improvement versus bit-serial SERV (because CPI=32 for SERV), and typical die costs under $0.10 (Raisiardali et al., 7 May 2025, Vergos et al., 8 Nov 2025). Power is dominated by static (due to n-mos-only logic), but dynamic energy can be minimized by reducing unnecessary hardware and maximizing per-cycle utilization.

Design trade-offs include:

• Smaller instruction subsets yield smaller, lower-leakage, higher-frequency cores, but extending functionality via software emulation of missing instructions (e.g., code bloating) may erode some benefits.
• Bit-serial designs further minimize area and wiring (as in SERV/Bendable RISC-V), but are inherently slow.
• Bespoke, by-constant MAC co-processors attain much lower latency/energy for machine learning kernels by eliminating generic multipliers and weight fetches.

5. Machine Learning Co-Processors and Accelerator Integration

Mechanically flexible RISC-V systems have incorporated two distinct co-processor strategies for ML acceleration:

• Generic SVM Accelerator (Bendable RISC-V):
  • Integrates via a custom function unit (CFU) with handshake signals (accel_valid, accel_ready).
  • Eight parallel 4×4 multipliers (scalable for 4-, 8-, 16-bit precision), accumulator register, and argmax/majority logic for OvR/OvO schemes.
  • Operates under a handshake protocol (32-cycle operand transfer, 1-cycle compute).
  • Delivers ∼21× speedup and >95% energy reduction for SVM classification (LinearSVC on UCI datasets) (Vergos et al., 27 Aug 2025).
  • System-level: total power <1 mW at 52 kHz, conformal to substrate; reliable for >10⁴ flex cycles at a 3 mm radius.
• Bespoke Fixed-Coefficient MAC Co-Processor (Health Monitoring):
  • Co-processor tightly coupled to bit-serial SERV RV32E via custom R-type instructions and ready/valid protocol (Vergos et al., 8 Nov 2025).
  • M by-constant multipliers instantiated in parallel, hard-wired to model-specific weights (C′), selected via a formal CP-SAT optimization to meet gate, latency, and hardware capacity constraints.
  • Mapping to MLP inference: each neuron is accumulated over minimal cycles by chunking partial sums using available constants.
  • Achieves an average 2.35× speedup and 2.15× lower energy compared to the state-of-the-art flexible RISC-V (Flex-RV).

Integration is enabled by low NRE and rapid (∼6 weeks) FlexIC fab cycles, making one-off, model-specific hardware instantiations cost-effective. The CP-SAT formalization allows extension to broader MAC-based kernels (SVM, CNN, etc.).

6. Application Domains, Evaluation Benchmarks, and System Constraints

Deployments at the extreme edge leverage mechanically flexible RISC-V/ML hardware for constrained, always-on computing:

• Edge analytics: Atrial fibrillation detection, armpit malodour classification, XGBoost kernel execution—all implemented as FlexICs on application-specific RISP cores, with instruction subsets as low as 8 out of 40 RV32E instructions (Raisiardali et al., 7 May 2025).
• Healthcare & Wearables: ML inference for affect, arrhythmia, ECG/EEG, stress, dermatology, and human activity recognition tasks (topologies e.g., 63–9–3 MLP, MACs 435–3969), with quantized 4–5 bit weights/activations, inferencing <1 s and <1.0 mJ per prediction (Vergos et al., 8 Nov 2025).
• IoT and Environmental Sensing: SVM co-processor enables smart label, disposable patch, and conformal gas/humidity sensor applications, exploiting low cost and disposability (Vergos et al., 27 Aug 2025).

The power profile (typically 0.7–1.5 mW total) lies within printed flexible battery budgets (2–5 mW), and the mechanical flexibility supports thousands of bend cycles with negligible timing impact.

System limitations include single-cycle scalar core operation (no superscalar/out-of-order), clock frequencies capped (2 MHz max; 150–300 kHz typical), bit-serial bottlenecks, and a lack of nonvolatile memory integration. Code size may increase if missing instructions are emulated in software.

7. Future Directions and Research Prospects

Mechanically flexible RISC-V research is converging toward:

• Pipelined Core Variants: Adding pipelining to RISPs for improved throughput within FlexIC gate and timing constraints (Raisiardali et al., 7 May 2025).
• Hardware-Software Co-Design: Exploring multi-block granularity (e.g., partial instructions or micro-op folding) for fine-grained power/performance trade-off.
• Tightly Integrated ML Co-Processors: Expanding bespoke co-processors to support more complex MAC-based kernels (CNNs, temporal models) via enhanced decomposition and scheduling.
• System Integration: Embedding non-volatile flexible memories, energy harvesters, and analog front-ends for fully self-powered sensor–compute–communicate subsystems.
• Process/Materials Advancements: Continued optimization for sub-µm IGZO TFTs, low-resistance metals, and ultra-low modulus dielectrics to minimize area, leakage, and strain-induced failure.

A plausible implication is that flexible RISC-V architectures will underpin a spectrum of next-generation, disposable, and ultra-conformal machine intelligence platforms, contingent on further advances in power gating, scalable process integration, and the co-optimization of instruction set, microarchitecture, and process materials.