RISC-V GPU Architectures

• RISC-V-based GPUs are programmable accelerator architectures that leverage an open ISA extended with custom instructions for efficient SIMT control and warp management.
• They integrate streamlined hardware and software toolchains, supporting frameworks like OpenCL, OpenGL, and CUDA for diverse applications from datacenter acceleration to TinyAI edge computing.
• Designs emphasize scalability, energy efficiency, and extensibility by balancing minimal ISA overhead with enhanced collective operations and intra-warp communication.

RISC-V-based GPUs are programmable accelerator architectures that implement the open RISC-V instruction set, often with minimal, targeted extensions to support Single-Instruction-Multiple-Threads (SIMT) and graphics workloads. These platforms provide a research vehicle for general-purpose and domain-specific parallel computation, enabling full-stack innovation across hardware, ISA, toolchain, and runtime. Designs span a diversity of operating points, from datacenter-scale tensor engines to ultra-low-power, deeply configurable units for TinyAI applications, and include end-to-end support for programming frameworks such as OpenCL, OpenGL, and even CUDA through compatible intermediate representations.

1. RISC-V GPU ISA Extensions and Microarchitectural Primitives

Most RISC-V GPU architectures extend the base scalar ISA (RV32I/RV64I) with a small set of custom instructions tailored for SIMT control, warp management, and collective communications. The Vortex architecture is a canonical exemplar (Elsabbagh et al., 2020, Tine et al., 2021), adding five to six principal instructions: wspawn (wavefront launch), tmc (thread mask control), split/join for control divergence, bar for barrier synchronization, and optionally tex for texture sampling. The encoding style reuses R-type or I-type formats with a single custom opcode space, keeping toolchain impact minimal.

Key hardware features arising from these extensions include:

• Warp Scheduler: Tracks per-warp program counter and active mask, issuing instructions to SIMD lanes in lock-step.
• Barrier Table/IPDOM Stack: Manages thread reconvergence for divergent branches (split/join) and schedules barrier operations locally and globally.
• Register File Design: Per-warp partitioning, sometimes enhanced with crossbar or reduction tree interconnects to support warp-level features (e.g., shuffle, ballot) (Pu et al., 6 May 2025).

SIMT pipelines typically retain standard five- to seven-stage RISC-V datapaths—fetch, decode, execute (vector/scalar ALU), memory, write-back—with modest augmentation for vector and mask management.

2. Programming Models and Toolchain Compatibility

RISC-V GPUs support a range of programming models. OpenCL compatibility is realized via the POCL runtime, which lowers OpenCL C kernels to ELF binaries for the target ISA (including the GPU extensions) (Elsabbagh et al., 2020, Tine et al., 2021, Machetti et al., 13 May 2025). The threading and work-group abstractions are mapped directly onto the hardware's warp/thread structure, with barrier, divergence, and mask management expressed through explicit intrinsics or lowered automatically by the compiler.

CUDA support is achieved by translating NVIDIA-specific IR (NVVM) to SPIR-V, then to OpenCL LLVM IR, replacing CUDA built-ins, barriers, and atomics with OpenCL analogues (Han et al., 2021). This multi-stage toolchain leverages open-source infrastructure for metadata handling and ensures that hardware backends can exploit SIMT features with minimal modification.

Edge-oriented designs such as e-GPU expose a lightweight Tiny-OpenCL framework, which maps kernel launches, work-groups, and thread sync onto highly resource-constrained, power-gated compute units (Machetti et al., 13 May 2025). Host runtime and scheduling are kept minimal, with kernel binaries compiled via standard GCC toolchains and direct mapping of physical buffers to accelerator memory.

3. Warp-Level Features: Hardware and Software Realizations

Modern GPU compute patterns increasingly demand fine-grained intra-warp communication primitives, such as ballot/vote, shuffle (register exchange), and sub-warp cooperative groups (Pu et al., 6 May 2025). Hardware implementations introduce new instructions (vx_vote, vx_shfl, vx_tile) and corresponding datapath modifications (cross-bar interconnects and reduction trees). The Vortex pipeline intercepts these instructions at decode and routes operands through augmented EX-stage ALUs and configurable schedule masks.

Measured performance gains are substantial: microbenchmark kernels exhibit up to 4× IPC improvement over baseline scalar cores, with hardware area overhead limited to ≈2% at the core level. In contrast, software emulation of warp features via explicit loop transforms and array allocations achieves functional correctness with no hardware cost but incurs high instruction bandwidth, code size, and latency penalties. For area- or energy-constrained scenarios, the compiler can detect and linearize warp-level calls, falling back to software routines. Design recommendations emphasize minimal ISA footprint, datapath reuse, and runtime configurability of lane/interconnect resources.

Benchmark	IPC_base	IPC_sw	IPC_hw	S_hw
vote	0.25	0.30	1.00	4.0×
shuffle	0.20	0.25	0.90	4.5×
mse_forward	0.40	0.45	0.50	1.25×
matmul	0.60	0.60	0.48	0.8×
reduce	0.15	0.17	0.60	4.0×
reduce_tile	0.10	0.12	0.52	5.2×
Geomean	—	—	—	2.42×

The hardware path is recommended where kernel performance is dependent on register-level collectives or subgroup synchronization, while the software path remains viable for low-communication or irregular workloads.

4. Application Domains: General-Purpose, TinyAI, and Domain-Specific Computing

Open-source RISC-V GPUs cover a span of use-cases:

• General-purpose GPGPU: Vortex supports OpenCL/OpenGL, PCIe host interfaces, and scales up to 32 cores at 200 MHz (peak 25.6 GFlops on Stratix 10 FPGA; sustained 18 GFlops) (Tine et al., 2021). Its minimal ISA and modular hardware foster reproducibility and extensibility.
• TinyAI: e-GPU targets edge applications with strict area/power constraints (0.24–0.38 mm², ≤28 mW). Configurability in thread count, cache banks, and power gating allows designers to balance parallelism and efficiency, achieving up to 15.1× speed-up and 3.1× energy reduction on bio-signal tasks (Machetti et al., 13 May 2025). Scheduling overhead for Tiny-OpenCL is negligible for matrix sizes ≥256×256.
• Safety-critical systems: METASAT incorporates Vortex alongside NOEL-V CPUs and SPARROW SIMD for space-grade, qualifiable, partitioned computing. Integration exploits AXI buses, RTEMS, XtratuM, and statically linked GPU kernels for resource isolation and certification compliance (Bonet et al., 28 Feb 2025). Where GPU resource is limited, inference time may lag stronger CPU/vector units, but demonstrates feasibility for partitioned high-performance platforms.
• Domain-specific acceleration: RISC-V GPUs have been extended with custom instructions for tasks such as Hyperdimensional Computing (HDC), enabling 56.2× speedup on HDC “Bound” primitives via direct register-level accumulation (Matsumi et al., 7 Nov 2025). The approach illustrates that domain-specific extensions can be safely integrated with minimal area and software impact.

5. Precision, Energy, and Throughput: The RISC-V Tensor Engine Perspective

High-performance RISC-V “GPU-style” accelerators, such as Tenstorrent’s Grayskull, are architected with multiple baby RISC-V cores, matrix-vector MAC units, and flexible precision support (FP32, BF16, BFP4/8/16) (Cavagna et al., 9 May 2025). Matrix multiplication is tiled and scheduled over a mesh/NoC of compute cores with explicit scratchpad memory, avoiding coherence and maximizing locality.

Performance modeling follows roofline analysis, with measured peak efficiency up to 1.56 TFLOP/W (BF16), outperforming NVIDIA A100/V100 in power-per-FLOP for equivalent precision, while trailing in raw TFLOP/s. Sustained compute-to-peak ratios are comparable (80–89%), and multi-core scaling is near linear up to grid sizes of 64 cores.

Device	Peak (BF16)	Sustained	Efficiency	TFLOP/W
Tenstorrent	55 TFLOP/s	49 TFLOP/s	89%	1.56
NVIDIA V100	125 TFLOP/s	110 TFLOP/s	88%	0.45
NVIDIA A100	312 TFLOP/s	250 TFLOP/s	80%	0.53

Power and area efficiency are achieved by eschewing hardware caches (except per-core SRAM), using explicit DMA-like data movement, and exposing low-level control to compilers for tiling and grid scheduling.

6. Scalability, Integration, and Extensibility

RISC-V GPUs are designed for modular scaling and flexible integration:

• Scalability: Architectural resource usage (ALUs, warp tables, IPDOM stacks, cache banks) scales nearly linearly with thread/warp count; area/power from synthesis supports up to 32 cores per FPGA and hundreds of threads per ASIC (Tine et al., 2021).
• Integration: SoC integration is streamlined via standardized bus interfaces (OBI, AXI), direct-mapped memory, and interrupt-driven completion. Power and clock gating are managed through host-controlled registers and custom instructions (e.g., SLEEP_REQ (Machetti et al., 13 May 2025)).
• Extensibility: ISA extensions for tensor, HDC, or matrix operations are implemented as new opcode/funct7 spaces with localized hardware datapath augmentation, preserving compatibility with baseline RISC-V ecosystem. Future development directions include more complex collective operations, dynamic warp control, expanded precision, hardware-assisted offloading, and power/thermal-aware scheduling (Pu et al., 6 May 2025, Cavagna et al., 9 May 2025).

7. Limitations, Trade-Offs, and Future Directions

Principal limitations of early-stage RISC-V GPU designs include limited thread/wavefront size (e.g., 32 vs. 64–128 in commercial GPUs), single-precision floating-point support, lack of native vector predication, and performance overhead in software-emulated collective features. FPGA implementations generally prioritize portability and flexibility over peak performance or area efficiency.

Trade-offs among hardware and software warp-level support, precision formats, memory hierarchy, and thread organization must be balanced with target workload and design constraints. Minimal ISA and hardware extensions are favored for maintainability, while domain-specific accelerators exploit custom instructions for maximum efficiency within a narrow operational scope.

Future directions focus on richer collective operations (reduce_by_key, segmented scan), adaptive kernel offloading, variable-length warp scheduling, vertical integration with memory/power/thermal stack control, and rigorous comparative analysis as these platforms mature and see wider adoption.

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RISC-V-based GPUs represent a technically diverse and rapidly evolving class of programmable hardware accelerators, leveraging the open ISA and toolchain ecosystem for research adaptability, low-power edge deployment, domain specialization, and ecosystem openness. The platform's evolution points toward further unification of hardware specialization, full-stack software portability, and granular control over architectural complexity for parallel processing performance, efficiency, and safety.