LLM4-IC8K: Automated IC Footprint Geometry

• LLM4-IC8K is a specialized framework that automates IC footprint geometry understanding from datasheet images via a sequential chain-of-thought approach.
• It employs a two-stage process, starting with synthetic pre-training on clean IC diagrams followed by fine-tuning on real, cluttered datasheet images.
• The framework achieves state-of-the-art performance in geometric labeling with rapid inference, despite challenges with high pin-count packages and varied drawing conventions.

Searching arXiv for the LLM4-IC8K paper and closely related recent work to ground the article. LLM4-IC8K is a framework for automated integrated-circuit footprint geometry understanding from mechanical drawings, introduced for the task of package geometry labeling directly from datasheet-style images. It treats IC mechanical drawings as images and leverages LLMs for structured geometric interpretation, decomposing the problem into pin counting, pin-center localization, and pin-dimension estimation. The framework is paired with ICGeo8K, a multi-modal dataset with 8,608 labeled samples, including 4138 hand-crafted IC footprint samples and 4470 synthetically generated samples, and is evaluated against baseline multimodal LLMs on a held-out benchmark where it achieves the strongest reported performance among the compared models (Wang et al., 30 Jul 2025).

1. Problem setting and scope

Printed-Circuit-board footprint geometry labeling of integrated circuits is presented as essential in defining the physical interface between components and the PCB layout, while also requiring exceptional visual perception proficiency. The underlying input is not a normalized CAD primitive representation but an unstructured footprint drawing embedded in datasheet pages that may include abstract diagram annotations, multiple views, text blocks, varied fonts, and other visual clutter. The paper states that automated parsing and accurate footprint geometry modeling remain highly challenging under these conditions, and further states that no methods currently exist for automated package geometry labeling directly from IC mechanical drawings (Wang et al., 30 Jul 2025).

Within this setting, LLM4-IC8K addresses a narrowly defined but technically demanding objective: recover a structured description of the footprint layout from the drawing. The recovered structure consists of the number of pins, the center coordinates of each pin, and the dimensions of individual pins. This framing places the method at the intersection of multimodal reasoning, geometric perception, and EDA-oriented diagram understanding.

A central motivation is the reported weakness of current large multimodal models on this task. The paper states that current LMMs severely suffer from inaccurate geometric perception, which hinders their performance in solving the footprint geometry labeling problem. This establishes LLM4-IC8K not as a generic visual question-answering system, but as a specialized framework for geometric extraction from IC packaging documentation (Wang et al., 30 Jul 2025).

2. Architectural organization and multimodal processing

LLM4-IC8K uses a two-stage architecture. In Stage 1, synthetic pre-training is performed on 4,470 synthetically generated IC footprint diagrams. Each synthetic sample is a clean, datasheet-style image plotted directly from EDA XML descriptions, with fully known pin count, pin centers and pin dimensions. This stage is described as teaching the model basic geometric reasoning in a noise-free setting. In Stage 2, the same multimodal LLM is fine-tuned on 4,138 hand-curated datasheet pages containing real IC footprint drawings; these images include clutter, three-view outlines, text blocks, multiple diagrams per page, and varied fonts/styles, and the purpose of this stage is to adapt the model to real-world visual complexity and idiosyncratic annotation formats (Wang et al., 30 Jul 2025).

The input is a high-resolution image $I$ of a datasheet page containing the target footprint diagram. The vision encoder, specified as Naive Dynamic Resolution mapping plus M-ROPE, converts $I$ into a sequence of image tokens. These tokens are concatenated with text tokens and passed into the LLM backbone. The base model reported for the framework is Qwen2-VL-7B with LoRA adapters.

The inference procedure is organized as a chain-of-thought-style multi-round dialogue. Rather than requesting the full geometry in one step, the framework asks three sequential queries: pin count, then pin coordinates, then pin dimensions. The paper states that this structuring allows the model to interleave visual grounding with symbolic reasoning in the LLM. A plausible implication is that the architecture is intended to reduce combinatorial ambiguity by imposing an explicit dependency order among outputs, rather than relying on a single unconstrained multimodal decoding step.

3. Task decomposition and learning objectives

The framework decomposes footprint labeling into three sub-tasks intended to mimic the step-by-step reasoning approach used by human engineers. The first task is pin counting. Its input is the image $I$, and its output is an integer $\hat N$, the predicted number of pads or pins, with the formulation

$\hat N = \arg\max_n P(n \mid I).$

The reported loss for this task is cross-entropy or MAE/RMSE on $\hat N$ versus the ground-truth count $N$ (Wang et al., 30 Jul 2025).

The second task is pin center coordinate prediction. Its input is the image together with the predicted count from Task 1, and the model is prompted that there are $\hat N$ pins and should list their center coordinates in order. The output is a set of 2D points

$$\{(\hat x_i,\hat y_i)\} \text{ for } i=1 \ldots \hat N,$$

where each coordinate is measured in millimeters relative to a predefined origin such as the package centroid. The per-pin formulation is

$(\hat x_i,\hat y_i)=f_{\text{coord}}(I,i),$

with mean squared error

$I$0

The third task is pin-dimension estimation. Its input is the image together with the outputs of Tasks 1 and 2, so the model is given the approximate location of each pin. The output is a set of width and height pairs

$I$1

The formulation is

$I$2

and the loss is either MSE on $I$3 or an IoU-based loss between predicted and ground-truth rectangular pads:

$I$4

The three tasks are trained under a combined objective

$I$5

where $I$6 is given as $I$7 or $I$8, and $I$9 are tuned so that all three losses contribute comparably, with the example setting $I$0, $I$1, $I$2 (Wang et al., 30 Jul 2025).

4. ICGeo8K dataset and synthetic data generation

The dataset introduced with the framework is ICGeo8K, described as a multi-modal dataset with 8,608 labeled samples. It contains 4138 hand-crafted IC footprint samples and 4470 synthetically generated samples. The synthetic component is referred to as ICGeo8K-Syn in the detailed summary and is constructed from real EDA XML footprint definitions collected from UltraLibrarian (Wang et al., 30 Jul 2025).

Synthetic generation is parameterized from package definitions containing pin count, pad centers, and pad sizes. The process randomly samples an IC package type and its parameter set, including pin count $I$3 in $I$4, X/Y pin spacing, and pad width and height, following the empirical distribution found in the 200 K Digi-Key entries. The resulting images are rendered as clean diagrams in the style of a datasheet footprint, with black lines on a white background, uniform font for dimension annotations, spacing arrows, index labels, and standardized placement of text labels. Ground-truth annotations are recorded directly from the sampled EDA files, and the output includes 4,470 synthetic images plus JSON Q&A pairs.

The dataset design is explicitly complementary across its two components. The synthetic subset provides wide coverage of pin counts and package types together with noise-free learning of annotation conventions, while the real subset exposes the model to clutter and visual heterogeneity encountered in practical datasheet pages. The reported training schedule follows this logic directly: 3 epochs on 4,470 synthetic samples, then 3 epochs on 4,138 real samples, using a learning rate of $I$5, sequence cutoff length 4096, and batch size 2 per GPU.

This staging is methodologically important because the paper’s ablations distinguish synthetic pre-training followed by real-world fine-tuning from both real-only training and joint training. This suggests that the benefit of synthetic data lies not merely in increasing sample count, but in imposing a curriculum from controlled geometric reasoning to visually noisy deployment conditions.

5. Empirical results and ablation findings

Evaluation is conducted on ICGeoQA, a benchmark of 400 held-out real entries whose distribution is matched to 200 K Digi-Key packages across 10 package types and pin counts from 1 to 800. The reported metrics are overall layout accuracy

$I$6

Task 1 MAE and RMSE on pin count, Task 2 average euclidean error $I$7, and Task 3 average pad-$I$8 (Wang et al., 30 Jul 2025).

Against baseline multimodal LLMs using single-shot prompting, the reported mean $I$9 standard deviation over 400 samples is as follows. GPT-4o achieves $\hat N$0, $\hat N$1, $\hat N$2, $\hat N$3 mm, and $\hat N$4. Gemini 2.0 achieves $\hat N$5, $\hat N$6, $\hat N$7, $\hat N$8 mm, and $\hat N$9. DeepSeek-VL2 achieves $\hat N = \arg\max_n P(n \mid I).$0, $\hat N = \arg\max_n P(n \mid I).$1, $\hat N = \arg\max_n P(n \mid I).$2, $\hat N = \arg\max_n P(n \mid I).$3 mm, and $\hat N = \arg\max_n P(n \mid I).$4. Qwen2-VL-7B achieves $\hat N = \arg\max_n P(n \mid I).$5, $\hat N = \arg\max_n P(n \mid I).$6, $\hat N = \arg\max_n P(n \mid I).$7, $\hat N = \arg\max_n P(n \mid I).$8 mm, and $\hat N = \arg\max_n P(n \mid I).$9. LLM4-IC8K achieves $\hat N$0, $\hat N$1, $\hat N$2, $\hat N$3 mm, and $\hat N$4 (Wang et al., 30 Jul 2025).

The ablation studies isolate two design choices. First, the dialogue strategy is best when all three tasks are asked in one CoT chain $\hat N$5; breaking them into separate or shuffled rounds degrades $\hat N$6 from 71.6% down to as low as 25.4%. Second, the data-staging strategy labeled T4, synthetic pre-training followed by real-world fine-tuning, yields 71.6% $\hat N$7, compared with 65.1% for real-only training (T1), 68.2% for joint real+synthetic training (T2), and 24.7% for synthetic-only training (T3). These results indicate that the reported performance depends not only on the backbone but also on the sequential prompting protocol and the synthetic-to-real training curriculum.

A further comparison is made to manual EDA workflows on the same 400 samples. Altium achieves $\hat N$8 $\hat N$9 at 7.0 minutes per sample, EAGLE achieves $N$0 at 15.0 minutes, KiCad achieves $N$1 at 15.0 minutes, and LLM4-IC8K achieves $N$2 at 0.26 minutes per sample. The reported numbers imply a clear separation between automation speed and absolute layout fidelity: the model is substantially faster per sample, while manual EDA tools remain stronger on $N$3.

6. Limitations, misconceptions, and projected directions

The reported limitations are specific and technically consequential. Extremely high pin-count packages greater than 600 may exceed the model’s token budget or yield degraded ordering accuracy. Unseen drawing conventions, including exotic fonts and very low-resolution scans, can still confuse the visual encoder. The supervised chain-of-thought approach also depends on accurate intermediate labels, and end-to-end errors in Task 1 propagate into later tasks. These limitations make clear that the framework is not an unconstrained parser for arbitrary IC documentation, but a structured pipeline whose later stages inherit uncertainty from earlier outputs (Wang et al., 30 Jul 2025).

Several misconceptions are addressed implicitly by the reported experiments. The manual EDA comparison indicates that LLM4-IC8K does not match Altium, EAGLE, or KiCad on overall layout IoU. This suggests that it is better understood as an automated footprint geometry interpretation system than as a direct replacement for manual EDA tooling. Likewise, the ablation results suggest that the improvement over off-the-shelf LMMs is not attributable solely to using Qwen2-VL-7B; the sequential CoT dialogue and the two-stage synthetic-to-real training procedure are both material contributors.

The paper outlines several future directions. One is reinforcement learning, exemplified by Group Relative Policy Optimization, to refine geometry outputs via a rendering-based reward. Another is an agentic architecture that can actively query additional context such as OCR transcriptions of dimension text. Additional proposals include scaling the real-world corpus beyond 4 K samples, augmenting with weakly supervised or web-mined datasheet images, and investigating multimodal retrieval or retrieval-augmented prompting to handle novel package types without full fine-tuning. In aggregate, these directions place LLM4-IC8K within a broader research trajectory toward multimodal systems that do not merely describe engineering drawings, but recover structured geometry from them with task-specific supervision and explicit reasoning stages (Wang et al., 30 Jul 2025).