CircuitGPS: Multi-Domain Circuit Systems

• CircuitGPS is a shared research label spanning multiple systems that couple circuit structure with localization, timing, and retrieval objectives.
• It leverages methodologies like hierarchical graph extraction, graph-edit-distance ranking, and few-shot learning for accurate diagram retrieval and parasitic capacitance prediction.
• Practical implementations demonstrate high precision in grid-based timing, real-time embedded vehicle tracking, and even quantum-secured geolocation, illustrating its multidisciplinary impact.

In the cited arXiv literature, CircuitGPS refers to several technically distinct systems rather than a single unified method. The name is used for a graph-based analog-circuit diagram retrieval pipeline, a few-shot graph-learning framework for parasitic-capacitance prediction in analog/mixed-signal (AMS) netlists, a precision-timing overlay on high-voltage transmission networks intended as a GNSS alternative, and several embedded GPS-centered vehicle tracking or intrusion-control implementations (Gao et al., 5 Feb 2025, Shen et al., 9 Jul 2025, Robson, 2023, Yaqzan et al., 2019, Güzel et al., 2018, Mustafa et al., 2020). Across these usages, the commonality is not application domain but the coupling of circuit structure with localization, timing, or retrieval objectives.

1. Terminological scope

The most precise way to treat the term is as a shared label across multiple research threads. In one thread, CircuitGPS retrieves analog-circuit diagrams by converting them into hierarchical graphs and ranking matches with graph-edit-distance (GED). In another, CircuitGPS is a few-shot learning method for parasitic-effect prediction in AMS circuits, using heterogeneous netlist graphs, subgraph sampling, and a GraphGPS-style encoder. In a third, CircuitGPS denotes a wired precision-timing network over electrical transmission grids, where chirp spread-spectrum signals disseminate time in a way intended to replace or back up GNSS. Separate implementation-oriented descriptions further use the label for GPS-enabled embedded systems in vehicle tracking and geolocation (Gao et al., 5 Feb 2025, Shen et al., 9 Jul 2025, Robson, 2023, Yaqzan et al., 2019, Güzel et al., 2018).

Usage	Core object	Representative paper
Circuit diagram retrieval	Hierarchical graph of devices, pins, and nets	(Gao et al., 5 Feb 2025)
AMS parasitic prediction	Heterogeneous netlist graph with coupling links	(Shen et al., 9 Jul 2025)
GNSS alternative timing	Chirp-based timing over PLC channels	(Robson, 2023)
Embedded GPS systems	NMEA/UART/GSM/FPGA vehicle platforms	(Yaqzan et al., 2019, Güzel et al., 2018, Mustafa et al., 2020)

A common misconception is to assume that all uses refer to GNSS or vehicle positioning. The literature does not support that reading. The graph-based uses are about circuit representation and retrieval or prediction, whereas the timing and vehicle systems are literal GPS or GNSS-related systems. This suggests that “CircuitGPS” functions primarily as a project name reused in different subfields, not as a stable acronym with a single accepted expansion.

2. Graph-based retrieval of analog-circuit diagrams

In "Circuit Diagram Retrieval Based on Hierarchical Circuit Graph Representation" (Gao et al., 5 Feb 2025), CircuitGPS is a retrieval system for analog-circuit diagrams that treats the problem as graph retrieval rather than conventional image retrieval. The pipeline has two phases: Circuit Diagram Recognition and Hierarchical Graph Retrieval. The recognition stage takes an RGB diagram image, performs object detection with an attention-augmented YOLOv8 model called GAM-YOLO, and then extracts topology via a 2-step connected domain filtering algorithm. The retrieval stage builds two graph representations and applies a coarse-to-fine GED-based search.

GAM-YOLO inserts a Global Attention Module (GAM) between the neck and head. Feature maps $P_1, P_2, P_3$ are reweighted by channel and spatial attention in series,

$$F_{\text{out}} = F_{\text{in}} \odot M_c(F_{\text{in}}) \odot M_s(F_{\text{in}}).$$

The head uses VariFocal Loss (VFL) for classification and Distribution Focal Loss (DFL)+CIoU for localization. On a 2 048 + 227 circuit-diagram dataset (23 304 labeled symbols), GAM-YOLO achieves precision=0.914, recall=0.907, mAP＠50=0.902 (Gao et al., 5 Feb 2025).

Topology extraction first converts the image to grayscale with

$GRAY=0.299R+0.587G+0.114B$

and binarizes using Otsu for light backgrounds and the Triangle method for dark backgrounds. The first connected-domain filter removes domains smaller than 10 % of total pixels to eliminate text and noise. The second removes any domain that does not intersect a detected component’s bounding box. By intersecting filtered net blobs with symbol boxes, the system recovers pin-to-net connectivity.

The retrieval stage uses two graph levels. The Class-1 (Device-only) graph has device symbols as nodes, with an edge between two devices if they share at least one net. The Class-4 (Device-plus-Pin) graph augments device nodes with pin nodes and uses edges both from devices to pins and between pins that are wired together. Node types are encoded as one-hot vectors $x_v \in \mathbb{R}^C$, and connectivity is represented by adjacency matrix $A$, where $A_{uv}=1$ if $(u,v)\in E$, else $0$.

Similarity is computed via normalized graph-edit-distance,

$$nGED(G_1,G_2)=\frac{GED(G_1,G_2)}{((|V_1|+|V_2|)/2)},$$

and converted to

$S(G_1,G_2)=\exp(-nGED(G_1,G_2)).$

GED is computed via an A*-based search [48]. Stage 1 computes $$F_{\text{out}} = F_{\text{in}} \odot M_c(F_{\text{in}}) \odot M_s(F_{\text{in}}).$$0 on Class-1 graphs and keeps the top 20. Stage 2 recomputes $$F_{\text{out}} = F_{\text{in}} \odot M_c(F_{\text{in}}) \odot M_s(F_{\text{in}}).$$1 on these candidates using Class-4 graphs and returns the top 5 final matches (Gao et al., 5 Feb 2025).

On the retrieval dataset of 503 diagrams across 10 circuit families, the reported AP＠5 / avg. time/query values are as follows:

Retrieval setting	AP＠5	Avg. time/query
Class-1 only	0.815	47.6 s
Class-4 only	0.881	252.1 s
Hierarchical (Class-1→Class-4)	0.881	57.9 s

The baselines are ResNet101+FC+cosine (mAP≈0.529), VGG16+SVD+QE (mAP≈0.627), and VGG16+PCA+QE (mAP≈0.416). The paper identifies three principal advantages: topology-aware discrimination, flexible fidelity through coarse and fine graphs, and a plug-and-play retrieval stage in which any GED or subgraph-matching engine can be used. Its stated limitations are equally explicit: GED remains NP-hard, edge labels are omitted in the prototype, and future work could weight “critical” blocks such as differential pairs more heavily (Gao et al., 5 Feb 2025).

3. Few-shot learning for AMS parasitic-capacitance prediction

In "Few-shot Learning on AMS Circuits and Its Application to Parasitic Capacitance Prediction" (Shen et al., 9 Jul 2025), CircuitGPS is a few-shot learning method for predicting parasitic effects in AMS circuits. The input is an AMS circuit netlist cast as a heterogeneous, undirected graph

$$F_{\text{out}} = F_{\text{in}} \odot M_c(F_{\text{in}}) \odot M_s(F_{\text{in}}).$$2

Each node carries

$$F_{\text{out}} = F_{\text{in}} \odot M_c(F_{\text{in}}) \odot M_s(F_{\text{in}}).$$3

and each schematic edge carries

$$F_{\text{out}} = F_{\text{in}} \odot M_c(F_{\text{in}}) \odot M_s(F_{\text{in}}).$$4

Coupling relations to be predicted are represented as additional link types,

$$F_{\text{out}} = F_{\text{in}} \odot M_c(F_{\text{in}}) \odot M_s(F_{\text{in}}).$$5

with every node also receiving a secondary attribute vector $$F_{\text{out}} = F_{\text{in}} \odot M_c(F_{\text{in}}) \odot M_s(F_{\text{in}}).$$6, such as transistor widths or counts of connected devices. The full graph is written as

$$F_{\text{out}} = F_{\text{in}} \odot M_c(F_{\text{in}}) \odot M_s(F_{\text{in}}).$$7

A central design choice is small-hop enclosing subgraph sampling. Given a target link $$F_{\text{out}} = F_{\text{in}} \odot M_c(F_{\text{in}}) \odot M_s(F_{\text{in}}).$$8, CircuitGPS extracts an $$F_{\text{out}} = F_{\text{in}} \odot M_c(F_{\text{in}}) \odot M_s(F_{\text{in}}).$$9-hop enclosing subgraph $GRAY=0.299R+0.587G+0.114B$0 defined by

$GRAY=0.299R+0.587G+0.114B$1

with edges restricted accordingly. In practice, the paper states that $GRAY=0.299R+0.587G+0.114B$2 suffices, both for efficiency and because of theoretically guaranteed $GRAY=0.299R+0.587G+0.114B$3-decay of high-order heuristics from SEAL [Zhang & Chen ’18]. Negative samples for link-prediction pre-training are constructed as structural negatives by endpoint permutation while preserving node-type compatibility.

The encoder follows the GraphGPS recipe [Rampášek et al. ’22], interleaving an edge-aware MPNN with a global Transformer block. For layer $GRAY=0.299R+0.587G+0.114B$4,

$GRAY=0.299R+0.587G+0.114B$5

$GRAY=0.299R+0.587G+0.114B$6

and

$GRAY=0.299R+0.587G+0.114B$7

Residual connections and batch normalization are applied after each block. Circuit-statistic vectors $GRAY=0.299R+0.587G+0.114B$8 are projected or embedded into $GRAY=0.299R+0.587G+0.114B$9 and added before global pooling and the task-specific MLP head (Shen et al., 9 Jul 2025).

To inject positional information with low overhead, the method defines double-anchor shortest-path distance (DSPD):

$x_v \in \mathbb{R}^C$0

These distances are embedded via learned look-up tables and concatenated with the node-type embedding to form

$x_v \in \mathbb{R}^C$1

The training pipeline has two stages. Pre-training minimizes binary cross-entropy for link prediction,

$x_v \in \mathbb{R}^C$2

with negatives balanced across $x_v \in \mathbb{R}^C$3, $x_v \in \mathbb{R}^C$4, $x_v \in \mathbb{R}^C$5 coupling types. Fine-tuning minimizes mean absolute error for capacitance regression,

$x_v \in \mathbb{R}^C$6

On three unseen benchmarks—DIGITAL_CLK_GEN, TIMING_CONTROL, and ARRAY_128_32—CircuitGPS achieves zero-shot link-existence accuracies of 0.980–0.989 versus 0.72–0.76 for ParaGraph/DLPL-Cap, described as a ≥20 pp improvement. In capacitance regression, it reduces MAE from ≈0.15 to ≈0.08 (a drop ≥0.067). The ablation results further show that DSPD yields the best accuracy (0.9618) at low cost (0.017 s/subgraph), and that a pure GatedGCN MPNN matches or slightly outperforms the MPNN+Transformer hybrid while requiring less compute (Shen et al., 9 Jul 2025).

4. Precision timing over electrical transmission grids

In "A GPS Alternative using Electrical Transmission Grids as Precision Timing Networks" (Robson, 2023), CircuitGPS is a precision-timing overlay on existing high-voltage transmission networks. It replaces or backs up GNSS by transmitting time-synchronised chirps over power-line carrier (PLC) channels and recovering 1 PPS ticks through high-resolution chirp cross-correlation. The system has a calibration stage, when GNSS is available and a remote substation measures the one-way time-of-flight (TOF), and an implementation stage, when GNSS is unavailable and the substation reconstructs the correct 1 PPS by subtracting the previously measured TOF from the received-chirp timestamp.

The transmitted linear chirp is modeled as

$x_v \in \mathbb{R}^C$7

with instantaneous frequency $x_v \in \mathbb{R}^C$8 and $x_v \in \mathbb{R}^C$9. The theoretical timing resolution is on the order of $A$0. For instance, $A$1 kHz yields a fundamental resolution of $A$2, while interpolation and larger bandwidths support sub-$A$3 accuracy.

Delay estimation is based on maximizing the cross-correlation of $A$4 with a local chirp copy,

$A$5

Rather than direct sliding-window correlation, the method dechirps the received signal and performs a single $A$6-point FFT, reducing complexity from $A$7 to $A$8. Fine interpolation is performed through $A$9 dechirp shifts of $A_{uv}=1$0, yielding

$A_{uv}=1$1

and

$A_{uv}=1$2

The paper states that modern CSS engines on FPGAs or DSPs can compute $A_{uv}=1$3 such correlations per second (Robson, 2023).

The network architecture consists of a central substation transmitter with a GNSS-disciplined timing module, chirp generator, upconversion to a PLC carrier around $A_{uv}=1$4–300 kHz, and a capacitive coupling network (TACS); and remote substation receivers with coupling taps, bandpass and low-noise amplification, ADC-to-FPGA chains, FFT processing, arg-max logic over fine-shifted bins, moving-average filtering, and timing reconstruction. A laboratory prototype uses $A_{uv}=1$5, $A_{uv}=1$6, $A_{uv}=1$7 kHz, and $A_{uv}=1$8 ms, implemented on a Xilinx FPGA with a 65 MSPS DAC/ADC pair (Robson, 2023).

ATP-EMTP simulations on the UK L6 extra-high-voltage network use JMarti frequency-dependent line models. Chirps of 81.92 ms, $A_{uv}=1$9 kHz, $(u,v)\in E$0, and $(u,v)\in E$1 are injected via a custom C++ foreign model. Noise is modeled by an $(u,v)\in E$2-stable process plus clipping of impulses above threshold. The signal-to-dispersion ratio is defined as

$(u,v)\in E$3

Monte Carlo runs show sub-$(u,v)\in E$4 timing standard deviation for $(u,v)\in E$5 dB, $(u,v)\in E$6 ns at $(u,v)\in E$7 dB, and insensitivity to impulsiveness down to $(u,v)\in E$8. The error variance is stated to track the linear-FM Cramér–Rao bound,

$(u,v)\in E$9

with further averaging over $0$0 chirps reducing noise by $0$1 (Robson, 2023).

In laboratory testing over a 700 m RG58 coax with delay $0$2, the recovered 1 PPS maintains sub-$0$3 RMS timing error down to an SNR of –20 dB. The paper further notes that EHV aerial modes attenuate only $0$4 dB/km at hundreds of kHz, so national-scale deployment is presented as plausible if averaging times and per-link SNR budgets are properly managed (Robson, 2023).

5. Embedded GPS and vehicle-security implementations

A separate group of CircuitGPS usages concerns embedded GPS-centered systems for vehicle tracking, geolocation filtering, and intrusion response. These systems are distinct from the graph-based retrieval and AMS-learning lines because they operate on NMEA streams, UART links, GSM modules, microcontrollers, or FPGA SoCs rather than graph matching or subgraph representation learning.

In the FPGA-based GPS Vehicle Tracking SoC described by Yaqzant, Damaj, and Zantout (Yaqzan et al., 2019), the top-level architecture includes a GPS RF/IF front end, NMEA parser & ASCII-to-binary converter, coordinate computation engine, soft-core microcontroller subsystem, memory interface & data buffering, and I/O control & RF transceiver interface. In the NMEA-only mode, the GPS module outputs ASCII at 9600 baud; a UART deserializer feeds a FIFO; a parser FSM scans for “\$0$$5GPGGA”</strong>; field delimiters select time, latitude, longitude, speed, and date; and an ASCII-to-binary converter handles <strong>ddmm.mmmm</strong> conversion. On an <strong>Altera Stratix-EP1S10F484C5</strong>, reported utilization is <strong>~6 000/10 570 LUTs (57$$0$618.50 at 1000 pcs (Yaqzan et al., 2019).

In the Arduino + SIM908 geolocation tool (Güzel et al., 2018), the system centers on an Arduino-compatible microcontroller board with a stackable SIM908 shield integrating quad-band GSM/GPRS and an integrated GPS L1-band receiver. The specifications reproduced in the source include ATmega328P @ 16 MHz, 5 V supply, 32 kB flash, 2 kB SRAM, and a SIM908 GPS receiver range of 1561.098 MHz–1587.250 MHz with −159 dBm tracking sensitivity. Typical wiring maps PWRKEY to digital pin 8, and routes TXD/RXD to Arduino serial pins. The GPS subsystem streams GPRMC, GPGGA and related NMEA sentences at 9600 baud for downstream parsing and reporting via HTTP or SMS. Two filtering methods are applied: a 1-D Kalman filter with $0$7 and $0$8,

$0$9

and a cumulative average filter

$nGED(G_1,G_2)=\frac{GED(G_1,G_2)}{((|V_1|+|V_2|)/2)},$0

In a clear-sky outdoor test in Ankara, Turkey with $nGED(G_1,G_2)=\frac{GED(G_1,G_2)}{((|V_1|+|V_2|)/2)},$1 consecutive fixes, reported errors were 9.39 m raw, 3.64 m last-error and 3.47 m minimum-error for the Kalman-filtered output, and 4.18 m for the average-filtered output (Güzel et al., 2018).

A related GPS-enabled vehicle intrusion-control system (Mustafa et al., 2020) integrates Holux GR-89 GPS, SIM300CZ GSM, an 8052 µC (AT89S52 class), Mercury Tilt Switches, and relay control for gears and engine. The GPS module is wired with VCC (3.3 V), GND, TXD to 8052 P3.0 (RxD), and RXD from 8052 P3.1 (TxD), using a level shifter if the microcontroller is 5 V. The GR-89 outputs standard NMEA-0183 at 4800 bps by default and is often configurable to 9600 bps. Firmware listens for GPRMC, verifies checksum, parses latitude and longitude, converts from ddmm.mmmm or dddmm.mmmm to decimal degrees,

$nGED(G_1,G_2)=\frac{GED(G_1,G_2)}{((|V_1|+|V_2|)/2)},$2

and sends location via AT+CMGF=1 and AT+CMGS on the GSM link. The paper-level description states that on intrusion, the owner can respond by SMS to lock the gears or seize the engine from a far-off place (Mustafa et al., 2020).

System	Main hardware	Reported outcome
FPGA vehicle tracking SoC	Stratix FPGA, soft-core CPU, parser, BRAM, UART/I²C	~17 μs parsing, ≥50 Hz sampling (Yaqzan et al., 2019)
Arduino geolocation tool	Arduino/ATmega328P + SIM908	9.39 m raw to 3.64 m Kalman last-error (Güzel et al., 2018)
Intrusion-control GPS path	8052 + Holux GR-89 + SIM300CZ	SMS alert and remote gear/engine control (Mustafa et al., 2020)

These systems are concrete embodiments of GPS-centered embedded design. They are not retrieval engines and do not use graph similarity; instead, they are organized around UART framing, NMEA parsing, RF front ends, relay actuation, and low-cost filtering or hardware acceleration.

6. Related quantum-secured GPS and broader implications

A further GPS-related line of work, while not presented as the same system as the graph-based or embedded CircuitGPS variants, is the device-independent quantum-secured GPS protocol of (Kam et al., 11 Apr 2025). Its core is a self-test of a genuinely multipartite entangled five-qubit code via a Bell-type inequality, then embedding that self-test into a GNSS positioning loop so that tampering spoils the certified Bell violation. The protocol begins with the CHSH functional

$$nGED(G_1,G_2)=\frac{GED(G_1,G_2)}{((|V_1|+|V_2|)/2)},$$3

and extends to a five-party Bell functional $$nGED(G_1,G_2)=\frac{GED(G_1,G_2)}{((|V_1|+|V_2|)/2)},$$4 whose maximum $$nGED(G_1,G_2)=\frac{GED(G_1,G_2)}{((|V_1|+|V_2|)/2)},$$5 is certified by a sum-of-squares decomposition. Achieving this maximum self-tests the two-dimensional code space spanned by $$nGED(G_1,G_2)=\frac{GED(G_1,G_2)}{((|V_1|+|V_2|)/2)},$$6 and $$nGED(G_1,G_2)=\frac{GED(G_1,G_2)}{((|V_1|+|V_2|)/2)},$$7 (Kam et al., 11 Apr 2025).

For GPS authentication, the paper replaces a classical code with a flying encoded state $$nGED(G_1,G_2)=\frac{GED(G_1,G_2)}{((|V_1|+|V_2|)/2)},$$8 distributed among four satellites and the receiver. Before pseudorange use, the parties estimate $$nGED(G_1,G_2)=\frac{GED(G_1,G_2)}{((|V_1|+|V_2|)/2)},$$9; if the violation falls below $S(G_1,G_2)=\exp(-nGED(G_1,G_2)).$0, the protocol aborts. The paper assumes an adversary can intercept up to two of the five qubits in any round and argues that three or more tampered qubits are required to evade detection while preserving encoded data. The five-qubit encoder circuit uses 4 Hadamard gates and 8 CNOTs, with depth

$S(G_1,G_2)=\exp(-nGED(G_1,G_2)).$1

Reported platform comparisons give $S(G_1,G_2)=\exp(-nGED(G_1,G_2)).$2 ns and $S(G_1,G_2)=\exp(-nGED(G_1,G_2)).$3 for superconducting qubits, versus $S(G_1,G_2)=\exp(-nGED(G_1,G_2)).$4 and $S(G_1,G_2)=\exp(-nGED(G_1,G_2)).$5 for trapped ions (Kam et al., 11 Apr 2025).

This quantum-secured line is methodologically remote from the graph-retrieval and AMS-learning versions of CircuitGPS, but it highlights a recurrent theme across the broader literature: circuit structure is used not merely as hardware implementation detail, but as a formal object for inference, certification, or control. In the retrieval and AMS settings, structure is represented as graphs; in the timing-network setting, as a transmission medium with modeled propagation; in the embedded systems setting, as a tightly coupled signal-processing and communication pipeline; and in the quantum-secured setting, as a code space certified by Bell nonlocality. A plausible implication is that the recurrence of the name reflects a shared emphasis on circuit-aware system design, even though the technical content diverges sharply across domains.