Papers
Topics
Authors
Recent
Search
2000 character limit reached

FlowPlace: Macro Placement Framework

Updated 4 July 2026
  • FlowPlace is a flow-matching generative framework for chip macro placement that transforms synthetic priors into optimized, legal layouts.
  • It employs a three-stage pipeline—mask-guided synthetic data generation, deterministic flow matching, and hard-constraint sampling—to ensure efficiency and legality.
  • Empirical results on OpenROAD and ICCAD benchmarks demonstrate 10–50× faster sampling and improved PPA metrics compared to traditional RL and diffusion-based placers.

Searching arXiv for papers on FlowPlace and closely related work to ground the article. FlowPlace is a flow-matching–based generative framework for macro placement in chip physical design. It was introduced to address three persistent issues in learning-based placers: weak priors in synthetic pretraining data, slow sampling due to long stochastic trajectories, and illegal layouts from soft constraint handling during generation. The framework combines mask-guided synthetic data, deterministic probability flows with flexible prior choices, and hard-constraint guided sampling that guarantees zero overlaps. On the OpenROAD and ICCAD 2015 benchmarks, it is reported to achieve better PPA metrics, 10–50×\times faster sampling efficiency, and zero overlaps (Xie et al., 26 Apr 2026).

1. Problem formulation and motivation

FlowPlace is designed for the chip placement problem at macro level. Given a chip canvas with fixed outline and a set of movable modules VV with sizes {(wi,hi)}\{(w_i,h_i)\} and netlist hypergraph G=(V,E)G=(V,E), the objective is to find coordinates {(xi,yi)}\{(x_i,y_i)\} for NN modules such that hard constraints are satisfied and placement quality objectives are optimized. The hard constraints are boundary containment and non-overlap among rectangles. The quality objectives include half-perimeter wirelength (HPWL), timing such as worst negative slack and total negative slack, congestion, density, and area. A typical macro-level formulation is

minJ(x)=αHPWL(x)+βCong(x)+γTiming(x)+\min J(x)=\alpha\cdot HPWL(x)+\beta\cdot Cong(x)+\gamma\cdot Timing(x)+\dots

subject to xiΩx_i\in\Omega and pairwise non-overlap of rectangles. One common HPWL surrogate is

HPWL(x)=k(maxinet kximininet kxi+maxinet kyimininet kyi).HPWL(x)=\sum_k \left(\max_{i\in net\ k}x_i-\min_{i\in net\ k}x_i+\max_{i\in net\ k}y_i-\min_{i\in net\ k}y_i\right).

These definitions place FlowPlace within the standard macro-placement setting rather than mixed-size or standard-cell placement proper (Xie et al., 26 Apr 2026).

The method is motivated by shortcomings in prior learning-based and analytic approaches. RL placers place macros sequentially, are sample-inefficient, and accumulate early mistakes. Diffusion-based placers such as ChipDiffusion pretrain on purely random synthetic layouts, require long stochastic sampling trajectories, use fixed Gaussian sources, and rely on gradient-based guidance that is a soft correction with hyperparameter sensitivity and no legality guarantee. Classical analytic placers such as DREAMPlace and RePlAce optimize differentiable proxies and typically relax non-overlap, requiring separate legalization that can hurt final PPA. FlowPlace is therefore framed as a response to weaknesses in priors, sampling efficiency, and legality handling (Xie et al., 26 Apr 2026).

2. Generative pipeline and prior injection

FlowPlace is organized as a three-stage pipeline. The first stage is mask-guided synthetic data generation. A GPU-parallelized, boundary-aware process produces scalable synthetic macro placements that mimic domain regularities such as large macros near the periphery, then reverse-engineers netlists via spatial pin proximity. The second stage is flow matching training with flexible priors, where the model learns a deterministic velocity field mapping a simple source distribution p0p_0 to the data distribution VV0 in 20–50 steps. The third stage is hard-constraint guided sampling, in which each integration step extrapolates toward a predicted terminal layout, projects it onto the legal non-overlap set, and interpolates back so that legality is enforced progressively during generation (Xie et al., 26 Apr 2026).

The synthetic-data component replaces random layouts with prior-infused data. The canvas VV1 is partitioned into a uniform grid with candidate cells VV2. Macros are placed in descending size order. For each macro VV3, FlowPlace computes a binary mask VV4 of legal cells under occupancy and boundary constraints, assigns a boundary-aware score

VV5

and samples positions according to

VV6

Netlists are then synthesized by generating pin offsets per macro and wiring spatially proximate pins. This modular scoring scheme is explicitly intended to inject realistic boundary bias into VV7.

Prior injection also enters through the source distribution VV8. Unlike diffusion models fixed to Gaussian VV9, FlowPlace can choose {(wi,hi)}\{(w_i,h_i)\}0 flexibly. The reported ablations state that a uniform distribution over the canvas performs better than Gaussian priors for HPWL and legality, and that uniform {(wi,hi)}\{(w_i,h_i)\}1 over the canvas yields the best HPWL among the tested source priors. The framework also allows additional priors such as keep-out regions, macro class alignment, and pin-access constraints to be introduced by modifying the scoring function {(wi,hi)}\{(w_i,h_i)\}2 or the masks {(wi,hi)}\{(w_i,h_i)\}3. The paper further notes that while it does not add explicit timing or congestion priors to the velocity field, the framework can incorporate potentials {(wi,hi)}\{(w_i,h_i)\}4 whose gradients act as guidance, for example {(wi,hi)}\{(w_i,h_i)\}5 (Xie et al., 26 Apr 2026).

3. Flow-matching formulation and model architecture

The mathematical basis of FlowPlace is probability flow. A distribution {(wi,hi)}\{(w_i,h_i)\}6 over time {(wi,hi)}\{(w_i,h_i)\}7 is transported by a velocity field {(wi,hi)}\{(w_i,h_i)\}8 satisfying the continuity equation

{(wi,hi)}\{(w_i,h_i)\}9

with sample dynamics

G=(V,E)G=(V,E)0

Because the true velocity field is unknown, FlowPlace parameterizes it by a network G=(V,E)G=(V,E)1 and trains it by conditional flow matching. Using the linear interpolant

G=(V,E)G=(V,E)2

the conditional velocity is constant,

G=(V,E)G=(V,E)3

and the training objective is

G=(V,E)G=(V,E)4

At inference, the learned ODE is integrated with Euler steps:

G=(V,E)G=(V,E)5

This gives FlowPlace a deterministic generative trajectory rather than the stochastic reverse-time process typical of diffusion models (Xie et al., 26 Apr 2026).

The representation and network reflect the macro-placement domain. Macros are nodes with normalized features G=(V,E)G=(V,E)6, edges carry pin offset pairs G=(V,E)G=(V,E)7 for macro connections, and coordinates are represented as G=(V,E)G=(V,E)8. The velocity-field network alternates GATv2 layers, which capture local connectivity on the hypergraph, with multi-head self-attention for global interactions. Time G=(V,E)G=(V,E)9 is sinusoidally embedded and fused with node features, and an MLP decoder outputs per-macro velocities. Training uses conditional flow matching with linear interpolants and requires no noise schedules. Inference solves a deterministic ODE via Euler with 20–50 steps.

A plausible contextual analogy is to "LayoutFlow" (Guerreiro et al., 2024), which also applies Flow Matching with linear interpolation and Euler integration to layout generation. The difference is that FlowPlace specializes the formulation to macro placement, where legality and netlist-aware conditioning are central rather than merely geometric plausibility.

4. Hard-constraint sampling and legality guarantees

A defining component of FlowPlace is hard-constraint guided sampling. Let {(xi,yi)}\{(x_i,y_i)\}0 denote projection of a macro layout onto the feasible non-overlap region. At sampling step {(xi,yi)}\{(x_i,y_i)\}1, the method first extrapolates to a predicted final state,

{(xi,yi)}\{(x_i,y_i)\}2

then projects this prediction to a legal layout,

{(xi,yi)}\{(x_i,y_i)\}3

and finally corrects the trajectory using

{(xi,yi)}\{(x_i,y_i)\}4

The corresponding pseudocode initializes {(xi,yi)}\{(x_i,y_i)\}5, iterates over {(xi,yi)}\{(x_i,y_i)\}6, applies extrapolation, hard projection, velocity correction, and interpolation, and returns {(xi,yi)}\{(x_i,y_i)\}7 (Xie et al., 26 Apr 2026).

The legalization operator performs greedy legalization on the grid. It chooses non-overlapping cells close to the predicted positions and canvas boundary, minimizing adjustment, while geometric checks and occupancy updates are GPU-parallelized. The reason legality is guaranteed is explicit in the method description: projection enforces exact non-overlap and boundary constraints at every step, and the subsequent interpolation preserves a smooth trajectory while avoiding the soft tradeoff and hyperparameter sensitivity of gradient guidance.

The geometric non-overlap condition is formulated exactly for axis-aligned rectangles. For rectangles {(xi,yi)}\{(x_i,y_i)\}8 and {(xi,yi)}\{(x_i,y_i)\}9, overlap is avoided by ensuring

NN0

with all rectangles contained within NN1. This is significant because many placement pipelines treat non-overlap as a relaxed penalty and rely on later legalization; FlowPlace instead incorporates legality into the generative trajectory itself (Xie et al., 26 Apr 2026).

5. Empirical evaluation and ablation results

FlowPlace is evaluated on two benchmark flows. On ICCAD 2015 Contest C, comprising 8 “superblue” designs with hundreds of macros and millions of cells, standard-cell placement is performed with DREAMPlace 4.1 and PPA metrics are extracted with Cadence Innovus EarlyGlobalRoute. On OpenROAD-flow-scripts, comprising 6 Nangate45 designs, the full OpenROAD flow is used, including global placement, detailed placement, optimization, clock-tree synthesis, and routing. The reported metrics include routed wirelength, horizontal and vertical overflow, worst negative slack, total negative slack, power, and cell area (Xie et al., 26 Apr 2026).

On ICCAD 2015, FlowPlace is reported to achieve the best average ranks across key metrics: rWL 1.62, rO-H 1.00, rO-V 1.25, WNS 2.62, and TNS 2.25. It delivers overlap-free layouts (0%) and lower wirelength than DREAMPlace, MaskPlace, EfficientPlace, and ChipDiffusion. The paper gives superblue7 as an example with NN2 and Overlap = 0%. On OpenROAD, FlowPlace is reported to rank best across timing, power, area, and rWL, with improved WNS/TNS and competitive power/area relative to DREAMPlace and EfficientPlace, and better results than ChipDiffusion and MaskPlace. Sampling is stated to be 10–50NN3 faster than diffusion, and zero-shot inference is reported to produce high-quality macro placements in seconds (Xie et al., 26 Apr 2026).

The ablations attribute these gains to both data priors and source-prior choice. Mask-guided synthetic pretraining improves average ranks across rWL, WNS, TNS, rO-H, and rO-V relative to random synthetic generation. For source priors, uniform NN4 achieves the best HPWL, with average ratio 1.019 versus Gaussian 1.067, and keeps initial samples within the canvas. Visualizations are described as showing periphery anchoring and macro footprint regularity, including tiling of same-sized macros, together with lower routed congestion versus baselines. The reported computational complexity further states that deterministic ODE sampling with 20–50 Euler steps scales as NN5 per sample and that legalization overhead is negligible because its checks are GPU-parallelized (Xie et al., 26 Apr 2026).

6. Research context and alternate uses of the term

Within chip placement, FlowPlace is positioned against three major lines of prior work. Analytical placers include RePlAce, DREAMPlace, timing-driven DREAMPlace 4.0/4.1, NTUplace4dr, Ripple, and POLAR. RL placers include Nature’s graph placer, MaskPlace, EfficientPlace, ChipFormer, and LaMPlace. Generative placers include ChipDiffusion. The central distinction claimed for FlowPlace is that it avoids sequential RL decision-making and the soft-constraint or post-hoc-legalization pattern of analytic and diffusion-based placers by integrating deterministic flow matching with progressive hard legality enforcement (Xie et al., 26 Apr 2026).

The label “FlowPlace” also appears in other arXiv contexts with different meanings. In "AeroPlace-Flow" (Mishra et al., 8 Mar 2026), a “FlowPlace” procedure denotes language-grounded aerial object placement in which a goal image is synthesized from instruction and RGB-D observations, metrically grounded in 3D, and converted into a collision-aware object flow for execution by an aerial manipulator. In "Flow Field Reconstruction with Sensor Placement Policy Learning" (Li et al., 13 May 2026), FlowPlace denotes a flow-aware sensor placement and reconstruction system that combines a directional transport-aware GNN with Two-Step Constrained PPO for boundary sensor placement. In "Flow and Density Reconstruction and Optimal Sensor Placement for Road Transportation Networks" (Lovisari et al., 2015), “FlowPlace” is a framing for flow-informed sensor placement via conservation laws, splitting ratios, and a Virtual Variances relaxation.

Usage Domain Core meaning
FlowPlace (Xie et al., 26 Apr 2026) Chip physical design Flow matching for macro placement with hard legality
“FlowPlace” in AeroPlace-Flow (Mishra et al., 8 Mar 2026) Aerial manipulation Object-centric flow for language-grounded placement
FlowPlace (Li et al., 13 May 2026); “FlowPlace methodology” (Lovisari et al., 2015) Sensor placement and reconstruction Flow-aware sensor placement under constraints

This multiplicity of usages suggests that “FlowPlace” has become a broader descriptor for placement systems that operate through explicit flow, transport, or flow-informed optimization. In the strict bibliographic sense, however, the primary standalone use of the title refers to macro placement for chip design (Xie et al., 26 Apr 2026).

7. Limitations and prospective directions

FlowPlace targets macro placement only. Standard cells are explicitly handled downstream by analytic placers, so extension to mixed-size joint placement remains challenging. Additional constraints such as IR drop, thermal effects, pin access, clock and power constraints, and multi-voltage domains are not explicitly modeled. The framework description states that such factors could be incorporated through masks NN6, richer conditioning, or priors of the form NN7. Very large SoCs and heterogeneous macro types may require hierarchical or multi-stage flows, and the paper identifies learning richer priors from RTL or dataflow as a further direction (Xie et al., 26 Apr 2026).

The same source identifies several methodological directions. These include constrained ODE solvers, optimal-transport variants for placement, tighter integration with timing-driven analyses such as OpenTimer, and learning priors from real data. A plausible implication is that the main research significance of FlowPlace lies not only in its benchmark performance, but in its reformulation of placement as deterministic transport over a legality-constrained state space. In that view, synthetic-data priors, source-distribution choice, and exact projection are not auxiliary heuristics but the core structural ingredients of the method’s design (Xie et al., 26 Apr 2026).

Topic to Video (Beta)

No one has generated a video about this topic yet.

Whiteboard

No one has generated a whiteboard explanation for this topic yet.

Follow Topic

Get notified by email when new papers are published related to FlowPlace.