In-Situ Refreshable Architecture

• In-Situ Refreshable Architecture is a design principle where mutable state is updated directly on the physical substrate, enabling continuous reconfiguration and calibration.
• It encompasses diverse systems such as photonic neural networks, DRAM controllers, memristive networks, and tactile interfaces that optimize in-place operations.
• The approach integrates live data visualization, hardware-in-the-loop training, and dynamic scheduling to efficiently manage performance under realistic constraints.

Searching arXiv for recent and foundational papers relevant to “In-Situ Refreshable Architecture.” In-Situ Refreshable Architecture denotes a class of systems in which state, parameters, configuration, or presentation are updated directly on the physical substrate or live execution path, rather than through full off-line reconstruction or repeated migration to an external processing stage. In the cited literature, the term spans DRAM refresh that overlaps with accesses, photonic and memristive neural hardware whose tunable elements are corrected on chip, explicit memories that accumulate new classes by update-in-place, optical processors whose topology is searched on the deployed device, visualization systems that render from live accelerator memory, and tactile interfaces whose displayed content is refreshed where interaction occurs (Ranjan et al., 2 Apr 2026, Wang et al., 17 Apr 2026, Chang et al., 2017, Karunaratne et al., 2022, Matthes et al., 2016, Reinders et al., 17 Feb 2026).

1. Conceptual scope and recurring architectural pattern

The phrase is used in more than one technical sense, but the recurring pattern is stable. A refreshable system maintains a mutable state that remains physically resident in the same medium that performs the task: thermo-optic phase shifters and microring biases in photonic CNNs, DMD bitplanes and readout partitions in scattering-based optical processors, PCM conductance states in explicit memories, DRAM bank or subarray contents under periodic refresh, or live visualization and tactile states resident on the same compute node or display surface (Ranjan et al., 2 Apr 2026, Wang et al., 17 Apr 2026, Karunaratne et al., 2022, Chang et al., 2017, Matthes et al., 2016, Abram et al., 2021).

A second recurring property is that refresh is not merely reloading. In several systems it is adaptive correction under real hardware response: SPSA on photonic phase shifters, Adam updates of DMD parameters and thresholds, progressive crystallization of PCM cells, supervised in-situ STDP in memristive SNNs, or dynamic bank/subarray scheduling in DRAM (Ranjan et al., 2 Apr 2026, Wang et al., 17 Apr 2026, Karunaratne et al., 2022, Prajapati et al., 28 Jul 2025, Chang et al., 2017). In other systems refresh means maintaining a live, externally visible representation without staging through disk or host-side transformation, as in ISAAC, Galaxy-coupled MPM, libyt, and refreshable tactile displays (Matthes et al., 2016, Abram et al., 2021, Tsai et al., 11 Dec 2025, Reinders et al., 17 Feb 2026).

Context	Refreshed object	In-situ mechanism
Photonic neural hardware	Phase shifters, microring biases	Digital twin plus SPSA
Optical scattering processor	DMD patterns, thresholds, architecture	Hardware-in-the-loop optimization and NAS
PCM explicit memory	Class-prototype columns	Progressive crystallization
DRAM	Bank and subarray availability during refresh	DARP and SARP
Live visualization and interaction	Visualization state, tactile highlights, analysis callbacks	Zero-copy rendering, asynchronous steering, incremental updates

This breadth makes the term partly architectural and partly methodological. A plausible implication is that “in-situ refreshable” is best understood as an umbrella descriptor for systems that preserve locality of state while permitting repeated correction, reconfiguration, or presentation.

2. Physical substrates and update-in-place mechanisms

In photonic computing, refreshability is embodied by tunable optical devices whose learned state must survive fabrication nonidealities, thermal coupling, and drift. The fully photonic CNN of “Photonic convolutional neural network with pre-trained in-situ training” realizes convolutional and fully connected layers with rectangular Clements meshes of Mach–Zehnder interferometers, uses a 10×10 mesh in the first convolutional layer, and contains 2,132 on-chip tunable parameters, 32 microring resonators, 8 WDM channels, and an 18 × 18 mm² die. Its digital twin pre-training reaches 96.92% MNIST test accuracy, hardware transfer yields 94.23%, severe thermal crosstalk gives 93.80%, and 100 SPSA iterations recover 94.00%; the system reports ≈0.8 μs latency, ≈12.4 μJ per inference, ≈0.32 TOPS, ≈46.2 pJ/OP, and 100–242× better single-image energy efficiency than state-of-the-art GPUs (Ranjan et al., 2 Apr 2026). The linear optical core is parameterized by

$$U(\theta, \phi) = \begin{pmatrix} e^{i\phi} \cos \theta & e^{i\phi} \sin \theta \ -\sin \theta & \cos \theta \end{pmatrix},$$

with cascaded Clements meshes implementing the coherent transforms (Ranjan et al., 2 Apr 2026).

TRON extends the same logic to a very different optical substrate. It couples a multi-scattering medium to a 912×1140-mirror DMD, a 532.3 nm CW laser, and a 2048×1088 CMOS camera with 8-bit quantization. The DMD refreshes at 2880 Hz in continuous streaming and up to 4220 Hz burst, while the camera reaches ≈340 Hz at full frame and up to 5.5 kHz with row-windowing. Its in-situ refresh includes not only parameter updates but also architecture changes: number of time-multiplexed passes, width, skip connections, pixel partition, and readout regioning. Reported results include 79.02% test accuracy on 3D MedMNIST Organ, 51.67% on 3D MedMNIST Fracture, and 82.46% test accuracy with 0.94 AUC on Leukemia RNAseq (Wang et al., 17 Apr 2026). Here the effective optical mapping is explicitly tied to physical optics,

$I = |T [B(x; t); m(\theta)]|^2 + \epsilon,$

so refresh operates on a live optical operator rather than an abstract weight tensor (Wang et al., 17 Apr 2026).

In-memory and memristive systems use still another material basis for refresh. The PCM explicit memory for few-shot continual learning stores one class prototype per column in a 256×256 PCM IMC core and updates it by progressive crystallization. Each support vector is accumulated in place through fine SET pulses with peak current 150 μA, flat duration 5 ns, trailing edge 40 ns, and source voltage 2.34 V; energy per programming cycle is ≈ 8.78 pJ per device, update time per class vector is ≈11.5 μs, and in-situ accumulation saves ≥4.7× programming energy versus programming “from scratch.” Hardware accuracy remains within 1.28%–2.5% of the state-of-the-art full-precision baseline software model on CIFAR-100 and miniImageNet when learning 40 novel classes on top of 60 old classes (Karunaratne et al., 2022). The memristive SNN architecture likewise updates weights directly in the crossbar. It uses a 1T1M topology, supervised in-situ STDP, a purely analog lateral inhibition circuit, and no external microcontroller or ancillary control hardware; reported results are 99.11% on Iris, 97.9% on BCW, perfect recognition on the 5×3 patterns, and 93.4% average recognition under 20% input noise (Prajapati et al., 28 Jul 2025).

DRAM literature gives the term a more literal meaning: refresh as a mandatory physical maintenance operation whose interference with accesses must itself be architected. DARP makes per-bank refresh out-of-order and access-aware, while SARP permits a bank to serve accesses to one idle subarray while another subarray is being refreshed. DSARP improves weighted speedup over all-bank refresh by +3.3% / +7.2% / +15.2% on average for 8/16/32 Gb, and by +7.9% / +12.3% / +20.2% over per-bank refresh, with maximum gains up to 27.0% and 36.6%, respectively (Chang et al., 2017). In this usage, refreshability is the ability to keep the memory fabric productive while refresh proceeds in situ.

3. Training, calibration, and hardware-in-the-loop optimization

A major strand of this literature treats refreshability as a training and calibration problem. The photonic CNN introduces a mathematically exact differentiable digital twin that matches the hardware simulation with < 10^{-15} absolute error at the individual MZI level, enabling 1-to-1 phase transfer and subsequent in-situ SPSA fine-tuning (Ranjan et al., 2 Apr 2026). Its update rule is

$$\hat{g}_i(\boldsymbol{\theta}) = \frac{f(\boldsymbol{\theta} + c\boldsymbol{\Delta}) - f(\boldsymbol{\theta} - c\boldsymbol{\Delta})}{2c\, \Delta_i}, \qquad \theta_i^{(t+1)} = \theta_i^{(t)} - a_t \, \hat{g}_i(\boldsymbol{\theta}^{(t)}),$$

with layerwise multipliers of ×0.3 for Conv1, ×0.5 for Conv2, ×1.0 for FC1, ×2.0 for NOFU, and ×3.0 for FC2 (Ranjan et al., 2 Apr 2026). The architecture is therefore refreshable not because it stores weights in a conventional SRAM hierarchy, but because the physical phases and biases can be re-anchored against the live optical loss surface.

TRON uses a related but broader hardware-in-the-loop loop. A calibrated digital twin is fit by sampling 5×10^4 Bernoulli input patterns with $p=0.5$ and regressing the camera-level model with a learnable noise term of hidden size 2000. Forward passes remain optical, while backward passes use a straight-through estimator with HardTanh surrogate for binary DMD gates, and parameters are updated by Adam directly on the device. Architecture search is also in situ: Optuna TPESampler explores a feedforward search space over passes, width, skip connections, pixel partition, and readout regioning, while MedianPruner discards unpromising trials. Warm-up in-silico training for 20 epochs is followed by in-situ training for 25 epochs (Wang et al., 17 Apr 2026). This makes refresh a joint optimization of parameters and topology under real hardware noise, quantization, and dynamic-range limits.

The PCM explicit memory separates feature learning from in-situ accumulation. A stationary ResNet-12 controller is pretrained and then frozen; continual learning proceeds entirely by in-situ updates to the explicit memory. Support vectors are binarized as $b(x)=\operatorname{sign}(f(x))$, physically superposed on the class column, and later queried by 4-quadrant matrix–vector multiply. Prototype accumulation is expressed as

$\hat{c}_j = \sum_{i=1}^{K} b(x_i),$

with differential conductance $\Delta G_{k,j} = G^+_{k,j} - G^-_{k,j}$ storing the signed sum (Karunaratne et al., 2022). This formulation shifts refreshability away from retraining the controller and toward in-place class-memory growth.

The memristive SNN pursues full controller-free on-chip learning. Pre-spikes are 1.1 V triangular pulses with 1 μs rise and fall, below the +1.2 V write threshold, while update voltages are +1.4 V and −2.6 V. The implemented supervised STDP law is summarized as

$$\Delta G_{ji} = \eta\, g_{\text{sup}}(j)\, \operatorname{sgn}(\Delta t_{ij}) e^{-|\Delta t_{ij}|/\tau},$$

with $g_{\text{sup}}(j)=1$ only for the teacher-labeled winning neuron (Prajapati et al., 28 Jul 2025). Refresh is therefore immediate presentation-driven plasticity rather than a separate maintenance phase.

A common misconception is that in-situ refreshability necessarily entails purely local learning with no digital model. The evidence is mixed. The photonic CNN and TRON both rely on digital twins and digital optimization for gradients or initialization, whereas the memristive SNN and PCM explicit memory place the update primitive directly in the analog substrate (Ranjan et al., 2 Apr 2026, Wang et al., 17 Apr 2026, Prajapati et al., 28 Jul 2025, Karunaratne et al., 2022).

4. Live data, visualization, and interaction on the running system

In high-performance computing and human–computer interaction, the same architectural idea appears as live-state refresh instead of weight refresh. ISAAC is a header-only C++ template library that visualizes simulation data directly on the same compute node and accelerator where the data already reside. It uses source accessors, functor chains, Alpaka kernels, IceT compositing, JPEG compression on rank 0, and JSON/TCP/WebSocket steering. On 4096 Nvidia Tesla K20X GPUs running PIConGPU, timestep time remained ~0.93 s, and ISAAC’s visualization overhead settled to ~8% of total runtime from 256 GPUs upward; base64 adds ~33% payload overhead, but compression and network transmission run concurrently on the root rank’s CPU (Matthes et al., 2016). Refreshability here means continuously updated visualization and asynchronous steering without deep copies or data transformation.

The Galaxy–Material Point Method interface for regional-scale natural hazards uses a loose asynchronous M:N coupling between MPM workers and Galaxy visualization workers. In the Oso landslide case study, the architecture visualized a 1500 × 1500 × 270 m domain with 4.2 million material points as spheres, streaming every 100 MPM steps. For a run from checkpoint at step 50,000 over 25,000 steps, 5,000 steps took ~2 h 23 min without visualization and ~2 h 26 min with visualization, implying a 2% amortized runtime increase; Galaxy rendered a visualization timestep in ~6.5 s while MPM needed ~3 minutes for the corresponding 100 steps (Abram et al., 2021). The refreshable aspect is explicit: new views can be added mid-run, and the renderer can drop frames rather than blocking the solver.

libyt generalizes this pattern to Python and Jupyter workflows. It embeds CPython per MPI rank, wraps intrinsic arrays into read-only NumPy arrays without duplication, generates derived fields on demand, and redistributes remote data via MPI one-sided RMA. Reported overheads are approximately 3–5% for core-collapse supernovae, 3% for the dwarf-galaxy workflow, and 15% for fuzzy dark matter; for a 9.0×10^8-cell AMR dataset, libyt is 20–45% faster in wall time than post-processing in a strong-scaling comparison (Tsai et al., 11 Dec 2025). Interactive refresh can be triggered through a Python REPL, file-based reload, or a simulation-launched Jupyter kernel.

The tactile-display architecture extends in-situ refreshability to multimodal interaction. It combines a Dot Pad RTD with a 60×40 pin matrix, an Ultraleap Leap Motion Controller 2 at 120 fps mounted 20 cm above the device at a 35° downward angle, a Unity-based Interaction Manager, and a GPT-4o-based Conversational Agent orchestrated through MQTT. USB serial runs at 115,200 baud, and deictic references are attached when the classifier confidence is at least 0.40 (Reinders et al., 17 Feb 2026). Tactile highlights, Braille labels, and speech are refreshed in place as the user touches the display and asks context-aware questions. This shifts the locus of refresh from hardware calibration to perceptual grounding.

These systems share a precise property: they avoid a post hoc workflow in which raw state is first written, then later analyzed elsewhere. The refreshed representation is produced where the computation or interaction already occurs.

5. Scheduling, modularity, and system-level reconfiguration

Another important usage of refreshable architecture concerns how a system is scheduled, partitioned, or physically reassembled. In DRAM, DARP and SARP are controller and device mechanisms for reordering refresh and exploiting subarray independence. DARP tracks per-bank refresh state and pulls refreshes into write-drain intervals, while SARP adds the internal control needed for a bank to service one subarray as another refreshes. The governing safety condition is that a bank must receive refresh within a bounded window, expressed as $$\Delta t_{\text{refresh}}(b) \leq 9 \cdot tREFI_{pb}$$, while power-safe overlap scales $I = |T [B(x; t); m(\theta)]|^2 + \epsilon,$0 and $I = |T [B(x; t); m(\theta)]|^2 + \epsilon,$1 by the current-overhead factor (Chang et al., 2017). This is refreshability as fine-grained scheduling rather than learning.

FreSh supplies a software analogue. Refresh is a generic transformation that turns a blocking, locality-aware index into a lock-free one by attaching done and helping flags to disjoint locality-preserving parts, running them first in expeditive mode and invoking lightweight help only after a thread finishes its own parts. The implementation operates over four non-overlapping traverse objects—buffer creation, tree population, pruning, and refinement—and achieves performance as good as the state-of-the-art blocking in-memory data series index while remaining robust to delays and failures (Fatourou et al., 2023). Here refresh means in-place completion of stalled work rather than physical recalibration. A plausible implication is that the central idea is not medium-specific; it can also be phrased as bounded, locality-aware recovery of unfinished state.

REFRESH FPGAs pushes the term into packaging and sustainability. The architecture proposes building new FPGA devices from recently retired FPGA dies assembled in a 2.5D system-in-package via an interposer, with “super duper long lines (SDLLs)” complementing the “super long lines (SLLs)” already used in multi-die FPGAs. Its sustainability analysis defines indifference and break-even times as

$I = |T [B(x; t); m(\theta)]|^2 + \epsilon,$2

and reports that, when comparing a single Versal VM1802 to a REFRESH device made from four ZCU102 dies, the higher embodied GHG of the new device can be offset within about one year in a California grid scenario, but two to three years under 90% renewables depending on workload case (Zhou et al., 2023). Refreshability here is modular lifetime extension: the device is refreshed by die reuse, chiplet replacement, or interposer-level redesign rather than by discarding the whole package.

TRON also belongs in this system-level category because it performs in-situ NAS over depth, width, skip connections, and pixel partition, often selecting skip connections rather than naive deep chains to compensate cumulative precision loss from repeated 1-bit re-encoding and hardware dynamic-range limits (Wang et al., 17 Apr 2026). Across these examples, refreshability includes runtime scheduling, modular serviceability, and architecture search.

6. Trade-offs, limitations, and open technical questions

The literature agrees that refreshability is not free. In photonic CNNs, thermo-optic phase shifters dominate static power at 10.3 W out of 14.7 W total static power, throughput is limited by serial patch streaming rather than optics, and detailed thermal settling or control-loop time constants are not reported (Ranjan et al., 2 Apr 2026). TRON is currently bounded by optoelectronic I/O, 1-bit DMD quantization, and deployment mismatch between simulation and hardware; improving modulators, sensors, and tunable scattering media is identified as necessary for faster refreshability and scalability (Wang et al., 17 Apr 2026). In memristive hardware, resistance variation is manageable but threshold variation is more damaging: Iris accuracy drops to 76.89% at 10% variation in $I = |T [B(x; t); m(\theta)]|^2 + \epsilon,$3 (Prajapati et al., 28 Jul 2025).

In in-memory continual learning, the reported few-shot regime keeps dynamic range small enough for progressive crystallization, but larger $I = |T [B(x; t); m(\theta)]|^2 + \epsilon,$4 would approach saturation and motivate smaller $I = |T [B(x; t); m(\theta)]|^2 + \epsilon,$5, RESET-and-reaccumulate, or redundant columns (Karunaratne et al., 2022). In DRAM, refresh reordering is constrained by JEDEC timing bounds and by the fact that per-bank refreshes cannot overlap arbitrarily across a rank (Chang et al., 2017). In REFRESH FPGAs, limited SLL/SDLL bandwidth, die aging, known-good-die requirements, and heterogeneous multi-die CAD remain open challenges (Zhou et al., 2023).

For live analysis systems, “in-situ” likewise does not mean zero interference. ISAAC time-shares the accelerator with the simulation, and only CPU-side compression and send are overlapped (Matthes et al., 2016). Galaxy’s coupling depends on the supercomputer’s internal interconnect and on the cost of repartitioning to the renderer’s regular spatial decomposition (Abram et al., 2021). libyt requires collective participation in RMA-based data stages, does not support interrupt or restart in the libyt kernel, and can incur large transient memory use for operations such as print_stats (Tsai et al., 11 Dec 2025). The tactile-display architecture depends on an external touch sensor because the Dot Pad lacks an integrated touch layer, and current chart support covers line, bar, scatter, and thematic maps with a subset of Vega-Lite transforms (Reinders et al., 17 Feb 2026).

A further misconception is that refreshability always implies complete autonomy. Several systems remain hybrid. The photonic CNN still requires modulators or lasers for input streaming and photodetectors for final readout; TRON uses optical forward and digital backward; ISAAC relies on a head/login-node server; libyt embeds Python in MPI ranks; and the tactile system uses cloud STT/TTS and LLM services in the reference implementation (Ranjan et al., 2 Apr 2026, Wang et al., 17 Apr 2026, Matthes et al., 2016, Tsai et al., 11 Dec 2025, Reinders et al., 17 Feb 2026). The common thread is therefore not elimination of all external support, but preservation of the primary state and update loop on the deployed substrate.

Taken together, these works indicate that In-Situ Refreshable Architecture is less a single blueprint than a design principle. Its central commitment is to keep mutable state physically close to where computation, memory service, rendering, or interaction already occurs, and to expose mechanisms—algorithmic, circuit-level, or packaging-level—for repeated in-place correction, update, or reconfiguration under realistic hardware and workload constraints.