Hf/Zr-Based Gate Stacks in Advanced CMOS

Updated 3 January 2026

Hf/Zr-based gate stacks are ultrathin, high-permittivity oxide layers enabling enhanced ferroelectric switching and negative-capacitance effects in CMOS, memory, and neuromorphic devices.
They utilize precise atomic layer deposition and engineered capping/interfacial layers to optimize polarization, leakage current, and reliability under strict thermal budgets.
Practical device performance is achieved by compositional tuning, defect passivation, and interface control, ensuring scalable EOT, robust endurance, and multi-level memory window control.

Hafnium Zirconium (Hf/Zr)-Based Gate Stacks constitute a foundational class of ultrathin, high-permittivity, electrically switchable oxide layers integrated into advanced silicon logic, memory, and neuromorphic devices. Their unique functional attributes arise from the stabilization of ferroelectric and high-κ phases in solid solutions or superlattices of HfO₂ and ZrO₂, often combined with engineered interfaces and capping layers (e.g., Al₂O₃, SrTiO₃) to optimize polarization switching, leakage current, and reliability under stringent CMOS thermal budgets. State-of-the-art Hf₀.₅Zr₀.₅O₂-based stacks support scalable, two-terminal architectures, steep-slope negative-capacitance coupling, and multi-level memory window control, and deliver threshold-voltage programmability via embedded dipoles and defect engineering.

1. Gate Stack Architectures and Integration

The canonical Hf/Zr gate stack comprises sequential deposition of bottom electrode (TiN; 30 nm), a thin dielectric interlayer (Al₂O₃; 3 nm by ALD), a ferroelectric Hf₀.₅Zr₀.₅O₂ film (HZO; 10 nm by ALD), and a top electrode (W; 30 nm) (Deshpande et al., 2021). Layering, crystallinity, and interfacial chemistry are optimized for compatibility with back-end-of-line (BEOL) processing constraints—specifically, maximum anneal temperature of 400°C. Atomic layer deposition enables precise control over thickness, stoichiometry, and interface abruptness for all constituents. Variants include MIFIS FeFETs (metal–insulator–ferroelectric–insulator–semiconductor) incorporating additional Al₂O₃ layers (0.85–13 nm) for memory window tuning (Hu et al., 2024), and HfO₂/ZrO₂/Al₂O₃ superlattices or dipole-embedded stacks supporting sub-nanometer equivalent oxide thickness (EOT) scaling (Song et al., 27 Dec 2025). In high-frequency GaN MIS-HEMTs, 2 nm HZO by PEALD realizes EOT ≈ 0.5 nm and breakdown field > 20 MV/cm (Cui et al., 2021).

Stack Type	Layer Sequence	Typical Thicknesses (nm)
BEOL-compatible FTJ	W / HZO / Al₂O₃ / TiN / p⁺⁺Si	30 / 10 / 3 / 30 / Sub.
MIFIS FeFET	TiN / Al₂O₃ / HZO / SiOₓ / Si	10 / (0.85–13) / 9.5 / 0.7 / Sub.
Superlattice (HZH/HZHA)	HfO₂ / ZrO₂ / HfO₂ (+Al₂O₃ dipole)	4–13 / 7–13 / 3 / Sub.

Additive, low-temperature process flows ensure direct integration atop completed logic metallization. Electrode materials (W, TiN) match established contact and interconnect layers. The scalability and CMOS compatibility are validated by interfacial phase control and sub-nanometer EOT after high-temperature RTA (Song et al., 27 Dec 2025).

2. Phase Stabilization and Ferroelectric Switching

Ferroelectricity in Hf/Zr-based oxides arises from metastable orthorhombic Pca2₁ phase formation, distinctly stabilized by nanometric film thickness, dopant composition, capping-induced stress, and rapid post-deposition anneal (Deshpande et al., 2021, Gent et al., 7 Jul 2025). The critical Hf:Zr stoichiometry window (x ≈ 0.4–0.6) maximizes orthorhombic-phase stability and hence remanent polarization (P_r). VCNEB calculations reveal a “through-plane” switching mechanism (S:T path) where three-fold coordinated O atoms cross metal planes at a lower energy barrier (ΔE_T ≈ 464 meV/f.u. for HZO) compared to conventional (S:N) paths, yielding a spontaneous polarization P₀ ≈ 70 μC/cm² (50% higher than prior estimates) (Wu et al., 2023).

Superlattice engineering—alternating Hf₁₋ₓZrₓO₂ and strained ZrO₂ sublayers—generates record P_r values (up to 42 μC/cm² for x=0.75–0.88) and multiplies endurance by leveraging interfacial oxygen management (Gent et al., 7 Jul 2025). The integration of capping layers (SrTiO₃, Al₂O₃, etc.) physically seals grain boundaries and chemically supplies oxygen, thereby suppressing localized conduction channels and stabilizing non-centrosymmetric o-HZO domains (Sulzbach et al., 2020).

3. Electrical Properties and Memory Window Control

Hf/Zr-based stacks exhibit bistable and multi-level resistive states via polarization-modulated tunneling (FTJ), large and tunable FeFET memory windows, and low-voltage operation. For BEOL-compatible W–HZO–Al₂O₃–TiN FTJs, after wake-up cycles, 2P_r ≈ 8 μC/cm², coercive field E_c ≈ 3–4.5 MV/cm, and tunneling electroresistance ratio TER ≈ 3–3.5 at read voltages (2–2.5 V) are typical (Deshpande et al., 2021). In MIFIS FeFETs with Al₂O₃ interlayers, ΔV_t increases linearly with t_Al₂O₃ up to ≈5.5 nm (max ~8.4 V), directly linked to persistent interface-trapped charge densities Q_it′ ≈ 18 μC/cm² (Hu et al., 2024, Hu et al., 2023).

The field distribution and capacitance-voltage hysteresis can be analytically described by series-capacitance and charge-neutrality models, with the full window accessible only when ferroelectric switching is supported by leakage-assist at ultrathin dielectric layers (Si et al., 2018). Thicker dielectric suppresses switching, limiting both P_r and window width.

Parameter	FTJ (BEOL)	FeFET (MIFIS, t_Al₂O₃=5 nm)
2P_r	8 μC/cm²	~20 μC/cm²
E_c	3–4.5 MV/cm	1.5 MV/cm
TER (ON/OFF)	~3–3.5	—
ΔV_t (memory window)	—	8.4 V
Interface trap density Q_it'	—	~18 μC/cm²

Endurance and retention are typically high, but excessively thick interlayers or superlattice periods can degrade reliability due to increased dielectric stress or internal field-induced gap narrowing (Hu et al., 2024, Huang et al., 2023).

4. Band Alignment, Defect Chemistry, and Leakage Control

Type-I (straddling) band alignment is achieved in epitaxial metal–Hf₀.₅Zr₀.₅O₂(130)–SiO₂–Si gate stacks, supporting high structural stability and absence of gap states under proper interface bonding (Chai et al., 2022). Oxygen vacancies are the lowest-energy point defects and dominate charge-trapping/de-trapping, directly implicating them in FeFET threshold-voltage drift and endurance fatigue. Their charge transition levels lie close to the Si band edges, rendering bias-induced electron/hole capture feasible. Passivation strategies include oxygen-rich ALD conditions, post-deposition anneals, and dopant engineering (e.g., La or Al incorporation).

The HZO band gap, E_g, decreases rapidly for low Zr substitution (x < 0.25; exponential regime), then linearly for x = 0.5–1.0, with E_g[x=0.5] ≈ 5.86 eV (Huang et al., 2023). Superlattice engineering can further narrow the gap below ZrO₂ values under large interface field or polar periods, although non-polar stacking suppresses this (Huang et al., 2023, Song et al., 27 Dec 2025).

5. Reliability, Endurance, and Scaling Guidelines

Endurance is controlled by managing oxygen vacancy migration, phase purity, dielectric breakdown strength, and interfacial trap density. ZrO₂-rich superlattices (up to 87.5% ZrO₂) attain exceptional cycling (10⁹ cycles, P_r > 20 μC/cm²) by localizing vacancy accumulation at multiple heterointerfaces and inhibiting conductive filament development (Gent et al., 7 Jul 2025).

Flat-band/threshold voltage tuning is accomplished by embedding Al₂O₃ dipole layers in HfO₂/ZrO₂ superlattices, enabling >200 mV shifts while maintaining sub-nanometer EOT and comparative stability under –2 V/125°C negative-bias stress (Song et al., 27 Dec 2025). Memory window and endurance optimization necessitate precise control of interlayer thickness and defect passivation: t_Al₂O₃ ≈ 4–6 nm maximizes ΔV_t but must be limited to retain endurance above 10³ cycles (Hu et al., 2024).

Reliability Metric	Superlattice (HZHA, 700°C)	Single-layer HfO₂/Al₂O₃
ΔV_FB (NBTI, –2V, 125°C, 100s)	–87 mV	–97 mV
EOT	8.4 Å	9.0 Å
Endurance (@1 kHz, PUND)	10⁹ cycles	≲10⁶ cycles

6. Theoretical Modeling, Phase Diagrams, and Optimization

Landau-Ginzburg-Devonshire (LGD) modeling provides robust frameworks for predicting phase stability, polarization reversal, and size/screening dependencies in HfₓZr₁₋ₓO₂₋ᵧ (Eliseev et al., 2024, Morozovska et al., 2023). “Effective” LGD coefficients are strongly nonlinear in composition (x), thickness (h), and oxygen vacancy (y). Screening conditions (small Debye length, high-k electrodes) lower the critical thickness for ferroelectricity; h/λ > 50 is preferred. Orthorhombic ferroelectricity is maximized for x ≈ 0.5–0.6, h ≈ 8–12 nm, y ≈ 3–5%, with P_r ≈ 0.15–0.20 C/m² and E_c ≈ 1–1.5 MV/cm (Eliseev et al., 2024). LGD phase diagrams delineate regions favoring FE or AFE behavior based on x and h.

Vertical compositional gradients (heterogeneous Zr/Al codoping) afford further enhancement: Zr sublayers at top/bottom leverage capping-stress stabilization, while Al-rich interfacial layers buffer built-in fields and trap sites, tuning phase fractions and fatigue (Yang et al., 22 Aug 2025).

7. Practical Guidelines and Emerging Directions

Composition: Target HZO (x ≈ 0.4–0.6) for CMOS, superlattice configurations (x ≥ 0.75) for maximal polarization/endurance.
Interlayer/Capping Design: Optimize Al₂O₃ (2–6 nm) or STO capping for trap-management; thicker layers tradeoff window width for reliability.
Phase Engineered Superlattices: Employ symmetric bilayers, multiple repetitions, and ≤5 nm sublayer thickness for strain-stabilized r-phase and interface-mediated breakdown prevention.
Defect and Dopant Control: Reduce interfacial oxygen vacancies by ALD, anneal, or passivation; avoid direct SiON/HZO contacts to suppress leakage.
Process and Thermal Budget: ALD at 250°C for oxides; BEOL-compatible annealing at 400°C for o-HZO formation; RMG flows with 700°C anneal for high-performance scaling.
Modeling: LGD coefficient maps and phase boundaries for process optimization, device simulation, and predicted performance.

Collectively, Hf/Zr-based gate stacks—engineered across composition, structure, interface, and dopant profiles—enable sub-nanometer EOT scaling, high-voltage stability, tunable threshold operation, and robust endurance, substantiating their central role in advanced logic, memory, and future Si-compatible nonvolatile architectures (Deshpande et al., 2021, Gent et al., 7 Jul 2025, Song et al., 27 Dec 2025, Wu et al., 2023, Hu et al., 2024, Si et al., 2018, Chai et al., 2022, Huang et al., 2023, Sulzbach et al., 2020, Eliseev et al., 2024).