10-nm Structured Silicon: Advances & Applications

• 10-nm structured silicon is a nanomaterial engineered below 10 nm, exhibiting quantum confinement and distinctive electronic and optical properties.
• Advanced fabrication techniques such as silicene nanomeshes, solid-state dewetting, and lithographic nanostructuring enable high precision and scalability.
• These architectures drive breakthroughs in MOSFETs, energy storage, and photonic devices while addressing challenges like defect control and thermal stability.

10-nm structured silicon refers to silicon-based materials and devices in which critical geometrical features—such as wire diameters, pore or grain sizes, nanocrystal dimensions, or lithographic line widths—are precisely engineered at or below the 10 nm scale. This dimensional constraint induces pronounced quantum, interfacial, and size-dependent effects, directly influencing electronic structure, transport, mechanical behavior, and optical response. Recent decades have seen the emergence of diverse methodologies to realize 10-nm structured silicon architectures for logic, optoelectronics, storage, and energy applications, spanning from bottom-up nanofabrication to subwavelength lithography and guided self-assembly.

1. Structural Engineering Methods for 10-nm-Scale Silicon

10-nm structured silicon is attainable via several advanced fabrication protocols, each offering distinct advantages in control and scalability.

• Silicene Nanomeshes (SNMs): Created by etching periodic triangular arrays of hexagonal holes in a monolayer silicene sheet (lattice constant ≃ 3.87 Å, buckling Δ ≈ 0.46 Å). Each nanomesh is notated [R, W], where R defines the number of Si atoms removed per hole (N_removed ≃ 6R), and W specifies the silicon wall width between holes, in atomic chains. For instance, a [1,4] SNM removes 6 Si atoms, leaving walls 4 Si atoms thick (Pan et al., 2015).
• Solid-State Dewetting/Nucleation in Thin Oxides: By RF sputtering silicon-rich oxide (SRO, 10 nm thick, Si content 28–70 area %) on rapid-thermal oxidized (RTO) SiO₂ spacers (3 nm), followed by high-temperature annealing (1000–1100 °C, 30–60 min), nanoscale phase separation results in buried bands of Si nanoclusters (4–10 nm diameter) within SiO₂ (Thøgersen et al., 2012).
• Plasma Synthesis and Assembly for Sub-10 nm Particles: Low-temperature non-thermal plasma (RF, 100 W, SiH₄/Ar) yields electrostatically stabilized Si nanoparticles (~5.8 ± 1.1 nm). Subsequent controlled evaporation and capillary assembly produce micron-scale superstructures, which can be infilled with graphitic carbon via CVD (C₂H₂), forming dense, stable anode materials (Ghildiyal et al., 21 Apr 2025).
• Lithographic Nanostructuring: Silicon nanogratings with 10 nm line width and 20 nm periodicity are achievable by extreme-ultraviolet/e-beam lithography, block-copolymer pattern transfer, atomic-layer etching, and spacer-defined sidewall methods, supporting wafer-scale fabrication (Toudert et al., 6 Nov 2025).
• In situ Solid-State Dewetting of a-SOI: Ultra-thin amorphous silicon-on-insulator (a-SOI) layers (1–2 nm thick, grown by solid-source MBE) undergo dewetting at 730 °C to yield mono-disperse, defect-free Si nanocrystals (7–14 nm diameter) embedded in SiO₂ (Aouassa et al., 2023).

The resulting morphologies—nanowires, dots, pores, gratings, and superstructures—are distinguished by high monodispersity, interface abruptness, and, where explicitly demonstrated, crystalline order at the sub-10 nm scale.

2. Quantum and Electronic Effects in 10-nm Structured Silicon

At the 10-nm scale, quantum confinement and surface/interface phenomena dominate electronic structure and transport:

• Bandgap Engineering in Nanomeshes: In SNMs, the bandgap ($E_g$) scales linearly with the atom-removal fraction ($f = N_{\rm removed}/N_{\rm total}$): $E_g \approx g\,f$, $g \approx 7.246~{\rm eV}$. Only SNMs with even W exhibit gap opening, driven by Brillouin zone folding and intervalley mixing; odd W networks remain semimetallic. Maximum computed $E_g$ reaches 0.68 eV at $W=2$ (for $R=1$ or $2$) and falls below 0.1 eV for $W \gg 10$ (Pan et al., 2015).
• Interface and Defect States: In buried nanocrystal systems, stacking faults and {111}-twin boundaries on the 4–10 nm scale introduce local states capable of trapping charge carriers or creating recombination centers, potentially broadening memory-device Coulomb blockade peaks and degrading carrier mobility (Thøgersen et al., 2012). Monocrystalline, defect-free nanocrystals (∼7 nm) have been reported in solid-state dewetted a-SOI, as confirmed by FFT-HRTEM (Aouassa et al., 2023).
• Quantum Well and Confinement-Enhanced Device Control: Embedding p⁺ silicon tubs (5 nm wide/deep, $N_A\approx2\times10^{20}$ cm⁻³) beneath source/drain in 10 nm FDSOI MOSFETs creates potential wells of depth 0.4–0.6 V, sharply suppressing OFF-state leakage and short-channel effects. Drive and leakage currents scale as $I_{\rm ON}\approx91.6$ μA/μm and $I_{\rm OFF}\approx0.12$ pA/μm, yielding $I_{\rm ON}/I_{\rm OFF}\approx7.6\times10^{5}$ and subthreshold swing $SS\approx87$ mV/dec at $L_g=10$ nm (Mehrotra et al., 2020).
• Phonon Confinement: Sub-10 nm SiNWs show anomalous Raman characteristics under pressure ($\le$ 15 GPa), including 2TO mode splitting at $P\geq5$ GPa—indicative of anisotropic, mode-dependent stiffening and increased linear modulus. For confined W-point phonons, the pressure coefficient collapses by $\sim\times10$ at high $P$ (effective modulus $\sim$1.1 TPa), while L-point and 1TO modes remain bulk-like (Bhattacharyya et al., 2010).

3. Electrochemical, Photonic, and Storage Applications

10-nm structured silicon enables advances in several device domains:

Application	Structure	Key Attributes
Logic (MOSFETs)	SOI with 5–10 nm tubs/channels	High $I_{\rm ON}/I_{\rm OFF}$, suppressed DIBL, planar
Lithium-ion batteries	<10 nm Si grains + pores	High tap density ($>$1.2 g/cm³), 80% retention @400 c.
Non-volatile storage	Si nanocrystals (4–10 nm)	Embedded in SiO₂, quantum memory, Coulomb blockade
UV-Optical memory	10 nm Si nanogratings	>600% contrast at 120 nm, 10–100× density vs Blu-ray
Photodetectors/solar cells	Si NCs (7–14 nm, high-ρ layer)	>10× current enhancement, R$_{\rm peak}$ $>$3 A/W

• Li-ion Anodes: Plasma-fabricated, sub-10 nm porous Si–C architectures deliver tap densities $\approx$1.22 g/cm³, initial CE 67–78% (full), stabilizing at $>$99.5%. Capacity retention is $\sim$80% after 400 cycles; gravimetric and volumetric capacities exceed commercial graphite by factors of 4× and 3×, respectively. The <10 nm dimension falls below the fracture threshold, suppressing anode pulverization during (de)lithiation and limiting SEI growth to outer ~40–50 nm shells (Ghildiyal et al., 21 Apr 2025).
• Phase-Change Optical Data Storage: Gratings with 10 nm Si lines/20 nm pitch yield strong VUV-plasmonic resonances ($\lambda_0 \approx 120$ nm), with up to 600% optical transmittance contrast between crystalline and amorphous phases due to epsilon-near-zero (ENZ) and surface-plasmon modes. Bit area shrinks from $(150\,{\rm nm})^2$ (Blu-ray) to $(20\,{\rm nm})^2$, promising >10–100× areal density increases. Fabrication leverages advanced lithographic and self-assembly processes (Toudert et al., 6 Nov 2025).
• CMOS-Compatible Optoelectronics: In ultra-dense MIS stacks, ∼7–14 nm monocrystalline Si nanocrystals grown via MBE/dewetting (density $10^{11}$–$10^{12}$ cm⁻²) enhance photoresponse: at $V=−1$ V, $I_{\rm ph}$(NC) $\approx$ 10×$I_{\rm ph}$ (Ref), $R_{\rm max}$ $\approx$ 3.2 A/W at 698 nm. Room-temperature I–V shows 2–3 decades higher conduction in accumulation (dark) due to percolation/tunneling through the NC layer (Aouassa et al., 2023).

4. Defect Control, Stability, and Device Reliability

Stochastic and process-driven defects present a principal engineering obstacle in 10-nm structured silicon:

• Nanocrystal Arrays: Stacking faults and multiple twins ({111} planes, 70.53° between twin facets) arise in 4–10 nm clusters for Si supersaturation $>$50 area % during SRO anneals. These extrinsic faults (schematically: …ABCBA CBA…) act as electronic traps and recombination centers, broadening quantum memory features and degrading device retention (Thøgersen et al., 2012).
• Defect-Free Growth: Si NCs formed via controlled dewetting of ultra-thin a-SOI at 730 °C/30 min and immediate a-Si caps followed by 800 °C/5 min anneals yield monodisperse, defect-free, crystalline cores (verified by HRTEM with diamond-cubic signature) (Aouassa et al., 2023).
• Phonon and Charge-Transport Stability: In Li-ion anodes, sub-10 nm pores constrain SEI formation; the SEI layer forms only at the exterior, blocking internal pores and mitigating continuous electrolyte decomposition. For sub-10 nm SNM FETs, I$_{\rm on}$/I$_{\rm off}$ degrades from $\sim10^3$ (0 K) to $\sim$40–100 (room T) due to increased phonon scattering, emphasizing substrate and encapsulation requirements (Pan et al., 2015).
• Mechanical Rigidity Under Stress: Sub-10 nm SiNWs, when subjected to pressures $\gtrsim$6 GPa, reorganize into rigid bundles suppressing anharmonicity and enhancing modulus (W-mode $B_{\rm eff}\approx1.1$ TPa), persisting up to 15 GPa without amorphization—contrasting with porous Si ($<$10 nm), which amorphizes near 10 GPa (Bhattacharyya et al., 2010).

5. Device Simulation, Characterization, and Modeling

Rigorous simulation and characterization protocols underpin 10-nm structured silicon research:

• First-Principles and Quantum Transport: DFT-GGA–PBE (DMol$^3$), DNP basis, 16%%%%47$P\geq5$48%%%%1 Monkhorst–Pack mesh, with NVT-MD (1 fs timestep, 1000 K) for SNM stability. Ballistic transport modeled with NEGF (ATK 11.2), extended Hückel or DFT-SZ, and room-T phonon effects included via MD-based elastic disorder (Pan et al., 2015).
• Device Physics and TCAD: 10 nm PWFDSOI MOSFETs modeled using drift-diffusion with quantum-confinement corrections (density-gradient), Fermi–Dirac statistics, Lombardi mobility, and self-heating; Poisson’s equation solved for variable tub/body doping and oxide stacks. Device benchmarking compares DIBL, $SS$, and leakage against reference ground-plane FDSOI and FinFETs (Mehrotra et al., 2020).
• Microstructural and Spectroscopic Analysis: TEM, EFTEM (Si plasmon loss at 16.8 eV), and HRTEM (0.314 nm {111} fringes) distinguish amorphous/crystalline clusters; MacTempas simulations (300 keV, Cs=0.6 mm) facilitate defect analysis (Thøgersen et al., 2012). Raman spectroscopy under pressure tracks phonon mode splitting, pressure coefficients, and line-widths to infer modulus and phase transitions (Bhattacharyya et al., 2010).
• Optical Simulation: FDTD field maps and Bruggeman effective-medium approximations elucidate UV/VUV plasmon modes and resonance conditions for a-Si/c-Si nanogratings (Toudert et al., 6 Nov 2025).

6. Prospects, Integration, and Technological Implications

10-nm structured silicon architectures provide a foundation for next-generation silicon technology, while entailing distinct fabrication and integration challenges:

• Scalability: Planar PWFDSOI retains compatibility with SOI processing (single planar lithography); sub-10 nm SNMs and nanogratings can leverage existing e-beam/EUV, block copolymer, and atomic layer etching protocols for scaling.
• Integration: All-Si photodetector stacks and storage arrays can be integrated monolithically above CMOS with standard materials (Si, SiO₂, a-Si), avoiding contamination or catalyst-related yield loss (Aouassa et al., 2023, Toudert et al., 6 Nov 2025).
• Thermal Budgets: Most processes (e.g., a-SOI dewetting at 730–800 °C) are compatible with FEOL/BEOL integration windows on SOI substrates.
• Device Limitations: For ultra-scaled FETs and SNMs, V$_{\rm DD}$ scaling and phonon scattering remain critical constraints; in nanocrystal-based devices, defect engineering and passivation directly impact long-term stability and retention (Pan et al., 2015, Thøgersen et al., 2012).
• Future Directions: Potential enhancements include dual- or surround-gate FET architectures, new encapsulation approaches for SNM/sub-10 nm arrays, and air-stable VUV-optical components for data storage. Exploring alternative dielectrics/substrates and exploiting 3D nanostructuring are plausible strategies for further performance gains.

7. Summary Table: Physical Metrics Across Key 10-nm Structured Silicon Systems

System/Property	Structural Feature	Relevant Metrics
Silicene nanomesh (SNM)	Even-W hex mesh	$E_g$ up to 0.68 eV ($W=2$), $I_{\rm on}/I_{\rm off} \sim 10^3$ ($0$ K) (Pan et al., 2015)
Buried nanocrystals in SiO₂	4–10 nm clusters, SiO₂	6–7 nm avg. diameter, twin and stacking faults freq. observed (Thøgersen et al., 2012)
FDSOI PWFDSOI MOSFET	5 nm tubs, $L_g=10$ nm	$I_{\rm on}/I_{\rm off}=7.6\times10^5$, $SS=87$ mV/dec, DIBL $\downarrow 50\%$ (Mehrotra et al., 2020)
Li-ion anode x-Si-AC	$<$10 nm grains/pores	Tap $\rho=1.22$ g/cm³, 80% capacity after 400 cycles (Ghildiyal et al., 21 Apr 2025)
Nanogratings for VUV storage	10 nm line, 20 nm pitch	$>600\%$ optical contrast @ 120 nm, $>60\times$ area density (Toudert et al., 6 Nov 2025)
a-SOI dewetted NCs	Monodisp. 7–14 nm NCs	$>10\times$ Photo-I at -1 V, $R_{\rm max} \approx 3.2$ A/W (Aouassa et al., 2023)

10-nm structured silicon represents a versatile materials platform incorporating quantum confinement, advanced interface control, and unique mechanical, electronic, and optical properties. Its deployment spans advanced nanoscale logic, high-density energy storage, next-generation optical data storage, and high-sensitivity optoelectronics, with the interplay of size, defect engineering, and integration strategies remaining central to future development.