Ferroelectric Josephson Junctions

• Ferroelectric Josephson junctions are hybrid quantum devices that combine superconductivity with ferroelectric barriers to electrically modulate the supercurrent.
• Device architectures include vertical trilayer SIS and S–I–FE–I–S stacks with engineered asymmetry for enhanced control, achieving up to 90% switching efficiency.
• These junctions underpin applications in cryogenic non-volatile memory and reconfigurable superconducting logic, while requiring precise control over strain and interface quality.

Ferroelectric Josephson junctions are hybrid quantum devices combining superconducting electrodes with barriers that possess switchable electric polarization. Their integration of ferroelectric and superconducting functionalities enables electrical modulation of the Josephson supercurrent, with applications in programmable superconducting electronics, cryogenic logic, and non-volatile memory. Device architectures span conventional superconductor-barrier-superconductor (S–I–S) configurations employing ultra-thin ferroelectric layers, to composite S–I–FE–I–S stacks where critical current is controlled by polarization reversal and structural asymmetry. Key characteristics include high-temperature operation, energy gaps exceeding those in low-Tc materials, and quantum interference phenomena sensitive to nanoscale inhomogeneity.

1. Device Architecture and Fabrication Methodologies

Ferroelectric Josephson junctions are physically realized as vertical trilayers or composite tunnel structures. Examples include (Navarro et al., 2020):

• Vertical Trilayer SIS Structure:
  • Electrodes: epitaxial GdBa₂Cu₃O₇–δ (GBCO), 16 nm thick (top and bottom).
  • Barrier: BaTiO₃ (BTO), thickness variable (1–4 nm; Josephson coupling observed up to dBTO = 2 nm).
  • Substrate: (100) SrTiO₃; 2 nm SrTiO₃ buffer reduces 3D defects.
  • Patterning: optical lithography, Ar ion milling, SiO₂ insulation (∼100 nm), Ag cap and tracks for four-point measurement. Final active area typically 20 µm × 20 µm.
• Composite S–I–FE–I–S Structure (Tang et al., 11 Nov 2025):
  • Layers: S (superconductor) | I₁ (dielectric, thickness l₁) | FE (ferroelectric, thickness d, polarization P) | I₂ (dielectric, thickness l₂) | S.
  • Asymmetry: Device may vary l₁, l₂, or their barrier heights to break inversion symmetry, critical for polarization control of I_c.

All thin films are deposited by sputtering (DC for GBCO, RF for BTO/SiO₂) and subjected to controlled thermal profiles for optimized epitaxy and oxygenation.

2. Ferroelectric Barrier Properties and Limitations

Ferroelectric barriers enable switchable tunneling profiles through their spontaneous polarization. Detailed studies show (Navarro et al., 2020):

• BaTiO₃ Barriers:
  • Bulk T_Curie ≈ 390 K; ferroelectricity quenched when dBTO < 2 nm.
  • XRD (Θ–2Θ): observable (002) BTO peaks for dBTO ≥ 2 nm; pronounced in-plane compressive strain (a⊥ ≈ 0.420 nm for 2 nm, 0.414 nm for 3 nm).
  • AFM: RMS roughness ∼0.7 nm (GBCO), rougher with BTO; presence of 3D defects/pinholes traced to electrode morphology.
  • I–V: No detectable ferroelectric hysteresis below 2 nm; barrier acts as conventional insulator with some high-bias oxygen vacancy migration.
• Polarization Control in S–I–FE–I–S: (Tang et al., 11 Nov 2025)
  • Ferroelectric polarization P introduces an electrostatic offset Δ_p, calculated from Thomas–Fermi screening:

  $$Δ_p = \frac{d/ε_f}{d/ε_f+2\delta}\frac{\delta}{ε_0}P$$ - Reversal of P yields two distinct barrier profiles (U₁, U₂), modulating the critical current.

Ferroelectricity is highly thickness-dependent; ultra-thin barriers lose polarization, limiting active devices to those thicker than ∼2 nm.

3. Electrical Transport and Josephson Coupling Phenomena

Transport in ferroelectric Josephson junctions manifests as zero-voltage supercurrent, hysteresis, and tunable critical currents:

• SIS Devices with BTO Barriers (Navarro et al., 2020):

  • Clear Josephson supercurrent and underdamped I–V at T ≤ 77 K (dBTO = 1 nm) and T ≤ 41 K (dBTO = 2 nm); absent for dBTO ≥ 3 nm.
  • Representative metrics:
  • | dBTO (nm) | Ic (4 K) | Rn | IcRn (mV) | TJ (K) |
  • |-----------|----------|----|-----------|--------|
  • | 1 | 0.5 mA | 0.5 Ω | 0.25 | 77 |
  • | 2 | 7.5 mA | 115 Ω | 0.86 | 41 |
  • Ic(T) follows Ambegaokar–Baratoff:

  $$IcRn(T)=\frac{\pi\Delta(T)}{2e}\tanh\left(\frac{\Delta(T)}{2k_BT}\right)$$ - Josephson energy at 12 K: EJ ≈ 1.5 mV (1 nm) to 7.5 mV (2 nm), exceeding low-Tc conventional junctions.

• Polarization-Modulated Critical Current (Tang et al., 11 Nov 2025):

  • Full WKB–Landauer transmission model:

  $$J_c(P) \approx \frac{e\Delta_0}{4h}\kappa(1+\theta P)$$ - Modulation efficiency:

  $\eta(P) \simeq |\theta P|$ - Realistic architectures achieve η ≈ 0.9 (90% switching efficiency) for engineered asymmetry.

This enables non-volatile, electrically programmable supercurrent switches operable at cryogenic temperatures.

4. Quantum Interference: Fraunhofer Patterns and Structural Inhomogeneity

Magnetic interference patterns probe the uniformity and inhomogeneity of the tunneling barrier and electrodes:

• Fraunhofer Oscillations (Navarro et al., 2020):

  • Ic(H): ideal rectangular junctions obey the diffraction formula,

  $$I_c(H)=I_c(0)\left|\frac{\sin(\pi\Phi/\Phi_0)}{\pi\Phi/\Phi_0}\right|$$ - Junctions exhibit nonzero Ic "floor" at minima, attributed to thickness fluctuations in BTO and grain/step defects in GBCO. - Empirical fitting includes fluctuation parameter

  $$\gamma = \frac{\langle \delta I^2 \rangle^{1/2}}{I_1} \approx 0.13$$

  (temperature-independent).

These results highlight the necessity of atomic-scale interface optimization for reproducible device performance and minimal structural noise.

5. Effects of Strain and Epitaxy on Superconducting Properties

Increasing barrier thickness alters strain in underlying superconducting electrodes, impacting device metrics:

• Strain-Induced Tc Suppression (Navarro et al., 2020):
  • TJ (Josephson coupling temperature) diminishes rapidly with dBTO, attributed to stress-induced suppression of Tc in bottom GBCO layer.
  • XRD and AFM evidence confirm increased epitaxial strain for thicker barriers.
  • This suggests a critical trade-off between barrier ferroelectricity and electrode superconductivity; optimizing one parameter can adversely affect another.

A plausible implication is that future designs must balance ferroelectric thickness for polarization retention without exceeding strain tolerances of high-Tc electrodes.

6. Programmable Supercurrent Switching: Theoretical Framework and Optimization

Ferroelectric Josephson junctions in S–I–FE–I–S geometry enable electrically programmable supercurrent via inversion symmetry breaking and polarization reversal (Tang et al., 11 Nov 2025):

• WKB and Ambegaokar–Baratoff Analysis:
  • Engineering barrier asymmetry in thicknesses (l₁ ≠ l₂) or heights (U₁ᵇ ≠ U₂ᵇ) is essential for switching efficiency.
  • Linearized switching efficiency, for Δ_p ≪ Uᵇ:

  $$J_c(P) \simeq \frac{e\Delta_0}{4h}\kappa(1+\theta P)$$

  $\eta = |\theta P|$ - Optimal device configuration entails maximizing η (up to 0.9 observed), typically with thinner high-barrier sides and carefully chosen ferroelectric thickness/dielectric constant.

• Trade-Offs:

  • Higher switching efficiency necessitates lower absolute J_c due to exponential suppression with barrier asymmetry and FE thickness.
  • Device architectures must be tuned for application-specific requirements, balancing high η with practical J_c (e.g., for memory readout operations).

7. Applications in Cryogenic Memory, Logic, and Future Prospects

Ferroelectric Josephson junctions present compelling attributes for next-generation superconducting circuits (Tang et al., 11 Nov 2025):

• Cryogenic Non-Volatile Memory:
  • Logical bits encoded in ferroelectric polarization states, distinguished by their critical currents.
  • Electrical writing via voltage pulses; reading via current threshold measurement.
  • Performance: η up to 90%, write voltages ≲1 V, nanosecond-class switching, operation below superconducting Tc.
• Reconfigurable Logic and Integration:
  • S–I–FE–I–S stacks can be fabricated in crossbar arrays, compatible with SFQ logic circuits and potentially monolithic with digital superconducting electronics.
  • Materials such as HfₓZr₁₋ₓO₂ allow CMOS-compatible integration, unlocking prospects for high-density, ultra-low-power cryogenic memory and logic operating at tens of GHz.
• Outlook:
  • Interface optimization at the atomic scale is critical for scalability and reproducibility.
  • Future work will need to overcome trade-offs between polarization retention and strain-induced Tc suppression, leveraging two-dimensional or engineered ferroelectric platforms for enhanced device operation.

Overall, ferroelectric Josephson junctions—through advanced thin-film architecture, asymmetry engineering, and quantum transport manipulation—represent a foundational technology for electrically programmable superconducting electronics and quantum-functional devices (Navarro et al., 2020, Tang et al., 11 Nov 2025).