Atomically Thin In₂O₃ FETs: Advances in Scaling

• The paper demonstrates atomically thin In₂O₃ FETs with near-ideal subthreshold swings and drive currents exceeding 10 A/mm through precise ALD and thickness control.
• Methodologies include sub-nanometer channel engineering, advanced gate dielectrics (e.g., HZO), and unique contact designs that enable tunable threshold voltages and low contact resistance.
• Results highlight robust scalability for BEOL integration, excellent electrostatic control in sub-5 nm devices, and potential for monolithic 3D circuit applications.

Atomically thin In₂O₃ (indium oxide) field-effect transistors (FETs), including indium-tin-oxide (ITO) analogs, constitute a rapidly advancing domain within oxide semiconductor electronics. These ultra-scaled FETs, with channel thicknesses routinely between 0.4 nm and 5 nm, leverage high-mobility conduction bands, wide bandgaps, and low-temperature atomic-layer deposition (ALD) processing for integration, enabling applications in back-end-of-line (BEOL) compatible logic, monolithic 3D integration, and low-power electronics. Key features include near-ideal subthreshold slopes, record drive currents exceeding 10 A/mm, contact resistance approaching the best metallic contacts, and demonstrated control of device threshold by thickness and interface engineering.

1. Device Structure, Fabrication, and Materials

Atomically thin In₂O₃ and ITO FETs are fabricated using ALD or sputtering approaches, with sub-nanometer thickness control and conformality:

• Channel Materials:
  • Amorphous or polycrystalline In₂O₃ channels, with thickness scalable from monolayer (t ≈ 0.43–0.7 nm) to several nm (Si et al., 2020, Xu et al., 2023).
  • Indium-tin-oxide (ITO) channels, typically sputtered from 90 wt% In₂O₃ + 10 wt% SnO₂, with active regions etched to 1–2 nm (Si et al., 2020).
• Gate Dielectrics:
  • High-κ dielectrics such as HfO₂ or Hf₀.₅Zr₀.₅O₂ (HZO) are ALD-grown at 200–225 °C; in some cases, dual top and bottom HfO₂ layers are used for “epitaxy-like” template crystallization (Wang et al., 17 Oct 2025).
• Source/Drain Contacts:
  • Ni or Mo films, often with raised S/D structures (e.g., 10 nm ITO under Ni S/D), providing low contact resistance (R_c ≈ 0.15 Ω·mm, ρ_c ≈ 1.1 × 10⁻⁷ Ω·cm²) (Si et al., 2020).
• Thermal Budget and Integration:
  • All processes are compatible with BEOL limits (<300–350 °C), supporting monolithic 3D stacking.
• Architectures:
  • Gate-all-around (GAA) nanoribbon (Zhang et al., 2022), dual-gate (Wang et al., 17 Oct 2025), planar, and back-gated configurations have been demonstrated, with channel lengths (L_ch) scalable to sub-10 nm (Lin et al., 2022, Xu et al., 2023).

2. Electronic Transport, Quantum Confinement, and Interface Physics

• Charge-Neutrality-Level (CNL) and Trap Neutral Level (TNL) Models:
  • In bulk and thick films (t > 3 nm), the CNL/TNL lies ≈0.4 eV above E_C, pinning the Fermi level inside the conduction band. As t decreases, quantum confinement raises E_C; below a critical thickness (~1 nm), E_C crosses above the neutrality level, enabling enhancement-mode operation and shifting V_th positively (Si et al., 2020, Si et al., 2020).
• Mobility and Current Transport:
  • Field-effect and Hall mobilities (μ_FE, μ_H) range from ≈3 cm²/V·s (t=0.7 nm) up to >100 cm²/V·s in optimized crystalline films (e.g., 100.9 cm²/V·s at 4.2 nm channel, 300 K) (Wang et al., 17 Oct 2025, Si et al., 2020).
  • Low density-of-states (DOS) yields high carrier velocities (v_inj ≈ 1 × 10⁷ cm/s), enabling near-ballistic transport in ultra-short channels (Lin et al., 2022).
• Quantum Confinement:
  • The conduction band offset increases with decreasing thickness, ΔE(t) = π²ħ²/(2m*t²), with DFT calculations confirming upward E_C shift and bandgap widening (e.g., E_g ≈ 2.43 eV at t=0.7 nm) (Si et al., 2020).
• Contact Injection:
  • Metal-like CNL alignment results in negligible Schottky barriers and ultra-low R_c for both amorphous and polycrystalline channels (Lin et al., 2022).

3. Device Performance Metrics and Scaling Behaviors

The key figures of merit for atomically thin In₂O₃/ITO FETs are:

Channel	Thickness (nm)	L_ch (nm)	I_ON (max)	μ_FE/μ_H (RT)	SS (mV/dec)	V_th (V)
In₂O₃	0.7–1.5	200	>10⁷ μA/μm	3–65 cm²/V·s	90–200	+4.5 to –3.8
ITO	1–2	<1000	0.243–1.06 A/mm	6.1–27 cm²/V·s	70–90	2–5
In₂O₃	1.2	40	2.0 A/mm (@0.7 V)	39 cm²/V·s	88	~0
In₂O₃	3.1	40	19.3 mA/μm	(not given)	100–120	0–0.2
In₂O₃	2.5–3.5	7	10.2 A/mm	30–48 cm²/V·s	63–70	~0

Drain currents above 2 A/mm at low V_DS (<1 V) have been demonstrated for ALD In₂O₃ with T_ch = 1.2 nm (Si et al., 2020), while ~20 mA/μm is achieved in a 3.1 nm GAA nanoribbon at V_DS=1.7 V (Zhang et al., 2022). Maximum transconductance reaches 4 S/mm (Lin et al., 2022). Subthreshold swing (SS) is consistently measured between 63–120 mV/dec, with enhancement-mode operation tuned via channel thickness (Si et al., 2020, Si et al., 2020).

Amorphous films enable highly uniform characteristics over large areas, with field-effect and Hall mobility scaling with grain size for polycrystalline channels (~97 nm grains yield μ_H ≈100.9 cm²/V·s) (Wang et al., 17 Oct 2025).

4. Disorder, Localization, and the Breakdown of Ohm’s Law

In atomically thin In₂O₃ FETs, disorder and quantum interference cause deviation from classical linear scaling of conductance with channel length:

• Localization Model:
  • Conductance G(L,V_G) = G₀(V_G)·exp(-L/ξ(V_G)), where ξ is the localization length (Niu et al., 3 Jan 2026).
  • ξ increases exponentially with gate bias, ξ(V_G) = ξ₀·exp(a V_G), with ξ₀ tunable via thickness, annealing, and disorder reduction.
• Implications:
  • For t_ch ≲ 0.8 nm and without annealing, ξ ≪ L, leading to exponential suppression of conductance for L ≫ ξ rather than Ohmic 1/L scaling.
  • O₂ anneals and increased thickness (t_ch ≥ 2 nm) increase ξ, restoring near-Ohmic scaling for mesoscopic channels (L ≪ ξ at operational V_G, T).
• Optimization Strategies:
  • Favoring slightly thicker channels and post-deposition crystallization to mitigate disorder effects, thus enhancing device uniformity and reproducibility (Niu et al., 3 Jan 2026).

5. Electrostatics, Short-Channel Control, and Ferroelectric Gating

Atomically thin channel geometry enables aggressive scaling with robust electrostatic control:

• Electrostatic Body Factor:
  • λ ≃ √(ε_s·t_s·t_ox / ε_ox); for 1–2 nm bodies, λ ~ 2.4–3.3 nm (Si et al., 2020).
  • Channel thicknesses well below λ suppress drain-induced barrier lowering (DIBL), maintaining threshold voltage stability at sub-50 nm channel lengths (Si et al., 2020).
• Ferroelectric HZO Gating:
  • Introduction of Hf₀.₅Zr₀.₅O₂ as a gate dielectric (ε_r ≈ 25–30) allows ferroelectric polarization with 2P_r > 20 μC/cm², corresponding to sheet charge densities >1.2×10¹⁴ cm⁻² (Si et al., 2020).
  • Polarization-induced ΔV_th is modeled as ΔV_th ≃ P/C_ox, enabling non-volatile threshold control.
• Immunity to Short-Channel Effects:
  • Both experimental and atomistic simulation results (DFT-NEGF) confirm strong gate control: sub-5 nm channels with L_g down to 2 nm meet or exceed ITRS high-performance and low-power specifications, with SS approaching theoretical limits (66–77 mV/dec) (Xu et al., 2023).

6. Integration, Scalability, and Technological Impact

• BEOL and 3D Monolithic Integration:
  • The ALD process supports deposition on global interconnect wafers at ≤225–350 °C, essential for monolithic 3D IC stacking (Si et al., 2020, Xu et al., 2023).
• Scalability Limitations:
  • Atomically thin channel FETs demonstrate gate length scaling to 2–3 nm (criteria: L_g ≥ t_ch), with quantum tunneling and contact engineering as emerging limitations (Xu et al., 2023).
• Comparative Performance:
  • UT In₂O₃ FETs outperform monolayer MoS₂, MoTe₂, and other 2D semiconductors in energy–delay product at sub-5 nm nodes, with wide bandgap (E_g ≈ 3.15 eV) ensuring low leakage (Xu et al., 2023).
  • ITO/ALD In₂O₃ achieves lower contact resistance and higher on-state currents than 2D transition metal dichalcogenides and amorphous IGZO TFTs (Si et al., 2020, Si et al., 2020).
• Process and Device Challenges:
  • Remaining challenges include scalable contact engineering, variability at sub-5 nm, and reliability under high-field and self-heating conditions (Zhang et al., 2022, Lin et al., 2022, Xu et al., 2023).

7. Future Directions and Research Outlook

• Crystallinity Control:
  • Dielectric-templated crystallization techniques (“epitaxy-like” HfO₂/In₂O₃/HfO₂ stacks) further boost μ_H and device reliability, suggesting extension to other oxide channels (e.g., ZnO, IGZO) (Wang et al., 17 Oct 2025).
• Modeling and Simulation:
  • Atomistic DFT-NEGF simulations are used to inform scaling limits including quantum tunneling, electron–phonon scattering, and statistical variability at the sub-5 nm regime (Xu et al., 2023).
• Complementary Circuits and P-Type Oxides:
  • Exploration of p-type oxide FETs and truly complementary logic remain priorities for circuit-level BEOL integration (Xu et al., 2023).
• Application Domains:
  • Prospects extend to logic, memory drivers, sensor arrays, and RF/analog front-ends leveraging >10 A/mm current drive, sub-70 mV/dec switching, and reproducible atomic thickness control (Lin et al., 2022, Si et al., 2020).

Atomically thin In₂O₃ and ITO FETs, by leveraging low-temperature ALD synthesis, unique interface and electrostatic design, and intrinsic quantum-scale physics, have established new state-of-the-art benchmarks for drive current, scaling, and integration in oxide semiconductor electronics (Si et al., 2020, Si et al., 2020, Si et al., 2020, Lin et al., 2022, Xu et al., 2023, Wang et al., 17 Oct 2025, Niu et al., 3 Jan 2026, Zhang et al., 2022).