Helios Trapped-Ion Quantum Processor

• Helios is an advanced trapped-ion quantum processor that implements the QCCD architecture with all-to-all connectivity and high-fidelity operations across 98 qubits.
• It employs segmented ion traps with dynamic ion transport, enabling parallel execution of quantum gates and minimal motional decoherence.
• A comprehensive low-latency software stack orchestrates real-time routing and dynamic circuit scheduling, pushing the limits of digital quantum computation.

The Helios trapped-ion quantum processor is an advanced quantum computing platform implementing the quantum charge-coupled device (QCCD) architecture. Distinguished by its all-to-all connectivity, dynamic circuit capabilities, and high-fidelity operations across up to 98 qubits based on hyperfine $^{137}$Ba$^+$ ions, Helios integrates innovations in segmented ion trapping, modular cryogenic control, parallel operation regions, and a comprehensive low-latency software stack for quantum program execution. The system is further complemented by advanced benchmarking protocols demonstrating performance beyond the reach of classical simulation for random circuit tasks, and by extension, sets a new benchmark for complexity and fidelity in digital quantum computers (Ransford et al., 7 Nov 2025, Pino et al., 2020, Ringbauer et al., 2021).

1. System Architecture and Ion Transport

Helios employs a planar two-dimensional surface-electrode trap cooled to cryogenic temperatures. The architecture features:

• Ring memory: A storage ring capable of hosting up to 82 two-ion Ba–Yb crystals, serving as a high-capacity, rotatable, random-access quantum memory. The rotation is electrically actuated, supporting bidirectional ion transport.
• Leg buffers: Two leg storage regions attached to the ring via an X-junction, functioning as first-in, last-out stacks for routing and staging of ion crystals.
• Cache region: A local buffer region capable of storing up to 16 ions prior to transfer into logic zones.
• Logic region: Eight independent quantum operation zones arranged in two rows, providing state preparation, cooling, high-fidelity single- and two-qubit logic, mid-circuit reset and measurement (MCMR), and dynamic scheduling.
• X-junction hub: The central routing node enabling arbitrary reordering of ions, supporting crystal merging, splitting, direction reversal, and transfer between ring, cache, and logic zones, thus achieving true all-to-all topological connectivity.

Ion transport primitives (linear shuttling, splitting, crystal order swaps) are realized via quadratically optimized voltage waveforms, typically adding less than 1–2 motional quanta per operation. These processes enable dynamic circuit mapping, parallel execution, and quantum resource allocation with minimal motional decoherence (Ransford et al., 7 Nov 2025, Pino et al., 2020).

2. Qubit and Qudit Encoding

The primary qubit encoding leverages the hyperfine "clock" transition in the $^{137}$Ba$^+$ ground $S_{1/2}$ manifold: $$\ket{0}\equiv\ket{F=1, m_F=0},\quad \ket{1}\equiv\ket{F=2, m_F=0}$$ with a frequency split $\omega_0/2\pi\approx 8.04$ GHz and bias field $B\approx 3.95$ G. The system Hamiltonian incorporates hyperfine, Zeeman, and higher-order magnetic effects, such that the clock transition displays only second-order sensitivity to field fluctuations (488.8 Hz/G$^2$), supporting extended coherence.

Each Ba$^+$ qubit is paired with a $^+$0Yb$^+$1 coolant ion for in-situ sympathetic cooling using 369 nm beams, critical for low-motional heating under frequent shuttling and gate operations.

In the "Helios" qudit variant, $^+$2Ca$^+$3 ions are used, exploiting up to seven-level encodings from the $^+$4 and $^+$5 subspaces. Transitions are controlled via individually addressed 729 nm beams, with multilevel logic supported by selection rules $^+$6 (Ringbauer et al., 2021).

3. Quantum Gate Operations and Metrics

Coherent gates are executed using stimulated Raman transitions (515 nm for Ba$^+$7; 729 nm quadrupole for Ca$^+$8 qudits), with the following key native gates:

• Single-qubit rotation:

$^+$9

Implemented using co-propagating beams to minimize motional sensitivity. Virtual $^{137}$0 rotations are handled in software with zero physical time.

• Two-qubit entangling gate:

Mølmer–Sørensen $^{137}$1 gate

$^{137}$2

Achieves perfect entanglement ($^{137}$3) with $^{137}$470 μs durations, alternating operation and cooling across zones for parallelization.

For the Ca$^{137}$5 qudit architecture, arbitrary SU(2) rotations are synthesized via pairwise drives, and two-qudit entangling gates are implemented by bichromatic sideband excitation, supplemented with composite pulse schemes for error mitigation (Ringbauer et al., 2021).

Empirical average infidelities reported via randomized benchmarking and cycle benchmarking on Helios are: $^{137}$6 with corresponding leakage rates $^{137}$7 below $^{137}$8 per Clifford operation (Ransford et al., 7 Nov 2025).

4. State Preparation, Measurement, and Crosstalk Mitigation

State preparation in Helios leverages narrowband optical shelving (1762 nm) into the $^{137}$9 manifold along with 493/650 nm optical pumping. Measurement is performed by selective shelving of $^+$0 (or both basis states for ternary readout) and fluorescence detection on $^+$1 cycling transitions.

Helios implements:

• Protected measurement mode: Simultaneous shelving of all 16 qubits in a batch prevents photon crosstalk between qubits.
• Ternary measurement: Distinguishes between logical states and leakage events by shelving both $^+$2 and $^+$3 into separate sublevels.

Standard SPAM (state preparation and measurement) infidelities average $^+$4, with minimized crosstalk and support for mid-circuit measurement and reset required for dynamic and fault-tolerant protocols (Ransford et al., 7 Nov 2025, Pino et al., 2020).

5. Software Stack and Dynamic Circuit Execution

A real-time software stack orchestrates mapping, ion routing, gate parallelization, and control flow, supporting dynamic circuits wherein virtual qubits are allocated, de-allocated, measured, or reset on the fly. Key responsibilities of the stack include:

• Online allocation and physical mapping of user-level qubits
• Real-time routing and scheduling, exploiting ring and cache topology
• Dynamic grouping of gates into parallel “slices,” interleaved with cooling and transport
• Streaming of gates from external coprocessors (e.g., for randomized compiling), with latency below 1 ms

This infrastructure enables true conditional execution, early termination, and runtime-optimized routing without precomputed static schedules, pivotal for randomized compiling, error correction, and adaptive quantum algorithms (Ransford et al., 7 Nov 2025).

6. System-Level Benchmarks and Classical Intractability

Helios has been benchmarked on both random Clifford circuits with mid-circuit measurements (“QIRB”) and large-scale random circuit sampling (RCS) using mirror benchmarking. Salient findings include:

• Process fidelity per layer in QIRB: $^+$5 (no mid-circuit measurement), $^+$6, $^+$7 for 8 and 16 mid-circuit measurements per layer, indicating effective layer fidelities in agreement with component error metrics.
• Random circuit sampling: Performed on all $^+$8 qubits up to depth $^+$9. The circuit return probabilities $S_{1/2}$0 are well-modeled by estimated effective errors, and the resulting distribution lies outside the practical reach of current classical simulation methods, even on largest available supercomputers, due to exponential scaling in both $S_{1/2}$1 and circuit depth.

This places Helios beyond classical tractability for meaningful circuit sizes, establishing it as a leading digital quantum computer in terms of achievable complexity and fidelity (Ransford et al., 7 Nov 2025).

7. Scalability, Qudit Extensions, and Error Correction Prospects

The QCCD blueprint deployed in Helios provides straightforward extensibility by adding more storage or logic zones, or concatenating additional trap segments. Fast ion transport, modular cryogenic engineering, and parallel optical architecture support increases in both register size and gate-zone count.

The qudit extension of Helios, demonstrated with $S_{1/2}$2Ca$S_{1/2}$3, achieves local Hilbert space sizes up to $S_{1/2}$4 (restricted only by experiment rather than hardware), with gate and SPAM fidelities approaching qubit thresholds ($S_{1/2}$5 per pulse, two-qudit entangling fidelities $S_{1/2}$6). Generalized Clifford and non-Clifford gates have been demonstrated, and error-correcting codes for qudits (surface codes, color codes) are compatible, with higher thresholds and reduced overhead relative to qubits (Ringbauer et al., 2021).

Expected improvements in noise filtering, optimized transport, and faster cooling protocols could further suppress dominant error sources, enabling fault-tolerant operation at scale—a critical milestone for quantum computation targets including quantum error correction and classically intractable quantum simulation (Ransford et al., 7 Nov 2025, Pino et al., 2020).