Constant-gm Bias Circuit

• Constant-gm bias circuits are self-biased transconductance-reference networks that set bias current via resistor and device-geometry ratios.
• They stabilize the effective transconductance in dynamic Gm-C amplifiers, reducing gain sensitivity to temperature and supply variations.
• The design employs current mirrors, common-gate devices, and asymmetric differential pairs to enhance linearity and mitigate process variations and startup issues.

Searching arXiv for the specified paper and closely related constant-$g_m$ bias work to ground the article in current literature. A constant-$g_m$ bias circuit is a self-biased transconductance-reference network in which the small-signal transconductance of a reference MOS device is set primarily by a resistor and device-geometry ratios, and the resulting bias current is mirrored into the signal path so that the amplifier transconductance and gain become much less sensitive to temperature and power-supply variation. In the Gm-C dynamic amplifier reported in "Design of a Gm-C Dynamic Amplifier with High Linearity and High Temperature and Power Supply Voltage Stability" (Yang et al., 20 Aug 2025), the constant-$g_m$ bias is the mechanism that stabilizes the effective $G_m$ appearing in the dynamic-gain relation $A_v \approx \frac{G_m T}{C}$, while linearity is obtained separately from two mirrored asymmetric differential pairs.

1. Functional role in the dynamic amplifier

In the reported dynamic Gm-C amplifier, gain is fundamentally set by transconductance charging a capacitor during a finite amplification interval, with

$A_v \approx \frac{G_m T}{C}.$

Here $G_m$ is the effective transconductance of the input stage, $T$ is the amplification time, and $C$ is the integrating or load capacitor. Because $C$ can be made stable using MIM or MOM capacitors, and $g_m$0 can be derived from a clock or DLL, the dominant source of environmental gain drift is $g_m$1. The constant-$g_m$2 bias circuit is therefore used to make the transconductance of the amplifier input devices approximately independent of temperature and supply voltage (Yang et al., 20 Aug 2025).

This role is distinct from the linearization mechanism. The amplifier main part employs two asymmetric differential pairs to enhance transconductance linearity, maintains a nearly constant gain within a differential input range of $g_m$3 to $g_m$4, and achieves a total harmonic distortion of $g_m$5. The bias circuit does not create that linearity; rather, it stabilizes the absolute scale of the main-stage transconductance and therefore the gain.

2. Topology and device organization

The constant-$g_m$6 loop is centered on transistors M24 and M25 and resistor R1. The paper states that the transconductance of M24 is determined by an expression involving only $g_m$7, $g_m$8, and $g_m$9, identified as R1. The current through M24 and M25 is denoted $g_m$0, which indicates that these devices form the core self-biased constant-$g_m$1 cell.

That reference current is distributed through current mirrors with gain factor $g_m$2. The current through M24 and M25 is $g_m$3, while the current through M9 and M10 is $g_m$4. M9 and M10 are therefore the receiving devices in the main amplifier bias tree and provide the tail-current bias for the main differential pairs.

Mirror accuracy is reinforced by common-gate devices M7, M8, M18, M19, M22, M23, M26, and M27. Their role is to isolate the drain voltage of the mirror common-source devices from output-voltage swings, equalize input-branch and output-branch drain voltages, and improve current replication accuracy. In practical terms, this means that the reference current established by the constant-$g_m$5 cell is less disturbed by finite output resistance and $g_m$6 mismatch when it is delivered into the signal path.

The main-stage interface is asymmetric. The constant-$g_m$7-derived current mirrored to M9 and M10 produces the tail current for the differential pairs, and the paper states that if the width/length ratio of M1 is $g_m$8, then $g_m$9 of tail current flows into one transistor of the differential pair, where $G_m$0 depends on the width ratios in the differential pair. For M1,

$G_m$1

Several surrounding devices preserve the effectiveness of the bias in the amplifier core. M11, M12, M14, and M15 reset the amplifier and reduce residual charge between phases. M13 and M16 suppress the effect of $G_m$2 and $G_m$3 on the drain currents of M1-M4. M5 and M6 switch between amplification and reset phases. M7 and M8 additionally increase the tail current source output impedance, reducing common-mode dependence of tail current and thereby preserving transconductance.

The paper does not explicitly mention a startup circuit, does not identify startup transistors, and does not discuss elimination of the zero-current state. Since classical self-biased constant-$G_m$4 cells often require startup assistance, this omission is a significant undocumented aspect of the implementation.

3. Closed-loop transconductance setting

The quantity held approximately constant is the small-signal transconductance of M24. The paper gives the reference relation in the standard constant-$G_m$5 form, which can be written compactly as

$G_m$6

The explicit conclusion is that $G_m$7 depends only on $G_m$8, $G_m$9, and $A_v \approx \frac{G_m T}{C}$0, and is not influenced by temperature or power-supply voltage (Yang et al., 20 Aug 2025).

The operating idea is that M24 and M25, operating with a geometry ratio, develop a resistor drop across R1 that is linked to device overdrive. Because both devices are embedded in the same self-bias loop, the branch current adjusts until the resistor drop and transistor operating-point relation are simultaneously satisfied. The equilibrium current is therefore such that the resulting $A_v \approx \frac{G_m T}{C}$1 is set mainly by $A_v \approx \frac{G_m T}{C}$2 and the size ratio of M24 and M25.

The reference current is then mirrored into the main stage. With current-mirror gain factor $A_v \approx \frac{G_m T}{C}$3, M9 and M10 each receive $A_v \approx \frac{G_m T}{C}$4. Because the composite differential pair is asymmetric, a given input transistor receives only a fraction of that current: $A_v \approx \frac{G_m T}{C}$5 The paper gives the transconductance of M1 in a form derived from the constant-$A_v \approx \frac{G_m T}{C}$6 reference current and concludes that $A_v \approx \frac{G_m T}{C}$7 depends only on $A_v \approx \frac{G_m T}{C}$8, $A_v \approx \frac{G_m T}{C}$9, $A_v \approx \frac{G_m T}{C}.$0, $A_v \approx \frac{G_m T}{C}.$1, $A_v \approx \frac{G_m T}{C}.$2, and $A_v \approx \frac{G_m T}{C}.$3. It then states that the same is true for M2, M3, and M4. This is the basis on which the main transconductor inherits the reference-cell stability.

The derivation implicitly relies on the strong-inversion square-law model,

$A_v \approx \frac{G_m T}{C}.$4

Under ordinary fixed-current biasing, $A_v \approx \frac{G_m T}{C}.$5 varies strongly with mobility, threshold voltage, bias current, and supply headroom. In the constant-$A_v \approx \frac{G_m T}{C}.$6 loop, $A_v \approx \frac{G_m T}{C}.$7 self-adjusts with device characteristics and resistor drop so that the resulting $A_v \approx \frac{G_m T}{C}.$8 remains approximately constant.

4. Mechanisms of supply-voltage and temperature stability

Supply-voltage insensitivity arises first from the constant-$A_v \approx \frac{G_m T}{C}.$9 relation itself. Because the reference transconductance is set by resistor and geometry ratio rather than directly by $G_m$0, moderate supply variation should not strongly alter the reference $G_m$1 as long as the transistors remain in the intended operating region. The paper presents this as the first layer of supply stabilization.

The second layer is the regulated current-mirror network. M7, M8, M18, M19, M22, M23, M26, and M27 are used as common-gate devices to isolate current-mirror drain voltages from output-voltage changes and to equalize input-branch and output-branch drain voltages. This reduces current-mirror error caused by channel-length modulation, finite output resistance, and branch $G_m$2 mismatch. In consequence, the current that reaches the main transconductor more faithfully tracks the reference current set by the constant-$G_m$3 cell.

Temperature compensation is achieved through closed-loop bias adaptation rather than an explicit PTAT or CTAT summation. Mobility typically decreases with temperature, threshold voltage also changes with temperature, and therefore at fixed current the overdrive and $G_m$4 drift. In the self-biased loop, however, current is not fixed independently; it is allowed to adjust until the resistor drop and transistor equations balance. Changes in $G_m$5 and $G_m$6 are therefore absorbed primarily as changes in current and overdrive, while the resulting $G_m$7 remains near the resistor-set value (Yang et al., 20 Aug 2025).

The resistor is the true transconductance-setting element, since the reference equation shows $G_m$8. The paper does not discuss resistor type or temperature coefficient. A practical interpretation is that residual gain drift will be limited by resistor TC, nonideal square-law behavior, mirror mismatch, finite output resistance, and incomplete cancellation.

5. Interface to the composite transconductor and measured behavior

The amplifier uses a composite differential pair formed from two mirrored asymmetric differential pairs for linearization. The constant-$G_m$9 bias circuit interfaces with this composite transconductor by setting a reference condition at M24/M25/R1, mirroring the resulting current with factor $T$0, delivering that current to M9 and M10, and thereby biasing the branches containing M1-M4. Since each input transistor $T$1 scales as $T$2, and $T$3 is generated by the constant-$T$4 loop, the transconductance of the input devices becomes a function primarily of ratios and $T$5, rather than of environmental variation.

The direct quantitative evidence for the bias architecture is the gain sensitivity to temperature and supply-voltage variation. The reported test condition is an input $T$6, temperature swept from $T$7 to $T$8, and supply varied from $T$9 to $C$0 around nominal $C$1, corresponding to $C$2. Gain is measured as differential output divided by $C$3 (Yang et al., 20 Aug 2025).

Design	Gain standard deviation	Gain range
Traditional Gm-C dynamic amplifier	1.9	13 to 19.5
Proposed amplifier with constant-$C$4 bias	262m	15.1 to 16.3

These numbers indicate that the gain range shrinks from $C$5 to $C$6, while the standard deviation shrinks from $C$7 to approximately $C$8. Since the proposed amplifier differs from the traditional design both in linearized transconductor structure and in constant-$C$9 biasing, the temperature and supply sweep is the clearest evidence specifically attributable to the bias architecture.

6. Limitations, caveats, and design implications

The constant-$C$0 bias circuit is presented as a means of stabilizing temperature and supply dependence, not as a complete remedy for process variation. The paper explicitly states that when the amplifier is used as a residue amplifier in a pipelined SAR ADC, the gain is still influenced by process corners. After fabrication, the gain must therefore be calibrated once by adjusting R1 or by other methods. R1 is thus both the fundamental transconductance-setting element and a practical calibration handle (Yang et al., 20 Aug 2025).

The architecture also contains a headroom tradeoff. The common-gate and cascode devices improve current-copy accuracy and preserve the intended bias behavior, but they consume voltage headroom. The implementation operates at $C$1 in $C$2, where this is acceptable; a plausible implication is that the same strategy may become more constrained if ported to lower-voltage nodes.

A second caveat is that constant-$C$3 behavior in theory does not guarantee identical current delivery in practice. The use of M7, M8, M18, M19, M22, M23, M26, and M27 shows that finite output resistance and drain-voltage mismatch would otherwise spoil current-copy accuracy and therefore spoil effective constant-$C$4 behavior at the main stage.

A third caveat is startup. Self-biased constant-$C$5 cells often have both a desired nonzero-current operating point and a zero-current metastable state, but the paper provides no explicit startup discussion, no startup branch description, and no startup simulation. Startup robustness therefore remains an undocumented assumption.

The principal technical interpretation is that the constant-$C$6 bias circuit is a ratio-and-resistor-based self-bias reference adapted to a dynamic Gm-C amplifier. Its function is to stabilize the main-stage transconductance so that, in conjunction with stable $C$7 and stable $C$8, the overall gain remains much less sensitive to temperature and supply-voltage variation. Its limits are equally explicit: process spread remains, resistor accuracy matters, mirror nonidealities must be actively suppressed, and startup is not documented.