Multi-Channel Readout Chip (MCRC) Overview

• MCRC is an integrated multi-channel readout solution that consolidates front-end amplification, shaping, and digitization for various detector systems.
• It features configurable analog chains and on-chip digital processing to reduce cabling, control noise, and match detector occupancy and timing.
• Design trade-offs in MCRC development focus on balancing noise, bandwidth, dynamic range, and power consumption to meet specialized application needs.

Searching arXiv for recent and foundational papers on multi-channel readout chips across detector domains. A Multi-Channel Readout Chip (MCRC) is an integrated readout device that services multiple detector channels in parallel and, depending on the application, can combine front-end amplification, shaping, discrimination, digitization, buffering, trigger logic, multiplexing, and data-reduction functions on the same chip or in a tightly coupled readout module. In the literature, the term spans semi-digital ASICs for resistive-plate chambers, waveform-sampling chips for Cherenkov cameras and MCP detectors, low-noise analog front ends for X-ray CCD-like sensors, cryogenic skipper-CCD readout ASICs, and high-density SoC digitizers for picosecond photodetectors (Kumar et al., 2016, Bechtol et al., 2011, Orel et al., 2024, Bessia et al., 2023, Seljak et al., 2024, Li et al., 27 Nov 2025). The unifying idea is architectural consolidation: many detector channels are handled locally, with reduced external cabling, controlled noise, and a readout format matched to detector occupancy and timing.

1. Detector-driven meaning and scope

The meaning of an MCRC is determined primarily by detector topology and system scale. In the INO-ICAL case, the requirement arises from about 29,000 glass RPC detectors of $2\,\mathrm{m} \times 2\,\mathrm{m}$, each with 64 readout channels in $X$ and 64 in $Y$, making detector-embedded, low-line-count readout mandatory; HARDROC was evaluated there as a 64-channel semi-digital ASIC with on-chip zero suppression and daisy-chain communication (Kumar et al., 2016). In MPGD tracking, SALSA was defined as a 64-channel chip for the EPIC experiment at the EIC, with continuous-streaming compatibility, per-channel ADCs, and a configurable DSP to manage output bandwidth under signal rates of order $10\,\mathrm{kHz}$ and time resolution of order $10\,\mathrm{ns}$ (Neyret et al., 17 Jan 2025).

In X-ray instrumentation, the same term denotes a compact analog front end integrated close to CCD outputs. The Stanford MCRC for MIT Lincoln Laboratory detectors was developed as an 8-channel ASIC that biases the detector output stage, amplifies the signal, and drives an external ADC, with selectable source-follower and drain-current input modes for conventional CCDs and SiSeRO devices (Orel et al., 2024, Chattopadhyay et al., 19 Aug 2025). In skipper-CCD work, MIDNA is explicitly framed as a multi-channel readout chip specialized for repeated non-destructive sampling, cryogenic operation, and sub-electron noise (Bessia et al., 2023).

Other instances broaden the concept rather than contradict it. GRAPH is a 16-channel mixed-signal readout ASIC for crossed-strip MCP detectors, where the essential requirement is waveform capture with local buffering and region-of-interest extraction (Seljak et al., 2024). TARGET is a 16-channel, GSa/s switched-capacitor-array digitizer for Cherenkov telescope cameras, where the MCRC is defined by deep analog storage, self-triggering, and tight windowed readout (Bechtol et al., 2011). Commercial parts can also occupy the same functional niche: ADAS1128 was used as a 128-channel current-integrating front end for Micromegas muon imaging, and Nalu’s HDSoC and AARDVARC were used as multi-channel waveform digitizers for second-generation LAPPDs (Wang et al., 2024, Li et al., 27 Nov 2025).

2. Common circuit architecture

Despite the diversity of detector modalities, MCRCs repeatedly instantiate a per-channel analog chain that conditions a small detector signal before thresholding or digitization. HARDROC provides a variable-gain preamplifier per channel with gain up to $\times 2$, 8-bit per-channel tuning, three fast CR-RC shapers with peaking time $\approx 20$–$25\,\mathrm{ns}$, three low-offset discriminators, and one slow shaper with $50$–$150\,\mathrm{ns}$ shaping and track-and-hold for analog diagnostic output up to $X$0 (Kumar et al., 2016). SALSA uses a charge-sensitive amplifier, pole-zero cancellation stage, and shaper, offers four gain ranges from $X$1–$X$2 to $X$3–$X$4, and eight selectable peaking times between $X$5 and $X$6 (Neyret et al., 17 Jan 2025).

For X-ray CCD-like sensors, the front end is usually analog and differential rather than threshold-centric. MCRC-V1 implements selectable voltage-input and current-input stages, on-chip bias generation for the detector output transistor, a fully differential preamplifier with two gain settings, and a unity-gain differential output buffer able to drive a $X$7 line directly into an external ADC (Orel et al., 2024). In the SiSeRO drain-current mode, the chain is further specialized into an active cascode, programmable current source, $X$8 current-to-voltage amplifier, AC coupling, differential preamplifier, and output buffer (Chattopadhyay et al., 19 Aug 2025).

Cryogenic skipper-CCD readout pushes the architecture in a different direction. MIDNA integrates four channels, each containing a folded-cascode preamplifier, a DC restorer, and a dual-slope integrator with chopping to suppress low-frequency noise generated inside the integrator itself (Bessia et al., 2023). GRAPH, by contrast, combines a programmable fast charge-sensitive front end with the Hybrid Universal sampLing Architecture, where each sample cell incorporates a sampling capacitor, local comparator, overwrite-protection logic, and a 12-bit digital register (Seljak et al., 2024). TARGET uses per-channel switched-capacitor-array storage and Wilkinson conversion; here the buffer architecture rather than the preamplifier topology defines the chip (Bechtol et al., 2011).

This diversity indicates that “multi-channel” is not a single circuit template. It is a systems category in which the analog chain, memory organization, and trigger path are specialized to the detector’s signal duration, expected occupancy, and downstream bandwidth.

3. Readout modes, triggering, and data reduction

A central distinction among MCRCs is whether they perform thresholded, integrated, or waveform-based readout. HARDROC is a semi-digital design. Each channel has three thresholds set by internal 10-bit DACs, and discriminator outputs are fed to a 3-inputs-to-2-outputs encoder that generates 2-bit semi-digital coding. The chip evaluates the status of the 64 lowest-threshold comparators every $X$9; if any fires, the 64-channel data are captured, stored in a 128-deep digital memory, and frames with no fired channels are not stored, thereby implementing zero suppression (Kumar et al., 2016).

SALSA represents the opposite pole: per-channel waveform digitization followed by on-chip digital processing. Each of its 64 channels includes a 12-bit SAR ADC operating from $Y$0 to $Y$1, and the chip-level DSP performs pedestal equalization, common-mode noise subtraction, baseline following, IIR filtering, low-amplitude sample suppression, and feature extraction of amplitude, time of arrival, and signal width (Neyret et al., 17 Jan 2025). GRAPH likewise stores sampled waveforms locally, with 2048 samples per channel, a sampling frequency adjustable from a few kHz up to $Y$2, and a region-of-interest sample-read algorithm that extracts only the samples around the pulse peak while the next event is being selected (Seljak et al., 2024). TARGET extends waveform-centric readout to the GSa/s regime, with 4096 samples per channel in TARGET~1 and 16384 samples per channel in TARGET~2, plus self-trigger functionality and tight window-selected digitization (Bechtol et al., 2011).

Other MCRCs use digitization outside the chip, or integrate over a fixed window instead of sampling a waveform. The Stanford X-ray MCRC explicitly omits analog CDS/DSI on the ASIC; the analog differential output is digitized externally, and CDS or optimal filtering is applied in the controller or off-line (Herrmann et al., 2024). ADAS1128 integrates 128 current amplifiers, sample/hold stages, and two 24-bit ADCs, but its operating principle is current integration over a programmable window from $Y$3 to $Y$4, with the results from cycle $Y$5 output during cycle $Y$6, ensuring no dead time or charge loss (Wang et al., 2024).

A recurring implication is that on-chip ADCs are not a defining requirement. Some MCRCs are front-end-plus-buffer devices, some are front-end-plus-ADC-plus-DSP devices, and some are mixed-signal samplers whose digitization is tightly coupled to storage and trigger control.

4. Integration, bandwidth, and scaling

MCRCs are often justified less by single-channel performance than by the way they collapse a large detector system into manageable modules. HARDROC was evaluated precisely because detector-embedded electronics and daisy-chain interconnection reduce external I/O lines for a detector system approaching $Y$7 RPCs; the chip was implemented as a COB on a 6-layer PCB with FPGA-based readout and control (Kumar et al., 2016). The same integration logic appears in SALSA, where local DSP is required because the raw data flux at $Y$8 bits is $Y$9, far above the chip’s maximum $10\,\mathrm{kHz}$0 aggregate output provided by up to four $10\,\mathrm{kHz}$1 serial links (Neyret et al., 17 Jan 2025).

High-energy-physics pixel systems show the same pattern at much higher link speed. The CMS Phase-2 pixel readout chip is controlled through a single $10\,\mathrm{kHz}$2 electrical downlink and transmits through four $10\,\mathrm{kHz}$3 CML uplinks, for $10\,\mathrm{kHz}$4 aggregate outbound bandwidth per chip, over low-mass twisted-pair links up to $10\,\mathrm{kHz}$5 long and tested to $10\,\mathrm{kHz}$6 (Smith, 2021). In scalable MPGD systems, the ASIC is only one tier in a hierarchy: the SRS architecture uses ASIC cards, Adapter cards, and FPGA-based Front-End Cards, with one FEC covering 512 channels in the VA140 prototype or 256 channels with AGET, and 17 FECs in a chassis yielding 8704 prototype VA140 channels or 17408 channels if all 64 channels per chip are bonded out (Zheng et al., 2016).

Large skipper-CCD systems demonstrate the scaling pressure from another angle. The OSCURA packaging study does not present a dedicated MCRC, but it defines the environment a future MCRC would have to inhabit: 1500 multi-chip modules, 16 skipper-CCDs per module, and 24000 readout channels in total, with a total readout time of $10\,\mathrm{kHz}$7 hours and a target noise of $10\,\mathrm{kHz}$8 per pixel (Botti et al., 2024). For Gen-II LAPPDs, commercial SoC readouts show a different scaling trade-off: HDSoC offers 32 channels in the board used, with a 64-channel second revision existing, while AARDVARC offers 4 channels in the evaluation board and 8-channel variants, reflecting the usual channel-density versus timing-performance compromise (Li et al., 27 Nov 2025).

5. Performance regimes and design trade-offs

The most persistent MCRC design trade-off is among noise, bandwidth, dynamic range, and power. HARDROC reached practical threshold settings down to $10\,\mathrm{kHz}$9, corresponding to $10\,\mathrm{ns}$0 noise, with auto-trigger capability down to $10\,\mathrm{ns}$1; gain equalization reduced channel-to-channel dispersion of the threshold inflection point from $10\,\mathrm{ns}$2 to $10\,\mathrm{ns}$3 for $10\,\mathrm{ns}$4 injection, and calibration gave $10\,\mathrm{ns}$5 DAC units at gain $10\,\mathrm{ns}$6 (Kumar et al., 2016). Yet the same work explicitly does not report cosmic-muon efficiency, timing resolution with real RPC signals, quantitative crosstalk, or per-chip power consumption, illustrating that MCRC validation is often staged rather than final.

SALSA exposes a more explicit bandwidth budget. The front-end prototype measured an ENC of $10\,\mathrm{ns}$7 under typical MPGD conditions, while the full chip targets $10\,\mathrm{ns}$8–$10\,\mathrm{ns}$9 sampling, $\times 2$0 effective bits in the operating range, and $\times 2$1 at $\times 2$2. Because the output bandwidth is capped at $\times 2$3, practical operation depends on the occupancy factor and DSP compression factor, not only on analog noise (Neyret et al., 17 Jan 2025). GRAPH illustrates a related compromise: it achieves $\times 2$4, a nominal $\times 2$5–$\times 2$6 input range, 2048 samples per channel, and $\times 2$7 sampling, but the measured usable analog headroom is $\times 2$8, the ADC noise after pedestal calibration is $\times 2$9, and the effective ENOB is $\approx 20$0 bits due to comparator offsets, ramp distribution, and occasional conversion outliers (Seljak et al., 2024).

In X-ray CCD work, the trade-off is commonly expressed as speed versus read noise at fixed spectroscopic performance. MCRC V1 coupled to CCID-93 achieved $\approx 20$1 read noise at $\approx 20$2 per output and Fe-55 FWHM of $\approx 20$3–$\approx 20$4, with performance virtually identical to the group’s best discrete amplifier implementation (Herrmann et al., 2024). The later MCRC-V1 study reports total ASIC power of $\approx 20$5 at optimal bias for eight channels, compared with $\approx 20$6 for the discrete eight-channel solution, and demonstrated radiation tolerance at least up to $\approx 20$7 TID with no digital bit errors and minimal analog drift up to $\approx 20$8 (Orel et al., 2024). The SiSeRO extension preserved comparable performance at $\approx 20$9, with ENC $25\,\mathrm{ns}$0 and FWHM $25\,\mathrm{ns}$1 at $25\,\mathrm{ns}$2, and pushed the drain-current mode to $25\,\mathrm{ns}$3 with ENC $25\,\mathrm{ns}$4 and FWHM $25\,\mathrm{ns}$5 (Chattopadhyay et al., 19 Aug 2025).

At the extreme low-noise end, MIDNA showed $25\,\mathrm{ns}$6 with $25\,\mathrm{ns}$7 skipper samples at room temperature, $25\,\mathrm{ns}$8 at $25\,\mathrm{ns}$9 using residual cancellation, and $50$0 using analog pile-up, while consuming $50$1–$50$2 per channel (Bessia et al., 2023). For picosecond photodetection, the limiting metric becomes timing rather than ENC: AARDVARC achieved electronics-only pair jitter of $50$3 in internal-trigger mode and $50$4 in external-trigger mode, whereas LAPPD pair jitter at SPE-level coincidence was typically $50$5 and often several hundred picoseconds, showing that detector statistics and trigger logic can dominate even when the MCRC-class digitizer itself is fast (Li et al., 27 Nov 2025).

A plausible implication is that MCRC design is usually constrained less by any single figure of merit than by the shape of the full operating envelope: occupancy, trigger strategy, calibration method, external interconnect, and acceptable dead time are often as decisive as nominal front-end noise.

6. Variants, boundary cases, and development directions

The term “MCRC” is broad enough that boundary cases matter. Not every multi-channel readout solution is a monolithic ASIC with one ADC per channel, and not every such chip is optimized for the same abstraction of a “channel.” In spin-qubit readout, for example, channelization can be frequency-domain rather than time-domain: an on-chip multiplexing network integrates a bias tee and LC resonator per channel so that multiple rf-QPC and dispersive gate sensors share a single $50$6 line, with channel identity defined by resonance frequency rather than replicated baseband front ends (Hornibrook et al., 2013). Conversely, a system such as the 20:1 LMH6574 multiplexer for directional dark-matter TPCs is not a detector-specific ASIC at all, but it still demonstrates MCRC-like design constraints such as switch dead time, grounding, and preservation of charge-distribution asymmetry after de-multiplexing (Ezeribe et al., 2017).

A concise cross-section of representative implementations is given below.

Implementation	Detector context	Characteristic features
HARDROC	RPCs for INO-ICAL	64 channels, three thresholds, zero suppression, 128-deep memory
SALSA	MPGD for EPIC/EIC	64 channels, 12-bit ADC per channel, DSP, up to $50$7 output
MCRC-V1	MIT-LL CCDs and SiSeRO	8 channels, selectable SF/DR input, external ADC
MIDNA	Skipper-CCD	4 channels, DSI, chopping, cryogenic sub-electron readout
GRAPH	Crossed-strip MCP	16 channels, HULA memory, ROI extraction
TARGET / TARGET~2	IACT cameras	16 channels, GSa/s SCA, self-trigger, windowed readout

Current development directions preserve the same detector-driven specialization. SALSA’s roadmap proceeds through a 32-channel prototype in 2025, a full-channel pre-series in 2026, and production at the horizon of 2027 (Neyret et al., 17 Jan 2025). The next X-ray MCRC iteration expands the channel count from 8 to 16, adds per-output enable/disable control, an internal temperature sensor, and on-chip reset-gate clock drivers (Orel et al., 2024). In SiSeRO work, the next revision is expected to address the I2V resonance seen in the first drain-current tests and to support integrated, parallel RNDR for multi-output CCD and APS variants (Chattopadhyay et al., 19 Aug 2025). In large skipper-CCD experiments, the silicon package work implies that any future MCRC must tolerate video-line capacitances of $50$8–$50$9, operate within a 24000-channel architecture, and preserve $150\,\mathrm{ns}$0 behavior over large skipper-sample counts while remaining compatible with low-background packaging constraints (Botti et al., 2024).

Taken together, these developments show that an MCRC is best understood not as a single chip family, but as a design class: a detector-proximate, many-channel readout engine whose analog front end, local memory, trigger logic, and data path are co-optimized for a specific measurement regime.