Superconducting Nonvolatile Memory

• Superconducting nonvolatile memory is a technology that stores data in metastable superconducting states, providing persistent data retention without continuous energy input.
• It employs diverse mechanisms such as vorticity, Josephson vortex occupancy, magnetic textures, and phase-slip events to encode digital information.
• Its ultralow energy dissipation, high speed, and compatibility with cryogenic systems make it essential for scalable quantum and classical computing architectures.

Superconducting nonvolatile memory refers to a class of memory elements in which binary or multi-bit information is stored in metastable physical states of superconducting circuits, robust against thermal or electronic noise, and without the need for continuous energy input. Unlike conventional volatile superconducting RAM (such as SFQ registers), these systems exhibit data retention even in the absence of applied bias, leveraging physical mechanisms—vorticity, magnetic texture, Josephson vortex occupancy, charge trapping, or topological phase slips—that are stable on timescales far exceeding operational requirements. Superconducting nonvolatile memory has emerged as one of the foundational requirements for scalable cryogenic classical and quantum computing, due to its unique combination of ultralow energy dissipation, high speed, and compatibility with superconducting logic and quantum subcircuits.

1. Physical Mechanisms and Encoding Principles

Physical encoding in superconducting nonvolatile memory exploits the topologically stable or energetically metastable states available in mesoscopic superconductors, Josephson circuits, or hybrid superconductor–ferromagnet composites. The principal mechanisms include:

• Vorticity-Based Storage: The quantized 2π phase winding (or vorticity $n$) of the superconducting order parameter around a planar or nanowire loop serves as a natural digital variable. The persistent supercurrent corresponding to each $n$ is stabilized by kinetic or geometric inductance and, for nanoscale loops, is immune to magnetic crosstalk (Murphy et al., 2017, Zhao et al., 2017, Nulens et al., 4 May 2025). These devices often use phase-slip events or controlled current pulses to change $n$.
• Josephson Vortex Occupancy: In long Josephson junctions, stationary Josephson vortices (JVs, 2π phase solitons) can be trapped, each carrying one flux quantum. Their count $n$ forms a robust memory variable. Entry and exit barriers stemming from edge geometry and the sine-Gordon soliton structure ensure metastability and nonvolatility (Kalashnikov et al., 2023).
• Hybrid Magnetic Textures: The relative alignment of ferromagnetic layers or the occupation of magnetic vortex/core states within a mesoscopic FM provides bistable stray fields, shifting Josephson interference patterns and thus the Josephson critical current. The ground state of the junction (e.g., 0 or π phase, or $I_c^{V}\neq I_c^{M}$) maps one-to-one to the magnetic texture, yielding a nonvolatile memory bit (Baek et al., 2013, Fermin et al., 2022).
• Kinetic Inductance and Persistent Currents: Information is stored in the direction or magnitude of a persistent current in a high-kinetic-inductance nanowire loop, with or without a phase-slip junction (Murphy et al., 2017, Ilin et al., 2020, Medeiros et al., 28 Mar 2025).
• Phase-Slip-Induced Topological Protection: Long, quasi-1D nanowire weak links in a ring exhibit topological double-well energy landscapes, with hysteretic phase slip transitions between winding number sectors. The encoded data is protected by large energy barriers against thermal and quantum phase slips (Ligato et al., 2020, Nulens et al., 4 May 2025).
• Charge Trapping and Gate-Controlled Superconductivity: Accumulated charges in the dielectric locally gate a superconducting weak link or Dayem bridge, shifting the threshold for supercurrent suppression; this is a dual analog of floating-gate flash but realized for cryogenic logic (Ruf et al., 21 Mar 2025).

2. Device Architectures and Representative Implementations

A broad range of device architectures has been demonstrated, each tailored to maximize density, robustness, energy efficiency, or logic compatibility. Notable classes include:

Memory Type	Physical Variable	Experimental Realization
Josephson Vortex	JV occupation, $n$	Planar SNS JJ in coplanar resonator
Kinetic-Inductance	Vorticity, persistent I	Asymmetric Nb or NbN nanowire loops
Vortex Trap	Abrikosov vortex state	Patterned Nb with nanohole trap
Hybrid Magnetic	FM alignment, phase	S–F–N–F–S or S–F–S Josephson stacks
Phase-Slip (Topol.)	Phase-slip sector, $n$	Al nanowire JJ in ring + SQUIPT probe
Nanowire nMem	Loop persistent current	NbN loop with nanowire cryotrons
Gate-Imprinted	Trapped charge, $Q$	Nb bridge on sapphire, voltage gated
Superhydride Flux	Granular flux pinning	La-(Nd,Sc,Ce)H$_x$ at 175–196 GPa
Vortex RAM/VTM	Flux state in SQUID loop	JJ-based RF-SQUID/interferometer cells

• Josephson-Vortex Memory: The cell comprises a planar Nb/Cu/Nb SNS junction (L ≈ 1.9 μm), embedded in a coplanar microwave resonator (~7 mm). The metastable count of JVs, $n$, is controlled by magnetic field pulses and read out non-destructively by resonance frequency shifts in S$_{21}(f)$. Each write/erase event dissipates ∼1 aJ, and readout can be performed at energy ≪1 aJ and in 100 ns, enhanced in principle to <10 ns by lowering $Q_l$ (Kalashnikov et al., 2023).
• Kinetic-Inductance Loop Memory: Nanoscale Nb nanowire loops (dimensions down to ∼500 nm) encode vorticity $n$ by means of phase quantization and kinetic inductance-dominated loop energy. Asymmetry enables selective writing. Readout uses critical current switching or, in advanced forms, integration into resonators for non-destructive read (Murphy et al., 2017, Ilin et al., 2020).
• Vortex Trap-Based RAM: Patterned Nb thin films (1×1 μm$^2$) incorporate asymmetric groove “easy-tracks” and a nanohole trap for Abrikosov vortices. Coincident word-line/bit-line pulses control vortex entry/exit, and readout is realized by resistance measurement in the passive (bit-line) direction. Sub-micron footprints permit projected densities of 10$^8$ bits/cm$^2$ (Golod et al., 2023); similar bistable-vortex concepts enable 50 GHz multi-bit crossbar arrays (Karamuftuoglu et al., 2024).
• Hybrid Superconducting-Magnetic Devices: S–FM–S or S–FM–N–FM–S Josephson junctions leverage exchange-field-controlled 0–π phase shifts, with parity (AP/P) encoded in the magnetization configuration. Devices exhibit size-independent, infinite retention at cryogenic T, switching energies in the fJ range, and are compatible with SFQ and crossbar RAM architectures (Baek et al., 2013, Ingla-Aynés et al., 10 Jan 2026).
• Topologically Protected Phase-Slip Memory: Hysteretic switching between winding states in a long Al nanowire weak link ring produces robust nonvolatility immune to stochastic phase-slip errors. Single-shot readout via SQUIPT probes achieves picosecond read/write with energy per bit 10$^{-24}$–10$^{-20}$ J (Ligato et al., 2020, Nulens et al., 4 May 2025).
• Cryotron-Operated Nanowire Memory: Nanowire storage loops, addressed via adjacent heat- or current-crowding cryotrons (hTron/yTron), offer write/read cycles with sub-fJ energy and 10–20 ns latencies. Persistent current states provide indefinite retention. Row-column arrays have demonstrated BER<10$^{-5}$ and functional densities >2 Mbits/cm$^2$ (Zhao et al., 2017, Medeiros et al., 28 Mar 2025).
• Gate-Imprinted and Charge-Trap Superconducting Memory: Voltage pulses applied to a gate dielectric (e.g., sapphire) inject/trap charges, locally modulating superconductivity and shifting critical current thresholds. Retention exceeds 24 h; write/erase energies are expected to fall into the fJ–pJ regime with proper scaling (Ruf et al., 21 Mar 2025).

3. Read/Write Protocols and Energy Efficiency

Read and write operations vary according to the physical mechanism:

• Vorticity/Josephson-Vortex/Phase-Slip Memory: Write operations commonly use calibrated magnetic field pulses or current pulses to inject or remove fluxons/phase-windings. The corresponding energy per event can be as low as 1 aJ (Josephson vortex (Kalashnikov et al., 2023)), 0.5 fJ (kinetic-inductance (Zhao et al., 2017)), or even sub-aJ (topological phase-slip (Ligato et al., 2020)). Write speed is set by intrinsic dynamics (sub-100 ps for phase slip; sub-10 ps for JV-injection under optimal conditions).
• Non-Destructive Readout: JV-memories and similar schemes use dispersive microwave (S$_{21}$) readout or local impedance measurement, which leave the metastable state intact and enable repeated, essentially non-destructive reads with minimal (<1 aJ) energy cost (Kalashnikov et al., 2023, Nulens et al., 4 May 2025).
• Destructive Readout: Certain nanowire- and kinetic-inductance-based designs employ switching-based reads, which require the memory state to be rewritten post-read (Medeiros et al., 28 Mar 2025).
• Hybrid Magnetic and Texture-Controlled Devices: Writing may involve local magnetic field pulses (few mT), heat-assisted magnetization reversal (sub-ns feasible with optimized heaters), or spin-transfer torque (ballistic sub-ns pulses). Readout uses critical current switching, SQUID comparators, or voltage detection at specified bias (Baek et al., 2013, Fermin et al., 2022, Ingla-Aynés et al., 10 Jan 2026).
• Gate-Imprinted and Charge Trap: “Write” and “erase” are performed by positive/negative voltage pulses, which set the trapped charge in the dielectric and thus shift the $I_c$–$V_G$ curve. Readout is performed at subthreshold voltage via a current ramp/detection scheme (Ruf et al., 21 Mar 2025, Chen et al., 22 Dec 2025).

4. Performance Metrics and Limits

Key quantitative metrics and comparative points across superconducting nonvolatile memory types:

Memory Type	Write Energy	Read Energy	Write Latency	Read Latency	Retention	BER (Best)	Cell Area
Josephson vortex (Kalashnikov et al., 2023)	∼1 aJ	≪1 aJ	<50 ps (model)	<10 ns (model)	>hours@35 mK	N/A (Δf/δf∼10)	Lithographic ($\gtrsim \lambda_J$)
Kinetic-inductance loop (Murphy et al., 2017, Ilin et al., 2020)	0.5–1 fJ	Sub-fJ	Sub-ns–10 ns	Sub-ns	>2 h (test)	10$^{-5}$	≲0.1 $\mu$m$^2$
Vortex-trap (Golod et al., 2023)	∼10$^{-16}$–$10^{-18}$ J	<10$^{-18}$ J	<1 ns (intrinsic)	<1 ns	>10$^4$ s	Not specified	1–0.2 μm$^2$
Nanowire nMem (Zhao et al., 2017, Medeiros et al., 28 Mar 2025)	2 fJ–1.3 pJ	2 fJ–0.23 pJ	10–20 ns–80 ns	∼100 ns	No flips (20 s)	10$^{-5}$	3×7 to 0.03 μm$^2$
Hybrid S/F/M (Baek et al., 2013, Fermin et al., 2022, Ingla-Aynés et al., 10 Jan 2026)	1–100 fJ	∼10$^{-19}$ J to nA	sub-ns (STT), ms–s	ns–μs	>years (AP vs P)	10$^{-6}$	0.1–1 μm$^2$
Phase-slip/topological (Ligato et al., 2020, Nulens et al., 4 May 2025)	10$^{-24}$–10$^{-20}$ J	5–10 μeV	∼1 ps	∼30 ps	>3 d @ 25 mK	Not specified	≤0.01 μm$^2$
Gate-imprinted (Ruf et al., 21 Mar 2025)	29 μJ (current)	pJ–fJ (optimistic)	Manual s, <ms (future)	<ms	>24 h	100% (few cycles)	~1 μm$^2$
Superhydride/granular (Semenok et al., 2024)	1–5 J ($\downarrow$ est.)	∼1.5×10⁻⁷ J	>100 ms	∼ms–s	hours–days @ 220 K	N/A	DAC pellet

All values as reported or immediately derivable; device and integration improvements are ongoing in each domain.

5. Scalability, Integration, and System Considerations

Nonvolatile superconducting RAM elements are compatible with superconducting VLSI, SFQ-logic, and hybrid cryo-CMOS co-integration. Integration strategies include:

• Multiplexed Readout: Microwave and frequency-multiplexed protocols enable $>$1,000 memory cells per common feedline (Kalashnikov et al., 2023, Nulens et al., 4 May 2025).
• Crossbar Architectures: Bistable-vortex and nanowire loop arrays (row/column addressed) achieve densities >10 Mbit/cm$^2$ and scale with lithographic advances (Medeiros et al., 28 Mar 2025, Karamuftuoglu et al., 2024).
• Transformless Cell Design: Removal of readout transformers and adoption of resistive or direct-inductive coupling reduces footprint and parasitics (Karamuftuoglu et al., 2024).
• Non-destructive and destructive options: Designs vary in whether readout is nondestructive (preferred for repeated access) or destructive (requiring write-after-read protocols).
• Logic Integration: Superconducting nonvolatile memory can be directly interfaced with SFQ pipelines, reciprocal quantum logic, and even act as functional logic elements (e.g., NAND) due to reversibly programmable $I_c$ thresholds or phase-states (Ruf et al., 21 Mar 2025, Karamuftuoglu et al., 2024).
• Materials and Process Compatibility: Realized using Nb, NbN, Al, cuprates/hydrides or FM layers (EuS, CoFe), these devices exploit established superconducting and hybrid fabrication processes.

Emerging directions include sub-100 nm lithography, multi-layer 3D integration, voltage-controlled (CMOS-compatible) operation, and operation above 4 K or even 77 K (in hydrides) (Semenok et al., 2024).

6. Challenges, Limitations, and Prospects

While the energy efficiency and speed of superconducting nonvolatile memory are unmatched, several challenges persist:

• Thermal and Quantum Stability: Devices based on flux trapping or phase slips must ensure energy barriers $U\gg k_BT$ at operating temperature to prevent spontaneous switching—this is achieved via inductance engineering, material selection, or kinetic inductance scaling (Murphy et al., 2017, Ligato et al., 2020).
• Write/Erase Protocols: Some schemes (e.g., hybrid S/FM/EIS trilayers, granular hydride memory) currently require slow or energetically intense write/erase (HAMR, field-cooling, or bulk heating); efforts focus on minimizing thermal crosstalk, pulse times, and localizing the stimulus (Ingla-Aynés et al., 10 Jan 2026, Semenok et al., 2024).
• Readout Fidelity and Destructivity: Achieving single-shot, high-fidelity, nondestructive readout remains easier in microwave-coupled memory (resonator-based) than in circuits relying on switching currents. Advanced protocols (SQUIPT, phase-sensitive detection) are being explored (Nulens et al., 4 May 2025, Ligato et al., 2020).
• Footprint and Fan-In Limitations: Scaling to $\sim$1 μm$^2$ or lower cell area requires aggressive nanofabrication, minimal feature inductances, and elimination of transformers—recent progress in kinetic and topological memory addresses this (Murphy et al., 2017, Karamuftuoglu et al., 2024).
• Integration with Cryo-Logic: Memory–logic co-integration at 4 K (or above) necessitates matching impedance environments, ultralow-loss interconnects, and robust protection against magnetic cross-talk or thermal noise (Kalashnikov et al., 2023, Medeiros et al., 28 Mar 2025).

7. Outlook and Future Directions

Superconducting nonvolatile memory stands at the intersection of fundamental soliton/phase engineering and applied cryogenic electronics. Ongoing research highlights several promising trends:

• Topologically Protected and Kinetically Engineered Devices: Exploiting order-parameter topology and phase-slip engineering is poised to enable near-thermodynamic-limit memory cells with retention and error rates far beyond conventional SRAM or DRAM (Ligato et al., 2020, Nulens et al., 4 May 2025).
• Hybrid Superconductor–Magnetic and Electrical Control: Magnetic texture memories and gate-imprinted superconducting states enable wider integration into neuromorphic, in-memory compute, and quantum platforms (Fermin et al., 2022, Chen et al., 22 Dec 2025, Ingla-Aynés et al., 10 Jan 2026).
• High-Temperature and All-Electric Control: Superhydride-based granular memory suggests a route to high-$T_c$ operation, and charge-trapping/gated devices point toward fully voltage-operated, CMOS-interfacing superconducting memory (Semenok et al., 2024, Ruf et al., 21 Mar 2025).
• Primitive In-Memory Computing: Current-summing crossbar arrays and multiply-accumulate operations have been demonstrated at 20–50 GHz with negligible power loss, confirming the feasibility of analog and digital in-memory operations (Karamuftuoglu et al., 2024).
• Scalability Toward Quantum Hardware: Nonvolatile memory architectures compatible with quantum readout protocols, SFQ low-temperature logic, and high-fidelity, low-latency operation are actively being co-developed to enable robust quantum error correction and cold data buffering.

In summary, superconducting nonvolatile memory has advanced beyond proof-of-concept, encompassing a range of physical mechanisms (vorticity, JVs, phase slips, magnetic textures, charge trapping), material systems (Nbn, Al, hydrides, FMs), and architectural paradigms (microwave, kinetic, hybrid, and crossbar). Each brings unique merit in speed, energy, retention, footprint, and integration with low-temperature superconducting electronics, collectively addressing the memory bottleneck in classical and quantum cryogenic computation (Kalashnikov et al., 2023, Murphy et al., 2017, Baek et al., 2013, Golod et al., 2023, Ligato et al., 2020, Zhao et al., 2017, Fermin et al., 2022, Karamuftuoglu et al., 2024, Nulens et al., 4 May 2025, Medeiros et al., 28 Mar 2025, Chen et al., 22 Dec 2025, Ruf et al., 21 Mar 2025, Semenok et al., 2024, Ingla-Aynés et al., 10 Jan 2026).