TLC: Intelligent Traffic Light Controller

• TLC is an FPGA-based Intelligent Traffic Light Controller that uses a sensor-adaptive Moore finite-state machine for dynamic intersection control.
• The design leverages parameterizable down-counters and modular architecture to implement differentiated phase timings with minimal hardware resources.
• The controller supports real-time adaptivity and cost-effective scalability for urban intersections with highly asymmetric flows.

TLC (Traffic Light Controller): Intelligent Intersection Signal Control on FPGA

TLC, in the hardware design and embedded systems context, refers here to an Intelligent Traffic Light Controller, as detailed in "FPGA Implementation of an Intelligent Traffic Light Controller (I-TLC) in Verilog" (Banerjee, 2024). This system realizes intersection traffic management using a parameterized, sensor-adaptive, Moore finite-state machine (FSM), implemented on an FPGA. The controller targets urban intersections with highly asymmetric flows, providing both cost efficiency and fine-grained real-time adaptivity unattainable with microcontroller- or ASIC-based controllers.

1. Architecture and Modular Design

The I-TLC architecture is a compositional, block-structured Verilog design mapping directly to a real four-way intersection with differentiated main and side road priorities:

• Sensor Interface: Accepts IR sensor signals from the side road, debounced and synchronized to eliminate metastability. Input "C" is a combinatorially debounced, single-cycle pulse signaling vehicle or pedestrian presence on the side road.
• Timer Units: Two parameterizable down-counters implement the traffic phase timeouts:
  • TS (Short Timer): Controls the amber phase interval duration.
  • TL (Long Timer): Controls the main and side green phase intervals with selectable values (for simple queue-adaptivity).
  • Both use programmable register loads, supporting external adjustment.
• Moore FSM Core: The FSM is Moore type, maintaining four states (S0–S3) corresponding to the protected and permissive phases for both main and side roads:
  • S0: Main road Green, Side road Red
  • S1: Main road Yellow, Side road Red
  • S2: Main road Red, Side road Green
  • S3: Main road Red, Side road Yellow
  • Inputs: Reset, C, TS_expired, TL_expired; Outputs: Light signals (MG, MY, MR, SG, SY, SR) and timer triggers.
• Top-Level Glue: This layer maps the logical IOs to the physical buttons, slide switches, and LEDs on the Xilinx Spartan-3E (xc3s500e-4-fg320) development board used for realization.

All state and timer transitions are strictly clocked at 50 MHz; output light logic is derived exclusively from the state in Moore-style.

2. Finite-State Machine Model and Timing Semantics

The traffic logic operates as a deterministic transition system:

$$\delta(s_i,\,C,\,TL,\,TS) = \begin{cases} s_1, & s_i = s_0,\,C=1,\,TL=1\ s_2, & s_i = s_1,\,TS=1\ s_3, & s_i = s_2,\,\big(TL=0\lor C=0\big)\ s_0, & s_i = s_3,\,TS=1\ s_i, & \text{otherwise} \end{cases}$$

Transition triggering is determined jointly by timer expiry (TS_expired/TL_expired) and the side-road occupancy (C). The adaptive green time (for the side road) is modeled as $$T_\mathrm{green} = T_\mathrm{min} + k N_\mathrm{waiting}$$, with $k=1$ and $N_\mathrm{waiting}\in\{0,1\}$ in this prototype, enabling basic queue-adaptivity with just one bit of additional hardware logic.

3. Functional Verification and Simulation Methodology

Simulation and coverage validation are executed via the Xilinx ISE 14.7 behavioral simulation suite:

• Testbench infrastructure: Generates a 50 MHz clock, issues controlled reset pulses, randomizes sensor (C) and timer-expiry (TS, TL) signals.
• Outputs monitored: State vector (MG..SR), timer-expiry signals.
• Functional validation: All possible input combinations over FSM and timer interfaces are exhaustively simulated.
• Coverage metrics: 100% state/transition code coverage is reported, indicating no latent untested transitions.

Waveform traces at representative state-change instants (e.g., 29.5 ns, 144.5 ns, 374.6 ns, 566.4 ns) confirm fidelity of logical encoding to design specification.

4. Hardware Realization and Resource Analysis

• Deployment: Xilinx Spartan-3E, xc3s500e-4-fg320, with light outputs mapped to board LEDs and inputs mapped to push-buttons/slide-switches.
• Synthesis/Place & Route: Performed in Xilinx ISE 14.7, with pin- and timing-constraints for single 50 MHz operation.
• Resource utilization: Extremely minimal; only 4/232 slices (1.7%), 3/464 slice-FFs (0.6%), 8/9312 LUTs (0.09%), 12/232 IOBs (5.2%), and 1 global clock net (4.2%). The maximum combinational path delay post-place-and-route is 5.982 ns.
• Performance: Achieved $f_\mathrm{max} \simeq 167\, \mathrm{MHz}$ (6 ns cycle), outperforming both sequential microcontroller (62.5 ns cycle @16 MHz) and matched only by custom-logic ASIC, absent the high NRE cost and lack of reprogrammability associated with ASIC flows.

Platform	Max Clock (MHz)	HW Utilization	Reconfigurability	Per-unit Cost
FPGA (TLC)	$\approx$167	8 LUTs ($<$0.1%)	Bitstream reload, instant	$<$ \$50/board
MCU	$\approx$16	External blocks	Firmware flash required	$<$ \$5/board
ASIC	100–200	NRE > \$T_\mathrm{green} = T_\mathrm{min} + k N_\mathrm{waiting}$0>$T_\mathrm{green} = T_\mathrm{min} + k N_\mathrm{waiting}$10.50/unit

FPGA supports maximal parallelism, dynamic timing reprogramming, and is the only option with field-upgradable logic.

5. Comparative Analysis and Adaptivity

The design delivers critical advantages for modern intersection control:

• Adaptivity: Simple queue-responsive logic using IR sensor feedback for the side road; green phase timings toggle automatically with traffic demand.
• Hardware efficiency: Sub-2% board resource consumption, supporting potential for large-scale multi-intersection or higher-functionality deployments.
• Speed: Sub-6 ns logic response grants high phase-resolution and ultra-low latency between sensor input and light actuation, minimizing unnecessary waiting and maximizing throughput.
• Reconfigurability: In-field updates (e.g., adjusted phase timings, enhanced sensor logic) are possible through bitstream reload.
• Upgrade path: Design is directly portable to higher-end FPGAs for advanced concepts (e.g., camera/image inference, multi-modal sensing, networked control).

6. Future Directions

Recommendations for enhancing TLC extend in three main directions:

• Increased adaptivity: Incorporate queue-length estimation (ultrasonic sensing, computer vision) to permit finely quantized green extension, $T_\mathrm{green} = T_\mathrm{min} + k N_\mathrm{waiting}$2, better matching service to demand.
• Priority preemption: Add logic for emergency vehicles (siren detection/audio sensing) to allow phase interruption.
• Integrated traffic management: Migrate to FPGAs with HPS (Hard Processor System) for real-time, networked intersection communication, edge analytics, and camera inputs.

By leveraging the simplicity of a Moore FSM, parameterized down-counters for phase timing, and the architectural flexibility of FPGA logic, the TLC design achieves scalable, robust, and intelligent intersection control with a minimal hardware and energy footprint (Banerjee, 2024).