EEsizer: LLM-based Transistor Sizing

• EEsizer is an LLM-based agent that iteratively adjusts transistor sizing parameters using closed-loop reasoning and Ngspice simulation feedback.
• It decomposes the AMS design process into structured stages, enabling effective handling of conflicting performance metrics across technology nodes.
• Benchmarking reveals the critical impact of LLM model choice, with models like OpenAI o3 excelling in meeting stringent analog specifications.

EEsizer is an LLM-based AI agent for transistor sizing in analog and mixed-signal (AMS) integrated circuits, proposed as a closed-loop alternative to the manual, simulation-heavy, and expertise-driven sizing workflow that remains common in AMS design. Its defining characteristic is the integration of LLMs with Ngspice simulation, custom analysis functions, prompt engineering, Chain-of-Thought prompting, ReAct-style action/observation/comparison loops, and function calling, so that the agent can iteratively propose sizing changes, evaluate the resulting circuit behavior, compare measured metrics with design targets, and refine subsequent actions without relying on external knowledge or external black-box optimizers in the core sizing loop (Liu et al., 29 Sep 2025).

1. Problem formulation and design rationale

The sizing problem addressed by EEsizer is the selection of transistor widths, lengths, and bias voltages for a fixed AMS topology under multiple, often conflicting, performance constraints. The paper identifies several reasons this task is difficult: the parameter space is high-dimensional, device and bias parameters interact nonlinearly with circuit behavior, target specifications conflict, technology scaling changes the feasible trade-off surface, and open analog design datasets remain limited (Liu et al., 29 Sep 2025).

In this formulation, improving one specification often degrades another. The paper uses examples such as bandwidth versus gain, stability, or distortion, and emphasizes that node dependence is not a secondary issue: sizing decisions that work at 180 nm do not directly transfer to 130 nm or 90 nm because short-channel effects, supply voltage reductions, and mismatch worsen. A further constraint is that LLMs alone are not numerically reliable enough for direct sizing without simulation feedback. This places EEsizer in a distinct category: not a one-shot generative design system, but an iterative agent whose numerical grounding comes from simulator-in-the-loop evaluation rather than from direct parametric prediction (Liu et al., 29 Sep 2025).

A common misconception is that an LLM-based sizing framework replaces circuit simulation. EEsizer does not do so. Its operational premise is that language-model reasoning can structure the search, but only closed-loop interaction with a circuit simulator and analysis functions can determine whether a candidate sizing satisfies the target metrics. This suggests that the contribution is primarily architectural: the paper positions reasoning, tool use, and iterative correction as the mechanism that compensates for the lack of direct numerical precision in the model itself.

2. Agent architecture and closed-loop workflow

EEsizer requires only a SPICE netlist and a set of target performance metrics as input. No extra circuit-type annotation or domain-specific description is required from the user. The agent then decomposes the task into four stages: identify the circuit type and sub-structure; extract input/output nodes for simulation setup; retrieve target performance values; and map the user requirements into structured targets for tool calls (Liu et al., 29 Sep 2025).

The reasoning layer is organized through Chain-of-Thought prompting. The prompt uses the system prompt, circuit type, previous results, current results, and user target. According to the paper, the CoT instructions ask the model to verify transistor regions, identify which metrics need improvement, connect sizing parameters with performance, and propose an optimization step within constraints. Those constraints are technology-specific. For 180 nm, the width range is $[0.18, 400]\,\mu m$, the length range is $[0.18, 18]\,\mu m$, the supply is 1.8 V, and the bias range is $(0, 1.8)$ V. For 130 nm, the ranges are $[0.13, 400]\,\mu m$, $[0.13, 13]\,\mu m$, supply 1.8 V, and bias $(0, 1.8)$ V. For 90 nm, they are $[0.09, 400]\,\mu m$, $[0.09, 9]\,\mu m$, supply 1.2 V, and bias $(0, 1.2)$ V (Liu et al., 29 Sep 2025).

The workflow is therefore not a monolithic optimization pass. It is a repeated cycle in which the LLM proposes a design direction, function calls invoke simulations and analysis tools, the resulting measurements are compared with the desired targets, and the next step is generated from both current and historical observations. The paper explicitly describes this as a closed-loop comparison procedure with minimal human intervention.

This design also clarifies what EEsizer is not. It is not described as using BO, gm/Id scripts, or another external numerical optimizer in the main loop. Nor is it described as relying on domain-specific fine-tuning. Instead, it generates its own labeled information during optimization from simulation outputs and uses that information to guide subsequent reasoning (Liu et al., 29 Sep 2025).

3. Simulation functions, measurements, and stopping criteria

The tool-execution layer is built around predefined simulation and analysis functions invoked through function calling, with Ngspice as the simulator. The general simulation functions are DC simulation, AC simulation, transient simulation, and run Ngspice. The analysis functions for amplifiers include DC gain, input offset, ICMR, THD, output swing, bandwidth, unity-gain bandwidth, phase margin, and CMRR. General metrics include power, delay, and frequency (Liu et al., 29 Sep 2025).

The paper also notes that the measurement setups are not generic wrappers but circuit-aware configurations. It mentions unity-gain configurations for offset and ICMR, open-loop configurations for output swing, and CMRR measurement configurations based on standard CMOS analog testing practice. This is significant because it shows that EEsizer’s apparent generality is mediated by hand-designed analysis procedures rather than by a universal parser that can infer every measurement protocol from the netlist alone.

Stopping is determined by a two-part success rule. After each simulation, measured outputs are compared to the targets using a 5% tolerance. Optimization stops only when all specification flags are true and no transistor operates in subthreshold, checked by ensuring that no values satisfy $v_{gs}-v_{th}<0$ (Liu et al., 29 Sep 2025). If either condition fails, the agent uses the current result and the optimization history to generate the next iteration.

This stopping logic is important for interpreting the reported successes. Meeting numerical targets is necessary but not sufficient; the operating-region constraint excludes superficially acceptable solutions that would depend on subthreshold behavior where it is not intended. A plausible implication is that the framework is designed to avoid metric-only optimization artifacts, although the paper does not claim a formal guarantee beyond the stated checks.

4. Benchmarking on eight LLMs and six basic circuits

The paper first benchmarks eight LLMs under a common protocol: Claude 3.5 Sonnet, Claude 3 Sonnet, Claude 3 Haiku, GPT-4o mini, GPT-4o, GPT-4.1, OpenAI o3, and Gemini 2.0 Flash (Liu et al., 29 Sep 2025). All models are tested with the same prompts, functions, and metrics.

The benchmark circuits are R-load, OTA, OSC, INV, NAND, and XOR. Their targets are specified explicitly: R-load with gain 20 dB, bandwidth 1 MHz, phase margin $[0.18, 18]\,\mu m$0; OTA with gain 40 dB, bandwidth 1 MHz, phase margin $[0.18, 18]\,\mu m$1; OSC with frequency 10 GHz; INV with delay 10 ps and transient power 5 pW; NAND with delay 20 ps and transient power 5 pW; and XOR with delay 30 ps and transient power 5 pW. All runs use a PTM 180 nm transistor model with initial sizing

$[0.18, 18]\,\mu m$2

and a budget of 20 iterations per run; exceeding 20 iterations is counted as a failure (Liu et al., 29 Sep 2025).

The benchmark serves two purposes. First, it is a model-selection stage. Second, it provides evidence that success depends materially on model choice even under an identical agent scaffold. OpenAI o3 had the best overall performance, with the highest success rate, fewest iterations, and lowest variability across circuits. Claude 3.5 Sonnet also achieved 100% success, but needed more iterations on 5T-OTA. GPT-4.1 was strong on most tasks but had only 40% success on the ring oscillator. Claude 3 Haiku worked on digital circuits but failed on the oscillator and 5T-OTA, while GPT-4o mini and Claude 3 Sonnet showed lower success and higher variability. On this basis, the paper selected Gemini 2.0 Flash, GPT-4.1, and OpenAI o3 as the three strongest models for the main case study (Liu et al., 29 Sep 2025).

These results indicate that EEsizer is not model-agnostic in practice, even if its framework is portable across models in principle. The reasoning quality of the underlying LLM remains a dominant variable.

5. Twenty-transistor operational amplifier and node transfer

The main case study is a 20-transistor CMOS operational amplifier with a complementary input stage and a class-AB output stage, evaluated across 180 nm, 130 nm, and 90 nm (Liu et al., 29 Sep 2025). The study targets 10 performance metrics, including rail-to-rail operation. The main metrics reported are gain, unity-gain bandwidth, phase margin, power, CMRR, THD, input offset, output swing, ICMR, and rail-to-rail operation constraints. For the node sweep, the loaded test conditions are $[0.18, 18]\,\mu m$3 and $[0.18, 18]\,\mu m$4, with 5% tolerance on metrics and a stopping budget of 25 iterations; runs exceeding the 25th iteration are considered failures (Liu et al., 29 Sep 2025).

The principal trend reported is degradation with technology scaling from 180 nm to 90 nm. The paper attributes this to stronger short-channel effects, worse matching, harder low-voltage operation, and greater sensitivity of small-signal stability to loading. Within this setting, OpenAI o3 had the best overall performance at all nodes. GPT-4.1 performed well at 180 nm and 130 nm but failed at 90 nm. Gemini 2.0 Flash was strongest at 180 nm but underperformed at smaller nodes. Most importantly, at 90 nm only OpenAI o3 successfully optimized the circuit (Liu et al., 29 Sep 2025).

The paper further resolves the 90 nm experiment into three target groups, G1, G2, and G3. For G1, the targets are gain $[0.18, 18]\,\mu m$5 dB, UGBW $[0.18, 18]\,\mu m$6 MHz, PM $[0.18, 18]\,\mu m$7, power $[0.18, 18]\,\mu m$8 mW, CMRR $[0.18, 18]\,\mu m$9 dB, THD $(0, 1.8)$0 dB, offset $(0, 1.8)$1 mV, output swing $(0, 1.8)$2 V, and ICMR $(0, 1.8)$3 V. The results are G1-1 success in 16 iterations, G1-2 success in 20 iterations, and G1-3 to G1-5 failures. G2 uses a different load and stricter power/frequency conditions, with $(0, 1.8)$4 and $(0, 1.8)$5; G2-1 succeeds in 20 iterations and G2-2 to G2-5 fail. G3 uses $(0, 1.8)$6 and $(0, 1.8)$7; G3-1 succeeds in 16 iterations and G3-2 to G3-5 fail (Liu et al., 29 Sep 2025).

The paper’s headline result is therefore specific rather than universal: OpenAI o3 achieved the user-intended target at 90 nm across three different test groups, with a maximum of 20 iterations, but not every trial in those groups succeeded. This distinction matters. It indicates adaptability and robustness at advanced nodes in the sense intended by the paper, yet it also shows that convergence remains sensitive to initialization, model behavior, or feasibility margins within a fixed iteration budget.

The case study also includes optimized transistor sizes and bias voltages for successful attempts such as G1-2, G2-1, and G3-1. The reported solutions span devices M1–M20 and six bias voltages, indicating that the agent performs coordinated resizing across the full analog bias and signal chain rather than isolated local edits (Liu et al., 29 Sep 2025).

6. Robustness, limitations, and relation to adjacent LLM-based sizing systems

To assess robustness, the paper manually designs a bias circuit for the optimized op-amp and performs a variation analysis on G1-2 using Gaussian-distributed variations on transistor dimensions and threshold voltages. The perturbations are specified as $(0, 1.8)$8 for transistor dimensions and $(0, 1.8)$9 for threshold voltage $[0.13, 400]\,\mu m$0, with threshold variation modeled by adding a voltage source at the gate (Liu et al., 29 Sep 2025).

In the 10-sample variation test, DC and transient behavior remain stable, input offset and output swing stay robust, and rail-to-rail operation is preserved. The most sensitive metric is gain, largely because changes in $[0.13, 400]\,\mu m$1 and parasitic capacitances also affect UGBW and frequency response. In the 50-sample Monte Carlo-style extension across all nine performance metrics, ICMR and output swing show the smallest deviations and consistently meet specifications, while gain and UGBW exhibit larger spreads, with pass rates of 78% for gain and 76% for UGBW (Liu et al., 29 Sep 2025). The paper presents this as evidence of reasonable robustness, while explicitly noting that it is not a full device-model Monte Carlo analysis.

The limitations are also stated directly. The study does not include layout or post-layout simulation. The robustness analysis is simplified. The analysis tools are manually designed for specific circuits, which reduces portability. Experiments are limited to 25 iterations and five trials per configuration due to API rate and cost constraints. The paper also notes that LLM oscillation is possible, so more iterations do not necessarily guarantee better results (Liu et al., 29 Sep 2025).

Within the broader literature, EEsizer can be contrasted with EasySize, another LLM-oriented analog sizing framework that uses a finetuned Qwen3-8B model to generate task-specific loss functions from Ease of Attainability and then applies Differential Evolution and Particle Swarm Optimization inside a feedback-enhanced flow (Wu et al., 7 Aug 2025). EasySize is explicitly heuristic-search-based and reports strong cross-node results from 350 nm training data to 180 nm, 45 nm, and 22 nm, including outperforming AutoCkt on 86.67% of tasks with more than 96.67% of simulation resources reduction (Wu et al., 7 Aug 2025). EEsizer differs in that its core loop is framed not as LLM-guided loss shaping for an external optimizer, but as a closed-loop reasoning agent using simulator calls and custom analyses without external black-box optimizers in the main sizing loop (Liu et al., 29 Sep 2025).

Taken together, these systems suggest two emerging lines in LLM-assisted AMS sizing. One uses LLMs to construct objectives for conventional search procedures; the other uses LLMs as iterative tool-using agents that reason over measurement feedback. EEsizer belongs to the latter line. Its significance, as presented in the paper, is not that it eliminates simulation or analog expertise altogether, but that it demonstrates a practical way for an LLM to act as a sizing agent across multiple circuit types and technology nodes, including successful transfer down to 90 nm under a constrained iteration budget (Liu et al., 29 Sep 2025).