Dynamic Threshold MOSFET (DTMOS) Scheme

• Dynamic Threshold MOSFET (DTMOS) is a design where the gate and body are interconnected to allow real-time adjustment of the threshold voltage, reducing leakage in OFF-state and enhancing drive in ON-state.
• Analytical models and simulations validate that DTMOS and its variant VTMOS achieve significant power savings and noise reduction, making them ideal for sub-threshold and analog circuit applications.
• Practical implementations in digital logic and analog front-ends demonstrate that dynamic threshold control enhances energy efficiency and design flexibility in modern CMOS circuits.

A Dynamic Threshold MOSFET (DTMOS) is a metal-oxide-semiconductor field-effect transistor structure in which the device’s body (substrate) connection is dynamically altered to track the gate terminal. This results in a threshold voltage that varies in real time according to the gate voltage, yielding reduced leakage in the OFF-state and enhanced drive in the ON-state. The DTMOS architecture enables ultra-low power and high current efficiency, especially attractive for sub-threshold, near-threshold circuits and advanced analog front-ends. Extensions such as the Variable Threshold MOSFET (VTMOS), as well as analytical models for dynamic threshold control in SOI and double-gate devices, further expand its applicability in both digital and analog CMOS design (Ragini et al., 2010, Xue et al., 3 Jan 2026, Chowdhury et al., 2012).

1. Principle of Dynamic Threshold Operation

Conventional MOSFET threshold voltage ($V_{\mathrm{TH}}$) is governed by the body effect, typically expressed as:

$$V_{\mathrm{TH}}(V_{SB}) = V_{\mathrm{TH0}} + \gamma \left[ \sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F} \right]$$

where $V_{SB}$ is the source-to-body bias, $V_{\mathrm{TH0}}$ the zero-bias threshold, $\gamma$ the body-effect coefficient, and $\phi_F$ the Fermi potential.

In DTMOS, the gate and body are directly tied together. For NMOS, $V_{SB} = V_{GS}$, so $V_{\mathrm{TH}}$ dynamically falls as $V_{GS}$ increases during ON-state, decreasing the channel barrier for conduction. Conversely, when OFF ($V_G = 0$), the threshold is maximized, resulting in minimum leakage. This toggling of $$V_{\mathrm{TH}}(V_{SB}) = V_{\mathrm{TH0}} + \gamma \left[ \sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F} \right]$$0 enhances ON-current ($$V_{\mathrm{TH}}(V_{SB}) = V_{\mathrm{TH0}} + \gamma \left[ \sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F} \right]$$1) for strong switching and suppresses OFF-current ($$V_{\mathrm{TH}}(V_{SB}) = V_{\mathrm{TH0}} + \gamma \left[ \sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F} \right]$$2) for leakage control, critical for circuits operating at $$V_{\mathrm{TH}}(V_{SB}) = V_{\mathrm{TH0}} + \gamma \left[ \sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F} \right]$$3 below $$V_{\mathrm{TH}}(V_{SB}) = V_{\mathrm{TH0}} + \gamma \left[ \sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F} \right]$$4 (Ragini et al., 2010, Xue et al., 3 Jan 2026).

2. Mathematical Models for DTMOS and Variants

Dynamic threshold modulation is described quantitatively by:

• Body-effect: $$V_{\mathrm{TH}}(V_{SB}) = V_{\mathrm{TH0}} + \gamma \left[ \sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F} \right]$$5
• DTMOS case: $$V_{\mathrm{TH}}(V_{SB}) = V_{\mathrm{TH0}} + \gamma \left[ \sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F} \right]$$6, so $$V_{\mathrm{TH}}(V_{SB}) = V_{\mathrm{TH0}} + \gamma \left[ \sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F} \right]$$7 decreases with increasing $$V_{\mathrm{TH}}(V_{SB}) = V_{\mathrm{TH0}} + \gamma \left[ \sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F} \right]$$8
• Linearized approximation: $$V_{\mathrm{TH}}(V_{SB}) = V_{\mathrm{TH0}} + \gamma \left[ \sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F} \right]$$9, with empirical $V_{SB}$0

In advanced double-gate or SOI FETs, full 2-D electrostatic models are employed, as in the Flexible-FET, where the top-gate threshold voltage $V_{SB}$1 is analytically derived as a function of the bottom-gate voltage $V_{SB}$2 via solution to the 2D Poisson equation using Young’s approximation. This yields explicit relations:

$V_{SB}$3

This allows continuous threshold tuning from high to low, with the analytical solution benchmarking well with experimental and SILVACO-Atlas simulation data (Chowdhury et al., 2012).

3. Circuit Implementations: DTMOS and VTMOS Schemes

DTMOS circuits adopt a direct gate–body connection (NMOS body = gate; PMOS body = gate). DTMOS inverters, NAND, and NOR gates follow standard CMOS topologies but substitute the body-gate tie for static body bias.

VTMOS extends DTMOS by introducing a fixed DC offset ($V_{SB}$4 for NMOS, $V_{SB}$5 for PMOS) between gate and substrate:

• NMOS: $V_{SB}$6, $V_{SB}$7 V$V_{SB}$8
• PMOS: $V_{SB}$9, $V_{\mathrm{TH0}}$0 V$V_{\mathrm{TH0}}$1 This enhances static power saving by further reducing both $V_{\mathrm{TH0}}$2 and $V_{\mathrm{TH0}}$3 beyond pure DTMOS, with only incremental increase in propagation delay (Ragini et al., 2010).

Amplifier Applications: In advanced analog designs, DTMOS is utilized to boost effective transconductance ($V_{\mathrm{TH0}}$4), where the body transconductance ($V_{\mathrm{TH0}}$5) increases small-signal gain and reduces input-referred noise without additional current or increased device size. This has been demonstrated in gain-boosted flipped-voltage-follower (FVF) front ends for bioimpedance sensing (Xue et al., 3 Jan 2026).

4. Performance Analysis and Simulation Results

Digital Logic (VTMOS/DTMOS vs CMOS) (Ragini et al., 2010)

Architecture	Power Dissipation ($V_{\mathrm{TH0}}$6)	Propagation Delay (ns)	Power-Delay Product (PDP)	Supply Voltage (V)
CMOS	$V_{\mathrm{TH0}}$7	$V_{\mathrm{TH0}}$8	—	$V_{\mathrm{TH0}}$9 (subthreshold)
DTMOS (VAN=0)	Slightly > CMOS	$\gamma$0	Reduced	$\gamma$1
VTMOS (0.2 V)	$\gamma$2	$\gamma$3	Reduced by $\gamma$450%	$\gamma$5

• Power reduction: VTMOS achieves up to $\gamma$6 lower static power vs CMOS.
• Delay trade-off: Slight penalty in propagation delay with increased body offset.
• Frequency dependence: Advantage persists up to ~8 MHz; at higher frequencies, dynamic power dominates.

Analog Amplifier Front-Ends (Xue et al., 3 Jan 2026)

Configuration	Input Noise (nV/$\gamma$7)	Power ($\gamma$8W)	Bandwidth (MHz)	Closed Loop Gain (dB)
Baseline	36.6	2.5	1.44	34
DTMOS-enabled FVF	32.4	2.5	1.44	34
DTMOS + SDCM	29.8	2.5	1.44	34

• Noise performance: $\gamma$9 reduction in input-referred noise using DTMOS, up to $\phi_F$0 with added source degeneration, with no increase in static current draw.
• Input impedance: Drops from $\phi_F$1M$\phi_F$2 to $\phi_F$3M$\phi_F$4 at $\phi_F$5 kHz due to bulk-gate tie.
• Design constraints: Signal swing and body-diode forward bias must be controlled to avoid forward conduction.

5. Physical Implementation and Device Modeling

The DTMOS effect is achievable in single-gate bulk devices but is particularly compelling in SOI and double-gate structures. In Flexible-FETs, a bottom gate (JFET) modulates the potential profile in a fully-depleted channel. The top-gate threshold is controlled by the bottom gate via the solved 2D Poisson equation. Practical models derived and validated against experiment capture:

• Effect of channel doping ($\phi_F$6): Higher $\phi_F$7 increases $\phi_F$8 and reduces tunable range.
• Si film and oxide thickness ($\phi_F$9): Thicker channels or oxides increase $V_{SB} = V_{GS}$0 and weaken threshold control.
• Agreement with data: Analytical models yield threshold predictions with $V_{SB} = V_{GS}$1 mV RMS error versus experimental and TCAD simulation results (Chowdhury et al., 2012).

6. Trade-Offs, Advantages, and Practical Considerations

Advantages

• Ultra-low power operation: Enables logic and analog circuits at $V_{SB} = V_{GS}$2.
• Enhanced energy efficiency: Net reduction in leakage (OFF) and strong ON current.
• Simple implementation: Only requires dynamic body bias infrastructure, no additional active devices.
• Transconductance improvement: In analog, increases $V_{SB} = V_{GS}$3, directly lowering noise at fixed bias current.

Limitations

• Propagation delay: Increases with larger body offset in VTMOS.
• Input impedance: Bulk-gate tie doubles effective input capacitance; may constrain suitability for high-impedance sensor interfacing.
• Body-diode conduction: Device design must avoid source–body forward bias.
• Frequency limitations: Power efficiency advantage degrades at mid-to-high MHz (digital logic) as dynamic capacitive currents dominate.

7. Applications and Outlook

The DTMOS scheme is implemented in both digital sub-threshold logic and ultra-low-power analog circuits:

• Universal logic gates: VTMOS/DTMOS inverters, NAND, NOR (65 nm node, $V_{SB} = V_{GS}$4 V) for energy-constrained computation (Ragini et al., 2010).
• Bioimpedance instrumentation amplifiers: DTMOS input stages in FVF-IA architectures deliver sub-30 nV/$V_{SB} = V_{GS}$5 noise at sub-$V_{SB} = V_{GS}$6W power budgets, key for autonomous, miniaturized biosensors (Xue et al., 3 Jan 2026).
• Threshold-programmable FETs: Flexible-FETs and similar devices provide hardware-controlled $V_{SB} = V_{GS}$7 tuning for adaptive digital/analog reconfiguration, with strong alignment with simulation and measurement (Chowdhury et al., 2012).

A plausible implication is that DTMOS and VTMOS techniques will remain central to the scaling of low-power CMOS and the optimization of device-level analog front-ends in sensor and AI edge computing platforms, especially as supply voltages continue to shrink and variability control becomes critical.