TMD Nanoribbon FETs: Scaling and Quantum Transport

Updated 23 January 2026

TMD nanoribbon FETs are ultranarrow electronic devices made from transition metal dichalcogenides, offering precise electrostatic control and quantum-confined switching.
They are fabricated using advanced top-down and bottom-up nanopatterning techniques to achieve sub-30 nm ribbon widths with atomically flat edges.
Innovative gate architectures and contact engineering enable high on/off ratios, subthermal subthreshold swings, and scalability for next-generation nanoelectronics.

Transition metal dichalcogenide (TMD) nanoribbon field-effect transistors (FETs) are electronic devices that exploit the unique properties of atomically thin TMD materials structured into ultranarrow ribbon geometries to enable aggressive channel scaling, enhanced electrostatic control, and advanced integration in next-generation nanoelectronics. Key TMD compositions include MoS₂, WS₂, and WSe₂, deployed in both n- and p-type configurations. Recent research has established atomically precise ribbon patterning, high-performance gating schemes, and quantum-confined switching behavior in these FETs, constituting a major development in post-silicon logic and memory technologies.

1. Synthesis and Nanopatterning of TMD Nanoribbons

TMD nanoribbons (NRs) are fabricated by a range of top-down and bottom-up approaches, with critical emphasis on lateral dimension control, crystallographic edge precision, and compatibility with wafer-scale processes.

Vapor-phase growth is used to synthesize multiwall MoS₂ nanoribbons, typically via iodine-mediated chemical transport at ∼1060 °C, producing mono- or few-layer structures with minimal plasma exposure (Fathipour et al., 2014).
Universal mask-and-etch patterning utilizes organic needle-like crystallites (para-hexaphenyl or dihydrotetraazaheptacene) self-assembled on 2D materials (MoS₂, WS₂, WSe₂, graphene) via hot-wall epitaxy. Oxygen plasma etching then carves sub-30 nm-wide single-crystal ribbons, followed by mask lift-off, yielding edge-aligned, high-yield networks (Aslam et al., 2022).
E-beam lithography and multi-patterning (LELE), coupled with XeF₂ or Cl₂/O₂ reactive ion etching, allows channel widths down to 25 nm while anchored contact geometry improves mechanical stability and device yield (Peña et al., 12 Sep 2025, Lan et al., 20 Jan 2026).
Wafer-scale monolayer transfer is implemented via CVD/MBE growth on 2-inch substrates, enabling fabrication of dense and uniform ribbon arrays requisite for logic integration (Lan et al., 20 Jan 2026).

Edge directionality (zigzag/armchair) can be selected via organic mask chemistry; atomic flatness and crystallinity are confirmed by Raman and transmission electron microscopy (TEM), with edge roughness below 5 nm and negligible disorder.

2. Device Architectures and Electrostatic Control

TMD NR FETs have advanced from simple back-gate single-ribbon layouts to sophisticated gate-all-around (GAA) and network-based devices:

Channel geometry: Channels are patterned with widths (W_CH) as low as 25–35 nm and lengths (L_CH) from 30 to 300 nm for individual FETs (Peña et al., 12 Sep 2025, Lan et al., 20 Jan 2026). Gate-length scaling down to 30 nm has been demonstrated without loss of switching behavior.
Electrostatics: GAA architectures employ ultra-thin high-κ dielectrics (3–7.5 nm HfO₂, EOT ≈ 0.9–1.5 nm). The scale length λ (λ = √(ε_ch t_ch t_ox / ε_ox)) decreases with narrower W_CH, enhancing lateral gate control (Lan et al., 20 Jan 2026).
Edge-field enhancement: TCAD simulations and PL mapping show edge electric fields up to 1.5× greater than the center, facilitating additional carrier accumulation without deleterious scattering (Lan et al., 20 Jan 2026).
In-network FETs, ribbon junctions are atomically continuous with negligible node resistance, ensuring parallel conduction (Aslam et al., 2022).

Gate-tunable architectures support both n- and p-type operation, compatible with complementary FET (CFET) logic design.

3. Electronic Transport, Modeling, and Performance Benchmarks

Transport in TMD NR FETs is governed by both classical drift-diffusion and pronounced quantum phenomena at sub-10 nm length scales.

Long-channel drift-diffusion regime: The drain current in the linear regime is given by

$I_D \simeq \mu C_{\mathrm{ox}}\frac{W_\mathrm{CH}}{L_\mathrm{CH}} \left[(V_{GS} - V_{TH})V_{DS} - \tfrac{1}{2}V_{DS}^2\right]$

where $C_{\mathrm{ox}} = \varepsilon_{\mathrm{ox}}/t_{\mathrm{ox}}$ and $\mu$ is the field-effect mobility (Lan et al., 20 Jan 2026).

Subthreshold swing (SS):

$SS = (\ln 10) k_BT/q \times n$

where $n=1 + C_{\mathrm{dep}}/C_{\mathrm{ox}}$ and $C_{\mathrm{dep}}$ is the depletion capacitance. Width scaling enhances effective $C_{\mathrm{ox}}$ , reducing $n$ and thereby $SS$ (Lan et al., 20 Jan 2026).

Quantum transport:

At lengths $L_{nh} \leq 9$  nm, quantum tunneling dominates OFF-state leakage. The NEGF-DFT formalism reveals a transmission coefficient $T(E)$ exhibiting ultra-steep energy dependence; for 3 nm channels, subthreshold swing falls below the classical Boltzmann limit, with SS ≈ 58–62 mV/dec (normalized by gate coupling factor $\alpha_{\mathrm{in}}$ ) (Chen et al., 4 Aug 2025).

Contact resistance ( $R_c$ ): Contact performance is a major bottleneck. State-of-the-art values include $R_c=$ 352 Ω·μm (MoS₂, 35 nm) and 675 Ω·μm (WS₂/Ni-Au, 50 nm). Quantum-limited projections suggest $R_{c,\min} \sim 0.026$  kΩ·μm at $n_s \sim 10^{13}$  cm⁻² (Fathipour et al., 2014, Peña et al., 12 Sep 2025, Lan et al., 20 Jan 2026).

4. Key Device Performance Metrics

The following table collates representative figures of merit for monolayer TMD nanoribbon FETs:

Material	$W_{CH}$ (nm)	$L_{CH}$ (nm)	$I_{on}$ ( $\mu$ A/ $\mu$ m)	SS (mV/dec)	$V_{TH}$ (V)	$\mu_{FE}$ (cm²/V·s)	$R_c$ (Ω·μm)
MoS₂	35	55	727	94	0.2	~40	352
MoS₂ (ultra)	80	30	600	74	—	—	—
WS₂	30	180	200	86	+0.3	—	—
WSe₂ (p)	80	380	400	80	–0.4	—	—
MoS₂ NRN [77K]	20	5000	800	250	+40 $^*$	85	—

$^*$ Gate shift post O₂ RIE, consistent with edge-induced p-type doping.

In addition:

On/off ratios: $I_{on}/I_{off}$ up to $10^8$ for MoS₂ and $10^5$ – $10^6$ for WS₂/WSe₂ (Aslam et al., 2022, Lan et al., 20 Jan 2026).
Mobility scaling: $\mu_{FE}$ preserved down to 10–20 nm width, with no catastrophic band-transport roll-off observed for $W_{ribbon} \gtrsim 10$ nm (Aslam et al., 2022, Peña et al., 12 Sep 2025).
Threshold voltage: Edges introduce positive $V_{TH}$ shift due to oxygen termination (up to $+0.25$ – $+0.4$ V) (Aslam et al., 2022, Lan et al., 20 Jan 2026).

5. Quantum-Classical Transport Crossover and Scaling Limits

As channel length and width are reduced into the single-nanometer regime, transport shifts from thermionic emission to quantum tunneling. This crossover is quantitatively described by two critical temperatures:

$T_c$ : Marks transition where d $J_{OFF}$ /d $T$ = 0; below $T_c$ , quantum leakage dominates, above $T_c$ , thermionic emission dominates.
$T_t$ : The temperature above which classical SS saturates.

For $L_{nh} = 3$ nm WSe₂ devices, pronounced quantum tunneling persists up to $T \gtrsim 500$ K, with the observed SS below the Boltzmann “tyranny” limit of 59.5 mV/dec, enabled by steep $T(E)$ (Chen et al., 4 Aug 2025). These findings indicate that ultra-scaled TMD NR FETs can, in principle, surpass classical energy efficiency constraints.

Emergent design guidelines:

Maximizing gate-channel coupling (high-κ, minimal EOT, double-gate) enables subthermal SS.
Edge-contact engineering (e.g., Pt-WSe₂) is essential to minimize series resistance in the tunneling regime.

6. Integration, Variability, and Applications

Large-area and device-to-device uniformity are achieved by combining CVD/MBE TMD monolayer growth with scalable mask-and-etch or LELE patterning.

Variability: Device threshold voltage and SS are tightly distributed (e.g., σ( $V_{TH}$ ) ≈ 0.1 V, σ(SS) ≈ 20 mV/dec for 47 devices) (Lan et al., 20 Jan 2026).
Contact pitch and logic density: Contact pitch of 60 nm is achievable in arrays, supporting high-density nanosheet logic (Lan et al., 20 Jan 2026).
Plasmonics and sensing: Edge-selective Ag decoration enables plasmonic and SERS functionality, while atomically sharp edges facilitate chemical detection and catalysis (Aslam et al., 2022).
Complementary logic: By combining MoS₂/WS₂ n-FETs with WSe₂ p-FETs in GAA geometry, full complementary (CMOS-like) logic circuits are feasible purely from TMD monolayers (Lan et al., 20 Jan 2026).

Remaining challenges include achieving uniform organic mask growth at wafer scale, integration of sub-nm EOT high-κ dielectrics, and scalable low-RES edge contacts for sub-10 nm ribbons.

7. Outlook and Prospective Directions

Recent results demonstrate that TMD NR FETs down to 25–35 nm width and 30 nm gate length achieve $I_{on}\gtrsim600\,\mu$ A/ $\mu$ m, $SS\approx70$ –$94$ mV/dec, and excellent device-to-device uniformity (Peña et al., 12 Sep 2025, Lan et al., 20 Jan 2026). For $L_{CH}\leq 10$ nm, full quantum treatment predicts that switching steepness can exceed the Boltzmann limit, enabling disruptive energy efficiency gains (Chen et al., 4 Aug 2025).

Further directions focus on:

Thinning EOT $<0.5$ nm using stack-engineered 2D/high-κ dielectrics.
Dual-gate and GAA topologies for optimal electrostatic control.
Phase-engineered/semimetal contacts for Rc approaching the quantum minimum.
Atomically precise ribbon edge engineering for ballistic transport.
Large-area transfer and patterning for circuits and memory arrays.

Monolayer TMD nanoribbon FETs thus establish a fundamentally viable, scalable, and complementary approach for post-silicon ultra-scaled logic, with a growing body of atomistic simulation and experimental research delineating both the classical and quantum operational regimes (Fathipour et al., 2014, Aslam et al., 2022, Peña et al., 12 Sep 2025, Chen et al., 4 Aug 2025, Lan et al., 20 Jan 2026).