FET-Based Minimal Neuron Analysis

• FET-based minimal neurons are energy-efficient neuromorphic devices that emulate essential neuronal dynamics using minimal FET circuitry and binary control.
• They utilize various FET technologies—such as FeFETs, BTBT devices, and S-FEDs—to achieve precise analog integration and reliable spiking behavior.
• Advanced control strategies, like bang-bang control and capacity optimization, underpin robust design and scalability for brain-inspired computing systems.

A Field-Effect Transistor (FET)-based minimal neuron is a neuromorphic circuit or device leveraging FETs or their derivatives (e.g., ferroelectric FETs, tunnel junction FETs, Schottky-barrier FETs) to emulate essential neuronal dynamics—typically integrating, thresholding, and firing—using a minimal set of components. The notion of "minimal" refers both to component count and functional abstraction: circuits abandon biological complexity to focus on scalable, energy-efficient hardware realizations of spiking or analog neurons, often suited for large-scale neuromorphic systems or deep neural network accelerators.

1. Unified Mathematical Framework and Control Perspective

FET-based minimal neurons are typically described in terms of affine dynamical systems:

$$\frac{dx}{dt} = f_0(x) + u(t) f_1(x), \quad x(0) = x_e, \quad x(t_n) \in M_s$$

where $x$ is a vector (often describing voltages at nodes emulating membrane potential), $u(t)$ is the control input (e.g., gate voltage, current pulse), $f_0(x)$ models passive response, and $f_1(x)$ captures the effect of applied control. This mirrors conductance-based neuron models with ion channels replaced by FET circuits (Renault et al., 2016).

Optimal spiking, particularly "minimal time to spike," is addressed using geometric optimal control theory and the Pontryagin Maximum Principle (PMP). The cost function:

$$T \rightarrow \min \quad \text{s.t.} \ x_1(T) = V_s, \ x(0) = x_e$$

is formulated with Hamiltonian

$$\mathcal{H}(x, p, u) = p \cdot f_0(x) + u[p \cdot f_1(x)] + p^0$$

and switching function

$\varphi(t) = p(t) \cdot f_1(x(t))$

Yielding bang-bang controls:

$$u^*(t) = u_{\max} \cdot \mathbb{1}\{\varphi(t) > 0\}$$

The absence of singular extremals (intervals with $\varphi(t) \equiv 0$) implies devices need only two control states—fully on or off—greatly simplifying digital FET neuron design.

2. Device Technologies and Physical Principles

Multiple FET technologies support minimal neuron realization:

• Ferroelectric FETs (FeFETs): Leverage HfO₂ or similar ferroelectric stack for analog or multi-bit nonvolatile weight storage. Programming is achieved via gate voltage pulses, producing symmetric, continuous resistance changes and high endurance (Halter et al., 2020, Obradovic et al., 2017). BEOL compatibility enables dense integration atop logic.
• Band-to-Band Tunneling (BTBT) Neurons: Use PD-SOI MOSFETs where BTBT at the drain-body junction stores holes (integration function); sub-threshold circuits detect threshold crossing, triggering reset/firing (Chavan et al., 2019). Achieves $\sim$3.2 fJ/spike and area densities $\sim$0.8 μm²/neuron.
• Bipolar Impact Ionization MOSFETs: L-BIMOS design leverages an L-shaped gate to crowd electric field, enhancing impact ionization and providing GHz spiking ($V_B$ = 1.68 V, $V_{th}$ = 0.2 V, 0.18 pJ/spike) (Kamal et al., 2019). Parasitic BJT action introduces positive feedback for sharp spiking.
• Schottky-Barrier FETs: Employ polycrystalline Si channels and Ni/Pt contacts to yield ultra-low conduction currents (nA/pA), supporting biologically realistic firing rates and minimized static power (Patil et al., 2023).
• Ferroelectric Tunnel Junctions (FTJs): Facilitate analog integration through gradual polarization switching—spiking can be electrically tuned via pulse parameters. Hybrid FTJ-CMOS architectures achieve energy-efficient asynchronous event processing for edge systems (Gibertini et al., 2022).
• Nanoscale Side-contacted Field Effect Diodes (S-FEDs): Offer dual-gate configuration with high on/off ratio and tunable thresholds (0.8–1.4 V), facilitating 0.964 fJ/spike and robust operation across PVT conditions (Motaman et al., 17 Dec 2024).

3. Circuit Methodologies and Dynamics

Minimal neuron circuits typically instantiate variations of integrate-and-fire (IF) or resonator models.

• Integrate-and-Fire (IF): Synaptic current charges a capacitor through the FET or derivative device until a threshold is reached; a spike ensues, and reset is performed by dedicated switches or control elements. Key equations trace to simple RC networks with FET modulated conductance.
• Resonator-Type Circuits: In more biologically plausible designs (INa,p+IK model emulation), RC networks and negative differential resistance (NNDR) blocks (often built from paired MOSFETs or memristors) capture sodium/potassium dynamics and Hopf bifurcation transitions to spiking (Nabil et al., 3 Jun 2025).

Bang-bang control strategies (binary gating) are optimal in the minimal time spiking problem, supporting robust and energy-efficient design (Renault et al., 2016).

4. Synaptic and Dendritic Integration

Recent FET devices support more sophisticated synaptic/dendritic computation:

• Multi-bit and Analog Weight Cells: FeFET-based weight cells in crossbar arrays enable in-memory Multiply-and-Accumulate (MAC), combining digital nonvolatile weight programming with analog current summation (Obradovic et al., 2017). Weight tuning is achieved by individually programming FeFET states.
• Tripartite Synapse and Dendritic Gain Modulation: DG-FeFETs employ ferroelectric and conventional gates to allow dynamic gain modulation, exacting analogies to astrocyte and dendrite functions in biological systems. The back gate enables real-time linear adjustment of synaptic weights for self-repair or homeostasis (Jiang et al., 20 Apr 2025).
• Dendritic Nonlinearity: Multi-gate FeFET neurons integrate diverse synaptic inputs on different "dendritic" branches with ferroelectric domains, nonlinearly summing branch outputs onto a shared floating gate for final somatic output (Islam et al., 2 May 2025).

Analytical models demonstrate improved computational capacity and reduced parameter requirements in networks using such dendritic architectures.

5. Information Theory and Capacity Optimization

FET-based minimal neurons can be analyzed in the framework of information theory, guiding signal fidelity and coding efficiency (Kuscu et al., 2016):

• Capacity Expressions: For bioFET-type neurons, channel capacity is given by:

$$C = \frac{1}{2} \log_2 \frac{N_r}{2\pi e} + \log_2 \left[ \sin^{-1}\left(L\frac{N_{tx}^{max} - k_{-1}/\alpha_{ch}}{N_{tx}^{max} + k_{-1}/\alpha_{ch}}\right) - \sin^{-1}\left(L\frac{N_{tx}^{min} - k_{-1}/\alpha_{ch}}{N_{tx}^{min} - k_{-1}/\alpha_{ch}}\right)\right]$$

with $L$ scaling with FET transconductance, ligand-induced potential, and noise.

• Capacity-achieving Input Distribution:

$$f_{N_{tx}^*}(x) = \frac{1}{K\,\sigma_{I_{rx}}(x)\,(\alpha_{ch}\,k_1\,x + k_{-1})^2}$$

Guides optimal signal distribution and hardware design for maximum information transfer.

6. Performance Metrics, Robustness, and Scaling

Key performance metrics and robustness evaluations reported include:

Device/Circuit Type	Area/Neuron	Energy/Spike	Firing Frequency	Robustness/Integration
PD-SOI BTBT MOSFET	0.8 μm²	3.22 fJ	sub-MHz	10x area, 10⁴x energy improvement
L-BIMOS	—	0.18 pJ	GHz	194x energy vs PD-SOI, CMOS compat.
S-FED IF neuron	—	0.964 fJ	20 MHz	<7% spike amp. over PVT variations
FeFET weight cell	—	—	—	4–bit linearity, BEOL integration

Devices are generally compatible with CMOS flows (PD-SOI, BEOL FeFETs, integration atop standard logic), supporting scaling to large arrays and allowing process-voltage-temperature tolerant neuromorphic hardware.

7. Advanced Modeling and Future Directions

Sophisticated analytical models cover device physics, circuit behavior, and learning-system performance:

• Compact Tri-gate FeFET Models: Efficiently capture transfer characteristics including field-dependent mobility degradation, polarization switching, and series resistance; enable scalable simulation for network training (Lu et al., 2020).
• Stochastic Dendritic Models: Analytical frameworks for voltage upcrossing rate with distributed synaptic inputs inform the design of FET-based spatially extended neurons and anticipate high-frequency response preservation even under multiple low-pass filters (Gowers et al., 2023).

Momentum continues toward minimal, modular, robust neuron designs supporting complex brain-like operations—e.g., self-repair, dendritic gain modulation, event-driven learning—enabled by flexible FET device technologies and supported by rigorous control and system theoretic analysis.

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FET-based minimal neurons thus combine the formal analytic core of conductance-based neural models with the practical demands of low-power, high-density integrated hardware, leveraging device, circuit, and system-level innovations for scalable, efficient neuromorphic computing. Experimental and theoretical results across recent literature establish design strategies ranging from bang-bang circuit control and device-level optimization, through capacity-based signal processing approaches, to advanced emulations of dendritic and astrocytic dynamics, collectively driving progress in brain-inspired hardware systems.