DR-DAQP: Multi-Domain DAQ & Optimization

• DR-DAQP is an acronym used in distinct research domains, defining a dark-matter triggerless data-acquisition pipeline, a precision low-noise DAQ system, and a hybrid optimization solver.
• The dark matter detector implementation features continuous sampling, online waveform reduction, and sub-500 ps synchronisation across 48 CAEN VX2745 digitisers.
• In precision measurement and optimization, DR-DAQP achieves ultra-high dynamic range, low-noise performance, and active-set acceleration with finite termination under strict conditions.

DR-DAQP is an acronym that appears in recent technical literature in three distinct senses. In detector instrumentation, it denotes the DarkSide-20k DR-DAQ Pipeline, a fully continuous, triggerless data-acquisition and online reduction system for a liquid-argon dark-matter experiment (Acerbi et al., 3 Apr 2026). In precision measurement instrumentation, the supplied technical summary uses DR-DAQP to designate a Dynamic Range Data Acquisition Quality Protocol implemented by a custom 24-bit, eight-channel system for a solid-state electron electric dipole moment experiment (Kim et al., 2011). In numerical optimization, \texttt{DR-DAQP} is an open-source hybrid Douglas-Rachford and active-set solver for strongly monotone affine variational inequalities (Arnström et al., 2 Apr 2026). The acronym therefore has no single field-independent meaning; its interpretation is determined by experimental or mathematical context.

1. Terminological scope

In the supplied literature, DR-DAQP is not a unique object but a shared acronym used across unrelated research programs.

Usage of DR-DAQP	Domain	Defining description
DarkSide-20k DR-DAQ Pipeline	Dark-matter detector DAQ	Continuous, triggerless digitisation and online reduction over 48 CAEN VX2745 digitisers
Dynamic Range Data Acquisition Quality Protocol	Precision low-noise DAQ	24-bit, eight-channel, galvanically isolated DAQ with fiber-optic links, battery power, and RF shielding
\texttt{DR-DAQP} solver	Affine variational inequalities	Douglas-Rachford operator splitting with active-set acceleration, warm-starting, and pre-factorization

This terminological divergence is technically significant. Two usages concern physical data acquisition, but they address very different operating regimes: one is a large-scale waveform pipeline for a dual-phase time projection chamber with veto subsystems, and the other is a low-bandwidth, ultra-high-dynamic-range synchronized measurement system. The third usage is not a DAQ architecture at all, but a solver for affine variational inequalities with finite-termination guarantees under additional regularity assumptions (Acerbi et al., 3 Apr 2026, Kim et al., 2011, Arnström et al., 2 Apr 2026).

2. DR-DAQP as the DarkSide-20k online acquisition and reduction pipeline

In DarkSide-20k, DR-DAQP denotes the detector’s end-to-end data-acquisition and reduction chain. DarkSide-20k is a WIMP search experiment using liquid argon as a target, designed to perform a background-free search for dark matter with unprecedented sensitivity, and is under construction at INFN Laboratori Nazionali del Gran Sasso. The detector comprises a dual-phase Time Projection Chamber complemented with external veto systems and is equipped with a total of 2720 SiPM-based readout channels. The DR-DAQ Pipeline is built around 48 CAEN VX2745 waveform digitisers arranged in four crates, with 12 modules per crate; each module provides 64 channels of 16-bit, 125 MS/s ADCs with 4 Vpp input range and 20 MHz analogue bandwidth (Acerbi et al., 3 Apr 2026).

The hardware stack couples commercial digitiser modules to custom timing and command distribution. An OpenFPGA framework loads custom firmware into the Xilinx ZU19EG SoC on each module, implementing a 64-tap FIR, dynamic acquisition windows, zero-length encoding, and sub-segment splitting. Timing is disciplined by a Stanford Research PRS10 rubidium oscillator using the LNGS 1 Hz GPS-based sync packet through a custom Input–Output GPS Clock board. A single Global Data Manager board decodes absolute time, corrects for fibre-optic delays, and distributes phase-aligned 125 MHz and control packets over eight optical 2.5 Gbps links to Crate Data Manager boards. Each CDM fans out the recovered clock, $\Delta$Time-Slice-Marker and busy/veto commands to the 12 digitisers in its crate. Phase alignment across all 48 modules has been measured to better than 500 ps.

The acquisition mode is fully continuous and triggerless. Sampling proceeds at $f_{\mathrm{clk}}=125\ \mathrm{MHz}$, with 16-bit depth, single-photo-electron detection efficiency $\ge 90\%$ at the digitiser output, and FEP hit-finding efficiencies up to 99% for single-PE signals. Each channel applies an on-board 64-tap, 16-bit-coefficient FIR filter running at an internal 250 MHz DSP clock with effective 62.5 MS/s decimation. A Dynamic Acquisition Window algorithm opens a gated segment when the filtered waveform crosses a threshold, includes pre- and post-trigger buffers, and closes when the signal returns below a secondary threshold. Long segments are split into sub-segments on the fly to avoid FPGA buffer overflows and are reassembled at the FEP.

The internal buffering path is explicitly structured. Metadata are written to a PARAMS FIFO of $512 \times 64$-bit words, waveform payloads to a WAVE FIFO of $4096 \times 64$-bit words, and both feed a shared Sort-Merge buffer limited in current firmware to approximately five times the ADC rate before staging in 2 GiB of DDR4 memory for ARM CPU readout. The theoretical raw data throughput per board is

$$R_{\mathrm{raw}} = N_{\mathrm{ch}} \times f_{\mathrm{clk}} \times b_{\mathrm{bits}} = 64 \times 125\times 10^6 \times 16 \simeq 128\ \mathrm{Gb/s}\ (16\ \mathrm{GB/s}),$$

but practical operation depends on on-board reduction. Each 10 GbE link sustains at least 250 MB/s per board after on-board filtering, while Monte Carlo-based estimates at 400 Hz dark rate predict about 60 MB/s per board.

The software pipeline consists of Front End Processor nodes, Time Slice Processors, a Pool Manager, and a Merger. Each FEP reads two digitiser modules over 10 GbE. Per-segment threads subtract a baseline from pre-trigger samples, equalise channel gains, and then apply an infinite-response Auto-Recursive exponential filter followed by a matched-filter hit finder. Hits are declared when the filtered waveform exceeds threshold and satisfies a minimum charge-to-prominence ratio. For each hit, time, charge, and prominence are recorded; full waveforms are discarded except for on-demand debugging. The FEP also forms Zero-Length Encoding sums over the Time Slice duration, producing top and bottom summed waveforms, time-sorts segments by the 62.5 MHz TSM counter, and builds TS packets. The Pool Manager on the MIDAS supervisor assigns TS packets round-robin to idle TSPs via ZeroMQ. Each TSP collects TS fragments from all 24 FEP modules, merges top and bottom sums, collates all extracted hits across the full detector, recovers boundary events by duplicating an overlap region equal to the maximum TPC electron drift time, $O(2\ \mathrm{ms})$, and can further classify a TS as WIMP-ROI S1, calibration S1, isolated low-energy S2, Inner/Outer Veto pulses, or anomalous bursts such as supernova neutrino candidates. The Merger node then receives completed TSs over raw TCP/IP, sorts by TS_ID, concatenates them into a continuous stream, and ships data to the external storage gateway or CNAF while retaining a rolling $\sim 100\ \mathrm{TiB}$ local buffer, corresponding to about one week, for fault recovery.

Validation was carried out at TRIUMF at the Quadrant scale, corresponding to one quarter of the final 48-board system. In a worst-case stress test, 12 digitisers, or 768 channels, were pulsed simultaneously at 2 kHz with 8 $\mu$s waveforms. Each digitiser sustained 250 MB/s to the FEP, limited by FEP CPU at at most 60% usage per thread, and the FEP-to-TSP rate was about 8 MB/s. Long-term operation exceeded 300 hours with zero data loss and no FIFO overflows, aided by segment splitting and optional firmware compression using 2$\times$ lossless Huffman-delta coding. During normal running, the system reduces a raw input of roughly 3 GB/s, corresponding to 48 boards at 60 MB/s expected each, to about 60 MB/s on disk, with $f_{\mathrm{clk}}=125\ \mathrm{MHz}$0; calibration modes rise to less than 200 MB/s. Throughput protection is enforced by a busy/veto handshake propagating a global busy whenever any WAVE FIFO ALMOST FULL condition asserts, with typical deadtime below 0.5% under worst-case rates.

3. DR-DAQP as a dynamic-range quality protocol for ultra-low-noise DAQ

In the supplied technical summary of Kim et al., DR-DAQP designates a Dynamic Range Data Acquisition Quality Protocol implemented by a custom high-precision DAQ system for a solid-state electron EDM experiment. The system architecture consists of one Spartan-3E FPGA-based master board and eight identical ADC boards. The master board contains 10 MHz and 14.7456 MHz oscillators, a Lantronix XPort Ethernet-RS232 module, eight TOSLink optical downlinks and uplinks, an FPGA-embedded FIFO for time-stamped multiplexed samples, a TTL trigger input, one general-purpose output, and an optional DAC optical interface. Each ADC board contains a low-pass and anti-aliasing analog front end, unity-gain LT1007 buffers, 4:1 attenuation from $f_{\mathrm{clk}}=125\ \mathrm{MHz}$1 to $f_{\mathrm{clk}}=125\ \mathrm{MHz}$2, a CMRR adjustment potentiometer, an LTC2440 24-bit $f_{\mathrm{clk}}=125\ \mathrm{MHz}$3 ADC, a CPLD with PLL for clock recovery, dual TOSLink modules, and battery-derived supply rails inside a $f_{\mathrm{clk}}=125\ \mathrm{MHz}$4 RF-shielded enclosure (Kim et al., 2011).

The defining architectural feature is galvanic isolation. All digital control and data lines between the master and each ADC board are carried over fiber-optic TOSLink links, eliminating ground loops and preventing common-ground EMI coupling. Each ADC board is powered by a single 12 V DC car battery, with on-board regulators generating $f_{\mathrm{clk}}=125\ \mathrm{MHz}$5 and $f_{\mathrm{clk}}=125\ \mathrm{MHz}$6 rails. The enclosure is a heavy-duty metal box, and the battery-defined zero reference is tied to the chassis. The supplied summary attributes sub-$f_{\mathrm{clk}}=125\ \mathrm{MHz}$7V noise suppression to this combination of isolation, battery powering, and shielding.

The protocol emphasizes dynamic range, effective resolution, noise, and cross-talk. The full-scale range is $f_{\mathrm{clk}}=125\ \mathrm{MHz}$8 peak-to-peak, or $f_{\mathrm{clk}}=125\ \mathrm{MHz}$9. At OSR$\ge 90\%$0, the measured rms noise is $\ge 90\%$1, yielding

$\ge 90\%$2

and, for the cited measurement, approximately 146 dB. The summary reports a specified ENOB of 24.4 bits from the LTC2440 data sheet and a measured ENOB of 23.8 bits. Measured ENOB values are also listed as 20.4 at OSR 128, 21.6 at OSR 512, 22.6 at OSR 2048, 23.8 at OSR 16384, and 24.1 at OSR 32768.

Noise characterization is correspondingly stringent. The input-referred noise PSD is reported as flat above 0.1 Hz, with no discernible 60 Hz pickup or harmonics, and the noise floor at 1 Hz is stated as approximately $\ge 90\%$3. Cross-talk testing applies a 1.5 Hz, 19 Vpp square wave to one aggressor channel at 95% of full scale while terminating the adjacent victim channel, recording both synchronously at OSR 512 and averaging more than 41k cycles on the victim. No square wave is observed on the victim channel, and the PSD shows no peak at 1.5 Hz or its harmonics, leading to a reported cross-talk below 191 dB. Frequency characterization combines a front-end anti-aliasing filter with the $\ge 90\%$4 digital filter to provide more than 100 dB attenuation above Nyquist, and long FFTs of 10k samples show no discrete spurs or non-Gaussian features.

The acquisition protocol is triggered simultaneous sampling rather than continuous triggerless operation. On every rising edge of an external TTL trigger, the master board broadcasts an OSR word to all ADC boards, and each ADC digitizes at the same instant. The maximum aggregate throughput is eight channels at OSR 64, giving 2.9 kHz per channel, limited by the XPort baud rate. Typical EDM operation uses OSR 256, corresponding to 976 Hz and ENOB 21.1. Digital filtering is supplied by the on-chip $\ge 90\%$5 modulator, which provides 384$\ge 90\%$6 oversampling at OSR 32768 and internal digital filter roll-off greater than 120 dB/decade, while external 2-pole RC anti-aliasing networks with corner frequency near $\ge 90\%$7 precede the ADC inputs. Data packets consist of 24-bit samples plus 32-bit timestamps per trigger, i.e. 56 bits per channel and 448 bits per eight-channel trigger, buffered in the FPGA FIFO and retrieved asynchronously by the DAQ computer in MATLAB via TCP/IP.

Performance targets in the summary are explicit. A noise target below $\ge 90\%$8 was achieved as $\ge 90\%$9 at 15 Hz bandwidth, corresponding to dynamic range greater than 146 dB. A cross-talk target below $512 \times 64$0 was achieved as below $512 \times 64$1. Settling time was measured as 200 ms for 22-bit accuracy and 51 s for full 24-bit accuracy. Linearity is reported as $512 \times 64$2 over $512 \times 64$3 and $512 \times 64$4 over $512 \times 64$5, with total harmonic distortion below $512 \times 64$6. The summary also notes negligible drift and effectively infinite PSRR for a test with 1.5 Hz ripple superimposed on the 12 V battery. Its limitations are correspondingly narrow: full 24-bit settling is too slow for rapid step changes, battery replacement and monitoring could be automated, and future work may integrate temperature sensors and digital calibration.

4. \texttt{DR-DAQP} as a solver for affine variational inequalities

In optimization, \texttt{DR-DAQP} is a hybrid Douglas-Rachford operator-splitting and active-set method for strongly monotone affine variational inequalities. The problem is to find $512 \times 64$7 such that

$512 \times 64$8

for an affine mapping $512 \times 64$9 and a polyhedral feasible set $4096 \times 64$0. The equivalent complementarity form introduces multipliers $4096 \times 64$1 satisfying

$4096 \times 64$2

The solver assumes strong monotonicity, namely the existence of $4096 \times 64$3 such that

$4096 \times 64$4

equivalently $4096 \times 64$5, which ensures uniqueness of $4096 \times 64$6 (Arnström et al., 2 Apr 2026).

The baseline iteration is Douglas-Rachford splitting with $4096 \times 64$7, the normal cone to $4096 \times 64$8, and $4096 \times 64$9. With $$R_{\mathrm{raw}} = N_{\mathrm{ch}} \times f_{\mathrm{clk}} \times b_{\mathrm{bits}} = 64 \times 125\times 10^6 \times 16 \simeq 128\ \mathrm{Gb/s}\ (16\ \mathrm{GB/s}),$$0 and $$R_{\mathrm{raw}} = N_{\mathrm{ch}} \times f_{\mathrm{clk}} \times b_{\mathrm{bits}} = 64 \times 125\times 10^6 \times 16 \simeq 128\ \mathrm{Gb/s}\ (16\ \mathrm{GB/s}),$$1, the classical DR operator is

$$R_{\mathrm{raw}} = N_{\mathrm{ch}} \times f_{\mathrm{clk}} \times b_{\mathrm{bits}} = 64 \times 125\times 10^6 \times 16 \simeq 128\ \mathrm{Gb/s}\ (16\ \mathrm{GB/s}),$$2

The iteration is written as

$$R_{\mathrm{raw}} = N_{\mathrm{ch}} \times f_{\mathrm{clk}} \times b_{\mathrm{bits}} = 64 \times 125\times 10^6 \times 16 \simeq 128\ \mathrm{Gb/s}\ (16\ \mathrm{GB/s}),$$3

$$R_{\mathrm{raw}} = N_{\mathrm{ch}} \times f_{\mathrm{clk}} \times b_{\mathrm{bits}} = 64 \times 125\times 10^6 \times 16 \simeq 128\ \mathrm{Gb/s}\ (16\ \mathrm{GB/s}),$$4

In the AVI-tailored form, a regularization $$R_{\mathrm{raw}} = N_{\mathrm{ch}} \times f_{\mathrm{clk}} \times b_{\mathrm{bits}} = 64 \times 125\times 10^6 \times 16 \simeq 128\ \mathrm{Gb/s}\ (16\ \mathrm{GB/s}),$$5 is introduced, with $$R_{\mathrm{raw}} = N_{\mathrm{ch}} \times f_{\mathrm{clk}} \times b_{\mathrm{bits}} = 64 \times 125\times 10^6 \times 16 \simeq 128\ \mathrm{Gb/s}\ (16\ \mathrm{GB/s}),$$6, $$R_{\mathrm{raw}} = N_{\mathrm{ch}} \times f_{\mathrm{clk}} \times b_{\mathrm{bits}} = 64 \times 125\times 10^6 \times 16 \simeq 128\ \mathrm{Gb/s}\ (16\ \mathrm{GB/s}),$$7, and $$R_{\mathrm{raw}} = N_{\mathrm{ch}} \times f_{\mathrm{clk}} \times b_{\mathrm{bits}} = 64 \times 125\times 10^6 \times 16 \simeq 128\ \mathrm{Gb/s}\ (16\ \mathrm{GB/s}),$$8. Each DR iteration then reduces to solving the strongly convex quadratic program

$$R_{\mathrm{raw}} = N_{\mathrm{ch}} \times f_{\mathrm{clk}} \times b_{\mathrm{bits}} = 64 \times 125\times 10^6 \times 16 \simeq 128\ \mathrm{Gb/s}\ (16\ \mathrm{GB/s}),$$9

followed by the update

$O(2\ \mathrm{ms})$0

The distinctive feature is active-set acceleration. After solving the QP subproblem, the method records the active set $O(2\ \mathrm{ms})$1. If $O(2\ \mathrm{ms})$2, the repeated active set is treated as a candidate for the true active set $O(2\ \mathrm{ms})$3. The method then solves the linear KKT system

$O(2\ \mathrm{ms})$4

If the resulting $O(2\ \mathrm{ms})$5 satisfies $O(2\ \mathrm{ms})$6 and $O(2\ \mathrm{ms})$7, the KKT conditions hold and the exact AVI solution has been found. If feasibility fails, the algorithm may still attempt a Newton-type correction: it solves the QP again at $O(2\ \mathrm{ms})$8, computes a candidate $O(2\ \mathrm{ms})$9, and accepts the step only if the natural residual $\sim 100\ \mathrm{TiB}$0 decreases strictly below any previous accepted step. Because only finitely many active-set combinations exist, the method eventually terminates exactly in finite steps once $\sim 100\ \mathrm{TiB}$1, provided LICQ and strict complementarity hold on the true active set.

The implementation is designed for repeated linear-algebra reuse. Since the Hessian $\sim 100\ \mathrm{TiB}$2 and constraint matrix $\sim 100\ \mathrm{TiB}$3 remain fixed across DR iterations, the method computes an $\sim 100\ \mathrm{TiB}$4 factorization of $\sim 100\ \mathrm{TiB}$5 once, at $\sim 100\ \mathrm{TiB}$6 cost, and thereafter reuses it with back-substitutions costing $\sim 100\ \mathrm{TiB}$7. The underlying active-set QP solver DAQP also maintains and updates an $\sim 100\ \mathrm{TiB}$8 factorization of the currently active KKT system, warm-starting from the previous active set. The reported overall per-iteration cost is dominated by one pre-factored QP solve, approximately $\sim 100\ \mathrm{TiB}$9, plus one linear solve whose cubic cost occurs once and whose subsequent evaluations are $\mu$0.

The stated convergence results are twofold. Under strong monotonicity, the generated sequence $\mu$1 converges linearly to the unique solution $\mu$2; the paper states the existence of a contraction factor $\mu$3 such that $\mu$4. Under the additional assumptions of LICQ on $\mu$5 and strict complementarity $\mu$6 for all $\mu$7, the method identifies the true active set in finitely many iterations and terminates with the exact solution.

The numerical results are explicit. On random AVIs with $\mu$8 and $\mu$9, median solve times over 100 runs are 0.018 s, 0.032 s, 0.055 s, and 0.081 s for \texttt{DR-DAQP}, compared with 0.28 s, 0.65 s, 1.03 s, and 1.55 s for \texttt{PATH}, and 1.2 s, 3.8 s, 7.4 s, and 12.0 s for a lifted QP solved with Clarabel. The paper describes \texttt{DR-DAQP} as roughly one order of magnitude faster in median, and up to two orders in the worst case. On a game-theoretic MPC benchmark, it attains $\times$0 s per step through the Julia interface, while the mixed-integer solver \texttt{NashOpt} requires approximately 0.02–0.1 s per step. The implementation is available as a high-performance C core with Julia, MATLAB, and Python interfaces, and the stated default parameters are $\times$1, accuracy tolerance $\times$2, and an active-set stability requirement of five consecutive DR steps before a Newton-step attempt.

5. Cross-domain comparison

The three meanings of DR-DAQP share an acronym but differ in mathematical object, operating mode, and evaluation criterion (Acerbi et al., 3 Apr 2026, Kim et al., 2011, Arnström et al., 2 Apr 2026).

The DarkSide-20k DR-DAQ Pipeline is a large-scale online waveform system. Its principal objects are waveform segments, Time Slices, extracted hits, and detector-wide summaries. The critical constraints are synchronisation across 48 digitisers, sustained Ethernet throughput, online reduction, and deadtime control. Its output is a reduced, time-ordered data stream suitable for storage and offline analysis. The protocol-oriented DR-DAQP described in the EDM instrumentation summary is instead a synchronized low-noise measurement architecture. Its principal objects are simultaneously sampled 24-bit voltage readings with timestamps. Its dominant constraints are galvanic isolation, suppression of EMI and cross-talk, effective number of bits, settling, linearity, and ultra-low noise. The optimization \texttt{DR-DAQP} solver operates on neither waveforms nor analog samples, but on affine operators, polyhedral constraints, active sets, and KKT systems. Its evaluation criteria are convergence rate, finite termination under regularity, and solve time relative to competing solvers.

This comparison also clarifies a potential source of confusion. In the two instrumentation usages, “DAQ” literally denotes data acquisition. In the optimization usage, the suffix reflects the software lineage of the DAQP active-set QP solver rather than any detector or analog acquisition function. A plausible implication is that acronym-based literature searches require domain qualifiers such as “DarkSide-20k,” “electron EDM,” or “affine variational inequalities” to avoid false matches.

6. Limitations, conditions, and interpretive cautions

The supplied literature does not support treating DR-DAQP as a single standardized framework. Instead, it denotes domain-specific systems with sharply different assumptions and failure modes.

For DarkSide-20k, throughput and deadtime management remain central engineering constraints. The system relies on segment splitting, optional firmware compression, and a busy/veto handshake to keep typical deadtime below 0.5% under worst-case rates. Its stated reduction factor, approximately 50 from expected raw input to stored data, is tied to normal running; calibration modes rise to less than 200 MB/s, and the worst-case stress-test configuration was explicitly designed to exercise the limit of simultaneous pulsing rather than nominal physics traffic (Acerbi et al., 3 Apr 2026).

For the EDM DAQ implementation, the principal limitation is temporal rather than spectral. The summary states that full 24-bit settling requires 51 s, which is too slow for rapid step changes, even though 22-bit accuracy is reached in 200 ms and is described as sufficient for EDM modulation cycles of a few hertz. Additional limitations mentioned are the need for automated battery replacement and monitoring and the possibility of future temperature-sensor integration and digital calibration (Kim et al., 2011).

For the AVI solver, the limitations are mathematical. The method requires affine $\times$3, polyhedral $\times$4, and strong monotonicity for the stated global convergence theorem. Exact finite termination additionally requires LICQ and strict complementarity at the solution. The paper explicitly lists affine operators and polyhedral feasible sets as part of the problem class, and names general monotone variational inequalities and non-polyhedral sets as future extensions rather than present capabilities (Arnström et al., 2 Apr 2026).

Across all three usages, the acronym DR-DAQP therefore functions best as a context-dependent label rather than a unified concept. In dark-matter instrumentation it identifies a continuous triggerless online reduction pipeline; in precision measurement it denotes a high-dynamic-range, low-noise acquisition quality framework; and in optimization it names a hybrid first-order and active-set solver with warm-started QP structure and finite-termination properties under additional assumptions.