Digitally Controlled Silicon QPU

• Digitally Controlled Silicon QPUs are defined by silicon quantum dots operating with digitally programmable controllers for scalable, error-corrected quantum logic.
• They use high-speed waveform generators and FPGA-based systems to deliver precise voltage and microwave pulse sequences, achieving sub-microsecond correction latency.
• Experimental implementations demonstrate process fidelities near 0.88 with quadratic error suppression, indicating strong potential for fault-tolerant quantum architectures.

A Digitally Controlled Silicon Quantum Processing Unit (QPU) is a quantum computational platform constructed from silicon-based qubits—typically quantum-dot electron or hole spins—whose preparation, manipulation, and measurement are governed via digitally programmable electronic control, including high-speed arbitrary waveform generators and field-programmable gate arrays (FPGAs). This platform aims to combine the scalability and fabrication advantages of mainstream silicon CMOS technology with the algorithmic power of quantum error-corrected logic, leveraging real-time digital controllers for precision gate sequencing, error correction, and feedback.

1. Physical Architecture of Silicon Spin QPUs

Silicon QPUs are built from linear or two-dimensional arrays of quantum dots defined lithographically in silicon/silicon–germanium (Si/SiGe) or silicon–metal oxide semiconductor (Si-MOS) heterostructures. Each dot is electrically isolated and electrostatically controlled by overlapping gate electrodes fabricated using CMOS-compatible processes. Qubit encoding is realized via the two Zeeman (spin-up/spin-down) states of a confined electron or hole. Single-qubit operations employ electric-dipole spin resonance (EDSR), where a microwave drive induces rotations on the Bloch sphere; two-qubit entangling gates are achieved by activating controlled exchange interactions between neighboring dots, tunable by gate voltages to the MHz regime (Takeda et al., 2022).

Digital control is achieved via high-speed arbitrary waveform generators supplying bias and microwave pulses, combined with onboard FPGAs that manage real-time pulse sequencing, calibration, error tracking, syndrome extraction, and feedback. Fast (sub-microsecond) readout through charge-sensing channels and reservoir-coupled tunneling enables measurement-based protocols, while improved long-range couplers continue to enhance the flexibility and interconnectivity of qubits for large-scale architectures (Wang et al., 14 May 2025).

2. Quantum Error Correction Protocols in Silicon QPUs

Silicon QPUs have experimentally realized QEC primitive protocols, enabling logical encoding, syndrome extraction, and active or passive correction of quantum information. The three-qubit phase-flip code in the $X$-basis, with logical states $|0_L\rangle=|{+}{+}{+}\rangle$ and $|1_L\rangle=|{-}{-}{-}\rangle$, forms the foundation of demonstrated error correction (Takeda et al., 2022).

After encoding an arbitrary state as $$|\psi_L\rangle = \alpha|0_L\rangle+\beta|1_L\rangle$$, a single $Z$ error (phase flip) on any physical qubit is syndrome-mapped via measurement or conditional logic on the pairwise parity stabilizers $S_1=Z_1Z_2$, $S_2=Z_2Z_3$. These mutually commute and, along with the codespace constraint $S_1=S_2=+1$, localize the error to the appropriate qubit. Correction can be accomplished via a three-qubit conditional rotation or via explicit measurement and feedback.

In silicon QPUs, such correction has been implemented using a resonantly driven iToffoli gate, a three-qubit unitary that targets a data qubit conditional upon the joint state of two ancillas, removing the need for slow measurement and feedback. This is achieved by pulsed exchange interactions and frequency-selective microwave driving, programmable by the digital controller to operate with sub-500 ns latency and fidelity near 96% (Takeda et al., 2022).

3. Digital Control and Real-Time Error Correction

Digital control in a QPU encompasses precise voltage and microwave pulse delivery, real-time error-syndrome processing, and low-latency feedback. Complex sequences—for example, syndromic extraction, correction gates, and calibration—are orchestrated by FPGAs that ingest measurement outcomes and immediately trigger subsequent operations based on classical logic rules optimized for the underlying error model and code.

FPGA-based controllers digitize analog measurement signals (e.g., single-electron transistors or quantum point contacts for spin readout), apply signal-processing pipelines (e.g., filtering, integration, thresholding), and implement lookup tables to convert syndrome patterns into correction instructions. The time from error detection to correction application is thus reduced to a few microseconds—often below natural dephasing or relaxation times in isotopically purified silicon (Livingston et al., 2021).

The iToffoli correction mechanism in silicon QPUs substitutes measurement-and-classical feedback with a digitally timed, analogically shaped multiqubit gate, reducing overall correction latency further. The digital controller schedules exchange pulses and resonant microwave bursts precisely within the timing budget to optimize on-resonance selectivity and minimize off-resonant leakage (Takeda et al., 2022).

4. Performance Benchmarks and Error Scaling

For a QPU correcting phase-flip errors with a three-qubit code, the logical fidelity as a function of the single-qubit flip probability $p$ is fit to $F_\mathrm{corrected}(p) = 1-3p^2+2p^3$, confirming quadratic suppression of leading-order errors. In silicon-based demonstrations, the correction protocol achieved a process fidelity baseline of $|0_L\rangle=|{+}{+}{+}\rangle$0 (reduced from unity due to $|0_L\rangle=|{+}{+}{+}\rangle$1 iToffoli fidelity and dephasing), with the linear term in the error expansion suppressed to $|0_L\rangle=|{+}{+}{+}\rangle$2 up to error probabilities $|0_L\rangle=|{+}{+}{+}\rangle$3 (Takeda et al., 2022).

When natural dephasing (quasi–static phase noise) is the dominant error source, logical Ramsey coherence time using error correction exhibits a markedly flatter initial decay compared to the unprotected physical qubit (where $|0_L\rangle=|{+}{+}{+}\rangle$4s), evidencing first-order error insensitivity. Residual decay of the logical qubit is dominated by multi-qubit gate infidelity and higher-order noise processes. Achieved improvement factors for logical lifetimes range from twofold to over tenfold, depending on the code and gate fidelities (Ofek et al., 2016, Livingston et al., 2021).

5. Scaling, Overhead, and Future Directions

Scaling silicon QPUs beyond few-qubit QEC demonstrations hinges on challenges including connectivity, readout speed, and multi-qubit gate fidelity. The transition to two-dimensional nearest-neighbor or modular topologies, enabled by advanced CMOS foundry techniques and air-bridged long-range couplers, is expected to facilitate the implementation of higher-distance quantum LDPC codes with scalable resource overhead (Wang et al., 14 May 2025).

Resource-efficient QEC codes (e.g., qLDPC) implemented on large silicon arrays can, in principle, achieve logical error suppression at reduced physical-qubit cost, with simultaneous multi-qubit stabilizer measurements orchestrated by parallel digital controllers. For near-term devices, the focus remains on minimizing latency in syndrome extraction and correction, as future large-scale devices will require logical clock rates compatible with fault-tolerant protocols such as lattice surgery, magic-state distillation, and logical-branching workflows.

The removal of real-time measurement and feedback via digitally controlled, multi-qubit coherent gates (e.g., iToffoli) is a critical advancement for silicon QPUs, given the relatively slow electron-spin readout and reset in these systems. Planned improvements include integration of faster readout mechanisms (singlet–triplet conversion), dynamical decoupling during extended gate sequences, and further gate-fidelity optimization (Takeda et al., 2022). These developments are expected to pave the way toward demonstration of surface-code primitives, full Shor or Steane codeblocks, and ultimately scalable, fault-tolerant silicon QPUs.

6. Representative Experimental Realizations

QPU Platform	QEC Primitive	Correction Method	Achieved Fidelity
3-dot Si/SiGe	3-qubit phase	Digital iToffoli gate	0.88 (process)
Superconducting	3-qubit phase	CCNot (Toffoli) gate	0.76 (process)
Planar Si QD	LDPC (Roadmap)	Parallel digital/FPGA	Roadmap

Key experimental parameters:

• 3-qubit iToffoli: $|0_L\rangle=|{+}{+}{+}\rangle$5, pulse duration $|0_L\rangle=|{+}{+}{+}\rangle$6 ns, correction latency sub-$|0_L\rangle=|{+}{+}{+}\rangle$7s, single-shot state-readout fidelity $|0_L\rangle=|{+}{+}{+}\rangle$8;
• Demonstrated quadratic error suppression in phase-flip code ($|0_L\rangle=|{+}{+}{+}\rangle$9 scaling);
• Digital control stack: FPGA-based fast feedback, waveform generation, in situ calibration.

These results collectively establish digitally controlled silicon QPUs as a viable platform for implementing error-corrected quantum logic, highlighting the synthesis of advanced semiconductor fabrication, real-time digital control, and algorithmic QEC (Takeda et al., 2022, Wang et al., 14 May 2025, Ofek et al., 2016, Livingston et al., 2021).