Quantum Error Correction Demonstrations

Updated 21 April 2026

Quantum error correction demonstrations are experimental validations of protocols that protect quantum information from decoherence using fault-tolerant circuits such as the Steane and repetition codes.
These experiments employ various architectures including trapped ions, superconducting qubits, photonic systems, and solid-state devices by utilizing syndrome extraction, dynamic feedback, and optimized decoders.
They provide practical insights into logical fidelity improvements, resource trade-offs, and scalable implementations that are essential for advancing fault-tolerant quantum computing.

Quantum error correction (QEC) demonstrations are experimental realizations and characterizations of protocols that protect quantum information from decoherence and operational noise. These experiments validate fundamental QEC principles, benchmark code performance, investigate fault-tolerance criteria, and assess resource trade-offs in practical quantum architectures including trapped ions, superconducting qubits, photons, and solid-state platforms. QEC demonstrations range from three-qubit repetition codes through multi-round fault-tolerant syndrome extraction to advanced measurement-based and topological error protection, encompassing both active and passive (autonomous) correction schemes.

1. Fundamental Protocols, Code Architectures, and Fault Tolerance

Early and recent QEC demonstrations are built around well-characterized codes, notably the Steane [[7,1,3]] code, repetition (bit- and phase-flip) codes, concatenated Shor codes, subsystem (gauge) codes, and measurement-based (graph or cluster state) schemes.

Steane Code Demonstration: The Steane [[7,1,3]] color code encodes a single logical qubit with distance 3. Stabilizers $S_{1..6}$ are defined as:

$\begin{aligned} S_1 &= X_1 X_3 X_5 X_7,&\quad S_4 &= Z_1 Z_3 Z_5 Z_7,\ S_2 &= X_4 X_5 X_6 X_7,&\quad S_5 &= Z_4 Z_5 Z_6 Z_7,\ S_3 &= X_2 X_3 X_6 X_7,&\quad S_6 &= Z_2 Z_3 Z_6 Z_7. \end{aligned}$

Logical operators are minimum weight-3 up to multiplication by stabilizers, e.g., $\bar X = X_2 X_4 X_6 \cdot S_1$ (Postler et al., 2023).

Auxiliary Logical Register and Fault-Tolerance: Steane QEC is implemented by encoding both data and auxiliary logical qubits using identical circuits. Transversal logical CNOTs ensure that any physical gate fault introduces at most one error per block, a requirement for fault tolerance. Ancilla verification using a flag qubit identifies and excludes weight-2 errors on the auxiliary register (Postler et al., 2023).
Repetition and Shor Codes: Three-qubit codes for bit- or phase-flip errors are realized across superconducting circuits, silicon spin qubits, and solid-state NMR, with syndrome extraction via encoded measurement and correction by Toffoli-style gates or feedback pulses (Reed et al., 2011, Takeda et al., 2022, Moussa et al., 2011). Larger concatenated repetition codes (e.g., $[[9,1,3]]$ Shor) have been demonstrated on both trapped-ion and superconducting platforms, including full state preparation, measurement, and analysis of optimal code distance under realistic error rates (Nguyen et al., 2021).
Subsystem (Gauge) and LDPC Codes: Experiments have realized multi-round QEC using subsystem codes (e.g., heavy-hexagon), employing both gauge and stabilizer checks, and have demonstrated logical error suppression using maximum-likelihood and matching-based decoders (Sundaresan et al., 2022). Low-overhead quantum LDPC codes (distance-3 and -4) were implemented with parallel syndrome extraction and scalable gate layouts, achieving logical error rates $\sim8\%$ per cycle for up to six logical qubits (Wang et al., 14 May 2025).

2. Experimental Demonstration Methodologies

A typical QEC demonstration involves (1) logical encoding, (2) engineered error insertion or naturally occurring noise, (3) syndrome extraction (via projective or continuous measurement), (4) real-time or post-processed decoding, and (5) recovery application and tomographic analysis.

Syndrome Extraction: Fault-tolerant syndrome circuits are realized using transversal logical CNOTs (Steane), repeated stabilizer (plaquette) measurements (surface codes, topological codes), or direct continuous parity measurements (in continuous QEC) (Postler et al., 2023, Livingston et al., 2021, Yao et al., 2012).
Dynamic Feedback and Decoding: Real-time classical processing, including mid-circuit measurement and reset, enables adaptive correction protocols. Maximum-likelihood and graph-based decoders (minimum-weight matching, belief propagation) are deployed both offline and in FPGA-based real-time architectures, achieving syndrome-decode cycles of sub-microsecond latency, critical to avoid backlog and achieve fast logical clock rates (Caune et al., 2024, Sundaresan et al., 2022, Weinstein, 2013).
Measurement-Based and Topological Schemes: Graph-code demonstrations encode information in photonic or spin-based clusters, with error-detection and correction proceeding entirely by local measurement and classical feed-forward, validating MBQC-based QEC (Qin et al., 2023, Bell et al., 2014, Barz et al., 2013).

3. Logical Fidelity, Error Suppression, and Quantitative Performance

QEC demonstrations centrally report the decay of logical fidelity or process fidelity across rounds of error correction or as a function of the number of gates.

Steane QEC Example: Logical fidelities $F_L$ for input $|0_L\rangle$ drop from $0.87\pm0.01$ (round 0) to $0.62\pm0.02$ (after three rounds) using Steane QEC, outperforming flag-based QEC across all rounds (e.g., $F_L^\mathrm{flag} = 0.50$ at $\begin{aligned} S_1 &= X_1 X_3 X_5 X_7,&\quad S_4 &= Z_1 Z_3 Z_5 Z_7,\ S_2 &= X_4 X_5 X_6 X_7,&\quad S_5 &= Z_4 Z_5 Z_6 Z_7,\ S_3 &= X_2 X_3 X_6 X_7,&\quad S_6 &= Z_2 Z_3 Z_6 Z_7. \end{aligned}$ 0). Relative logical gains are $\begin{aligned} S_1 &= X_1 X_3 X_5 X_7,&\quad S_4 &= Z_1 Z_3 Z_5 Z_7,\ S_2 &= X_4 X_5 X_6 X_7,&\quad S_5 &= Z_4 Z_5 Z_6 Z_7,\ S_3 &= X_2 X_3 X_6 X_7,&\quad S_6 &= Z_2 Z_3 Z_6 Z_7. \end{aligned}$ 1– $\begin{aligned} S_1 &= X_1 X_3 X_5 X_7,&\quad S_4 &= Z_1 Z_3 Z_5 Z_7,\ S_2 &= X_4 X_5 X_6 X_7,&\quad S_5 &= Z_4 Z_5 Z_6 Z_7,\ S_3 &= X_2 X_3 X_6 X_7,&\quad S_6 &= Z_2 Z_3 Z_6 Z_7. \end{aligned}$ 2 per round (Postler et al., 2023).
Decoder Comparison: In heavy-hexagon subsystem code experiments, maximum-likelihood decoders outperform matching decoders, achieving logical error per round as low as $\begin{aligned} S_1 &= X_1 X_3 X_5 X_7,&\quad S_4 &= Z_1 Z_3 Z_5 Z_7,\ S_2 &= X_4 X_5 X_6 X_7,&\quad S_5 &= Z_4 Z_5 Z_6 Z_7,\ S_3 &= X_2 X_3 X_6 X_7,&\quad S_6 &= Z_2 Z_3 Z_6 Z_7. \end{aligned}$ 3 (versus $\begin{aligned} S_1 &= X_1 X_3 X_5 X_7,&\quad S_4 &= Z_1 Z_3 Z_5 Z_7,\ S_2 &= X_4 X_5 X_6 X_7,&\quad S_5 &= Z_4 Z_5 Z_6 Z_7,\ S_3 &= X_2 X_3 X_6 X_7,&\quad S_6 &= Z_2 Z_3 Z_6 Z_7. \end{aligned}$ 4 with matching) (Sundaresan et al., 2022).
Continuous QEC: Direct parity-monitoring schemes reach $\begin{aligned} S_1 &= X_1 X_3 X_5 X_7,&\quad S_4 &= Z_1 Z_3 Z_5 Z_7,\ S_2 &= X_4 X_5 X_6 X_7,&\quad S_5 &= Z_4 Z_5 Z_6 Z_7,\ S_3 &= X_2 X_3 X_6 X_7,&\quad S_6 &= Z_2 Z_3 Z_6 Z_7. \end{aligned}$ 5 bit-flip detection efficiency and increase logical qubit relaxation time by up to $\begin{aligned} S_1 &= X_1 X_3 X_5 X_7,&\quad S_4 &= Z_1 Z_3 Z_5 Z_7,\ S_2 &= X_4 X_5 X_6 X_7,&\quad S_5 &= Z_4 Z_5 Z_6 Z_7,\ S_3 &= X_2 X_3 X_6 X_7,&\quad S_6 &= Z_2 Z_3 Z_6 Z_7. \end{aligned}$ 6 over bare $\begin{aligned} S_1 &= X_1 X_3 X_5 X_7,&\quad S_4 &= Z_1 Z_3 Z_5 Z_7,\ S_2 &= X_4 X_5 X_6 X_7,&\quad S_5 &= Z_4 Z_5 Z_6 Z_7,\ S_3 &= X_2 X_3 X_6 X_7,&\quad S_6 &= Z_2 Z_3 Z_6 Z_7. \end{aligned}$ 7 values, with correction delays of $\begin{aligned} S_1 &= X_1 X_3 X_5 X_7,&\quad S_4 &= Z_1 Z_3 Z_5 Z_7,\ S_2 &= X_4 X_5 X_6 X_7,&\quad S_5 &= Z_4 Z_5 Z_6 Z_7,\ S_3 &= X_2 X_3 X_6 X_7,&\quad S_6 &= Z_2 Z_3 Z_6 Z_7. \end{aligned}$ 8s (Livingston et al., 2021).
Resource Trade-Offs: Simulation studies demonstrate that frequent QEC cycles are not always necessary; applying QEC only at optimal intervals can offer near-identical fidelity to per-gate correction with much lower qubit-time overhead, and in $\begin{aligned} S_1 &= X_1 X_3 X_5 X_7,&\quad S_4 &= Z_1 Z_3 Z_5 Z_7,\ S_2 &= X_4 X_5 X_6 X_7,&\quad S_5 &= Z_4 Z_5 Z_6 Z_7,\ S_3 &= X_2 X_3 X_6 X_7,&\quad S_6 &= Z_2 Z_3 Z_6 Z_7. \end{aligned}$ 9-biased noise scenarios, infrequent or omitted QEC yields higher final fidelity (Weinstein, 2013).

4. Extensions: Autonomous, Measurement-Based, Topological, and High-Dimensional QEC

Autonomous (Reservoir-Engineered) QEC: Multicomponent bosonic encodings stabilized by continuous-wave dissipative channels autonomously correct for dominant errors (e.g., single-photon loss), achieving over $\bar X = X_2 X_4 X_6 \cdot S_1$ 0 improvement in logical lifetimes without fast hardware feedback (Gertler et al., 2020). Numerical projections indicate parity stabilization can be concatenated for protection against a broader set of errors.
Topological and High-Dimensional Codes: Photonic cluster-state experiments verify topological error correction with single-shot protection of logical correlations and demonstrate error rates consistent with high-threshold ( $\bar X = X_2 X_4 X_6 \cdot S_1$ 1) locality constraints (Yao et al., 2012). Single-shot QEC has also been realized with a [[33,1,4]] four-dimensional surface code, matching or exceeding the performance of comparable 2D codes and eliminating the need for repeated syndrome measurements (Berthusen et al., 2024).
Redundant Symmetry and Measurement-Based Codes: Exploiting redundant non-local symmetries (SPT order) in graph states enables error-oblivious teleportation. Alternate “paths” of entangling edges on redundant-symmetry graphs protect against dominant hardware crosstalk errors, maintaining teleportation fidelities $\bar X = X_2 X_4 X_6 \cdot S_1$ 2 for all error strengths and recent devices (Qin et al., 2023).

5. Impact of Platform, Hardware Advances, and Scalability

QEC demonstrations are platform-sensitive, leveraging the strengths of each architecture:

Trapped Ions: All-to-all connectivity is exploited for transversal gates and parallel syndrome extraction in Steane or color codes, with $\bar X = X_2 X_4 X_6 \cdot S_1$ 3 s coherence and active dynamical decoupling (Postler et al., 2023, Reichardt et al., 2024).
Superconducting Qubits: Fast mid-circuit measurement and agile FPGA-classical control have achieved multi-round QEC and low-latency (<1 μs) syndrome decoding. Repeatable low-weight stabilizer measurement is supported by device improvements and long-range coupling (Sundaresan et al., 2022, Caune et al., 2024, Wang et al., 14 May 2025).
Photonics and MBQC: Graph-state and cluster-based QEC implementations highlight advantages for quantum networks and modular architectures, especially against loss and erasures, and pave the way for topologically protected measurement-based computation (Bell et al., 2014, Qin et al., 2023).
Silicon Spin Qubits, NMR: Recent demonstrations establish full encode-detect-correct cycles (including native three-qubit gates), opening the path towards CMOS-compatible scalable QEC (Takeda et al., 2022, Moussa et al., 2011).
Bosonic Encodings: Autonomous and hybrid measurement-autonomous protocols demonstrate clear resource efficiency, and recent experiments with binomial and cat codes show break-even thresholds where logical lifetime exceeds all constituent component lifetimes (Ofek et al., 2016, Gertler et al., 2020).

6. Outlook: Towards Scale, Universal Fault Tolerance, and Code Optimization

Key directions following from comprehensive QEC demonstrations include:

Increased Code Distance and Overhead Reduction: qLDPC codes, higher-dimensional surface codes, and subsystem color codes are actively explored to achieve exponential error suppression with near-constant overhead (Wang et al., 14 May 2025, Reichardt et al., 2024, Berthusen et al., 2024).
Real-Time Decoding and Feedback Integration: Integrated, scalable decoders capable of keeping pace with syndrome generation rates are critical for lattice surgery, magic state distillation, and threshold crossing experiments (Caune et al., 2024).
Hardware-Adapted Optimization: Tailoring QEC frequency, syndrome circuit depth, and code families to the dominant noise bias is empirically observed to be essential for reaching fault-tolerant thresholds without prohibitive resource cost (Weinstein, 2013).
Universal Gate Set and Full Logical Computation: Experiments are beginning to realize not only memory protection but full encoded logical Clifford gates, teleported T-gates, and nontrivial graph-state entanglement across multiple logical blocks (Postler et al., 2023, Reichardt et al., 2024, Caune et al., 2024).