Quantum CMOS Architectures

• Quantum CMOS architectures are integrated systems that combine quantum computing principles with standard CMOS fabrication to enable scalable qubit arrays.
• They leverage precise electrostatic control, gate-based dispersive readout, and cryogenic electronics to achieve high-fidelity operations (up to 99.99%) and efficient error correction.
• The designs support high qubit densities (up to 4 Mqubits/cm²) and monolithic integration on silicon chips while addressing variability and thermal management challenges.

Quantum CMOS architectures denote the synthesis of quantum information processing systems with complementary metal-oxide-semiconductor (CMOS) technology—a convergence aimed at enabling scalable, manufacturable, and integrated quantum-classical hardware. The principal focus areas include silicon-based spin and charge qubit arrays, CMOS-integrated readout and control, error correction-compatible fabrics, cryogenic electronics, and scalable communication approaches. This article surveys the key structural, operational, and integration principles underpinning contemporary quantum CMOS platforms, referencing prominent experimental and theoretical advances from the recent literature.

1. CMOS-Compatible Qubit Realizations

Quantum CMOS architectures leverage established CMOS fabrication processes such as fully depleted silicon-on-insulator (FD-SOI) and bulk CMOS to define qubits as discrete quantum states in silicon-based quantum dots or superconducting Josephson junctions.

• Spin Qubits: Encoded in the spin state of an electron or hole confined by electrostatic gates within the channel of a MOS or SOI transistor (Maurand et al., 2016, Nikandish et al., 2020). Control is provided by gate voltages and often by microwave driving exploiting spin resonance phenomena.
• Charge and Hybrid Qubits: Charge qubits utilize spatially delocalized single electrons in double quantum dots, with readout through capacitive sensing (Nikandish et al., 2020). Hybrid qubits combine spin and charge degrees of freedom for all-electrical, rapid operation (Rotta et al., 2014).
• Superconducting Qubits: CMOS-compatible processes have recently demonstrated Josephson junction-based qubits with high yield and fabrication uniformity at the 200-mm wafer scale (Lang et al., 25 Apr 2025), achieving coherence times (T$_1$ approaching 80 μs) and process variation (junction resistance spread ~12.4%) suitable for multichip scaling.

This diversity is enabled by precise electrostatic control inherent in advanced nanometric CMOS nodes (down to 7–22 nm), with industry-standard fabrication ensuring uniformity and integration yield (Rotta et al., 2014, Sokolov et al., 11 Dec 2024).

2. Device Architecture, Control, and Readout

The core structural paradigm unites CMOS-defined quantum dots with digital and analog circuits for qubit initialization, manipulation, and measurement:

• Array Layouts: Qubits are arranged in one- or two-dimensional lattices, with local control gates for confinement/tuning (e.g., barrier gates such as QT0, QT1, QT2) and global “common-mode” source/drain/back-gate voltages that set band profiles and confinement depth (Sokolov et al., 11 Dec 2024, Amitonov et al., 11 Dec 2024). Multi-qubit modules are engineered to support both computation and SWAP-based communication (Rotta et al., 2014).
• Sequential and Row-Column Addressing: Control/readout architecture often adopts a DRAM-inspired cell design, employing access transistors and storage capacitors for dynamic memory of qubit states and voltages (Schaal et al., 2018, Ruffino et al., 2021). Row-column multiplexing methodology scales wiring overhead as O($\sqrt{N}$) for $N$ qubits, dramatically mitigating cryostat interconnect complexity.
• Gate-Based Dispersive Readout: Non-invasive radiofrequency reflectometry, implemented by integrating resonant tanks with the gate electrodes, senses the quantum capacitance associated with interdot charge tunneling or spin-dependent transitions (Ruffino et al., 2021, Ciriano-Tejel et al., 2020). The quantum capacitance (for double dot energy $E(\epsilon)$ and detuning $\epsilon$) is given by:

$C_Q = -\frac{\partial^2 E}{\partial \epsilon^2}$

with $E(\epsilon) = \sqrt{\epsilon^2 + 4t^2}$ for tunnel coupling $t$ (Hamonic et al., 3 Oct 2024). Frequency multiplexing enables parallel, scalable readout.

• Cryogenic CMOS Electronics: Dedicated control chips fabricated in modern FinFET nodes operate at 3 K to generate tailored microwave bursts and gate pulses with sub-millivolt/ps precision, supporting single- and two-qubit gate fidelities of up to 99.99% (Xue et al., 2020).

3. Scalability, Integration, and Error Correction

Quantum CMOS architectures directly address the requirements of moving from a few to millions of qubits:

• Qubit Density: For exchange-only double quantum dot structures, logical qubit densities reach 2.8–4 Mqubits/cm² (for 10–7 nm technology nodes using the Steane code) (Rotta et al., 2017). Conservative surface-code layouts reduce this by 1–2 orders of magnitude.
• Monolithic Integration: Recent architectures realize quantum processor units (QPUs) co-locating quantum dot arrays (hundreds of qubits), control injectors, detectors, on-chip pattern generators, and digital logic within a single 22-nm FD-SOI chip (Bashir et al., 2021). The approach is demonstrated to be scalable with thermal loads (e.g., control/detection circuitry <2.5 mW per qubit) compatible with commercial cryocoolers.
• Error Correction Compatibility: Modular layouts are designed to implement surface code QEC, with classical word/bit addressing supporting parallel syndrome extraction, while resource allocation is adjusted for code distance and ancilla overhead (Veldhorst et al., 2016, Rotta et al., 2014). Tolerances for architectural variability (e.g., valley splitting, g-factor spread, exchange coupling) are quantified and shown to be compatible with such codes provided robust control is available (Cifuentes et al., 2023).

4. Metrology, Variability, and Control

• Process Variability: Atomic-scale disorder at the Si/SiO$_2$ interface introduces controlled and bounded variability in dot positions, valley splitting, and SO coupling (Cifuentes et al., 2023). Atomistic tight-binding and path integral Monte Carlo simulations have shown that these variations (few-nanometer centroids, order-of-magnitude valley splitting variation, bounded g-factor/detuning variability) can be controlled via global biasing and electrical tuning strategies (lever arms $\approx$0.26–0.27 eV/V) (Sokolov et al., 11 Dec 2024).
• Yield and Pre-Measurement Sorting: For superconducting qubits, fabrication process control and RT resistance characterization (via test structures) are statistically correlated with low-T qubit frequency, enabling pre-cooldown device selection and higher yield for large multichip systems (Lang et al., 25 Apr 2025). The Ambegaokar-Baratoff relation relates normal-state junction resistance $R_n$ to qubit frequency $f_{01}$:

$$f_{01} = \sqrt{\frac{1}{R_n} \frac{0.882 k_B T_c}{h C_q} - \frac{e^2}{2 h C_q}}$$

• Scalable Metrology: Quantum current standards based on charge-pumping in dual quantum dot CMOS devices have been demonstrated with (1.2 ± 0.1) × 10⁻³ A/A accuracy at 50 MHz. Proposals extend to monolithic integration of one million pumps plus on-chip control for μA-level standards (Dash et al., 19 Jun 2025).

5. Advanced Readout, Communication, and Photonic Integration

• Multiplexed Measurement and Control: Multiplexers (off-the-shelf or custom cryo-CMOS) enable parallel characterization and switching of tens to hundreds of devices in a single cryostat cool-down, overcoming the I/O bottleneck and enabling high-throughput device screening and real-time control (Wuetz et al., 2019, Pauka et al., 2019).
• Photonic Integration: Deterministic single-photon sources based on in-situ transfer printing of InAs/GaAs quantum dot nanobeams into CMOS-fabricated silicon photonic chips have been demonstrated, using Purcell enhancement and near-unity waveguide coupling, enabling scalable quantum PICs (Katsumi et al., 2018).
• Isolation and Multiplexed Gate-Based Readout: "Isolated" quantum dot arrays decouple from electron reservoirs post-loading, reducing configuration complexity for single-spin occupancy. Readout is achieved dispersively via embedded, frequency-multiplexed LC resonators coupled to comparison gates (Hamonic et al., 3 Oct 2024).

6. Future Prospects and Technological Implications

• Simulation-First Design: Industry-calibrated Quantum TCAD allows detailed Poisson–Schrödinger self-consistent modeling, aiding device layout and bias optimization for high-yield quantum dot formation and operation before fabrication (Sokolov et al., 11 Dec 2024).
• Device and Architecture Scaling: Achievable operational windows span 1–100 GHz for exchange-gate-based architectures (set by coherence, adiabaticity, and classical controller compatibility) (Rotta et al., 2017). All elements—fabrication, control, error correction, and metrology—are co-designed for scalable, manufacturable quantum CMOS platforms with existing industrial methods (Iyengar et al., 3 Jul 2024).
• Challenges: Main challenges include device variability, thermal load at cryogenic temperatures, and robust QEC integration. Advances in material stack engineering, further miniaturization (e.g., 7 nm nodes), and robust multiplexed communication/readout are active areas.

Overall, contemporary research demonstrates that silicon quantum dot arrays, superconducting circuits, and photonic elements can all be defined, manipulated, and measured within standard or slightly modified CMOS nodes. This provides a compelling foundation for mass-manufacturable, scalable quantum computing whose architecture is shaped by both quantum information requirements and practical semiconductor process constraints.