Composable Logical Gate Error

• Composable logical gate error is the residual failure arising in error-corrected operations due to schedule, channel, or architecture dependencies.
• It quantifies the minimum number of physical faults needed to cause a logical error using metrics like effective distance in topological codes and diamond-norm distances in approximate QEC.
• Careful design of gate schedules, decoding strategies, and error-transparent operations can mitigate correlated errors, ensuring that composed gates preserve error suppression.

Searching arXiv for the key papers and closely related recent work to ground the article. Composable logical gate error is the schedule-, channel-, or architecture-dependent residual failure associated with implementing a logical operation inside an error-corrected computation, together with the question of whether that failure remains controlled when gates are composed. In topological codes, the central object is often the minimum number of physical faults required to form a valid spacetime error chain that causes logical failure, denoted $w_{\min}$ and identified with an effective distance $d_{\mathrm{eff}}$ for the gate schedule (Milburn et al., 2012). In approximate quantum error correction, the same issue is formalized as a restricted diamond-norm distance between the implemented physical channel and the target logical gate, $\epsilon_L(W,U_L):=\|(W-U_L)\circ \Pi_L\|_\diamond$, which captures both logical distortion and leakage and is subadditive under composition (Brenner et al., 18 Sep 2025). Across both viewpoints, the topic concerns whether a logical gate preserves the error-suppression guarantees of the code when inserted into long circuits.

1. Schedule-specific failure in topological codes

For a static patch of the surface code, distance is the minimum weight of any undetectable logical operator, $d=\min_{P\in L} w(P)$, where $w(P)$ is the number of physical qubits on which $P$ acts nontrivially. During a logical gate, however, the stabilizer-measurement pattern changes in time, and faults on data and measurement or ancilla qubits can stitch together into chains that extend in space, in time, and diagonally in spacetime. In that setting, the relevant quantity is the minimum number of physical faults that form a valid spacetime error chain consistent with the schedule and lead to a logical failure; the data denote this quantity by $w_{\min}$ and identify the gate’s effective distance as $d_{\mathrm{eff}}=w_{\min}$ (Milburn et al., 2012).

This schedule dependence is the basis of the tool Nestcheck. A gate schedule is specified as a sequence of frames with commands such as ACTIVE, INACTIVE, ADD_X/ADD_Z, TRIM_X/TRIM_Z, HAD, and directional SWAPs. Autotune groups measurements into “sets,” places sets at spacetime coordinates, enumerates all single faults, and constructs primal and dual “nests” of balls and sticks. A stick represents the detection signature of a single physical fault, either between two detection events or between a detection event and a boundary. Multi-fault chains are paths in this nest, and the minimum logical fault is the shortest path connecting the relevant logical boundaries. The minimum over primal and dual nests gives $w_{\min}$ for the gate schedule (Milburn et al., 2012).

The central composability issue is that two individually sound gates need not remain sound when concatenated. The combined spacetime schedule can create new cross-gate diagonal chains whose weight is lower than the standalone effective distance of either gate. The data summarize this with the heuristic

$d_{\mathrm{seq}}=\min(d_1,d_2,w_{\mathrm{cross}}),$

where $d_{\mathrm{eff}}$0 is the minimum weight of any diagonal spacetime chain spanning the gate boundary. Nestcheck computes this directly by graph search on the combined nest (Milburn et al., 2012).

Boundary handling is therefore not a peripheral implementation detail. The first and last syndrome results at activation or deactivation are random unless explicitly attached to boundaries, and basis changes combined with movement require extra nonrepeating $d_{\mathrm{eff}}$1 frames so that newly activated syndrome results are treated as boundary-attached rather than accidentally paired across rounds. The paper’s case-study message is that subtle schedule transitions can create unexpected low-weight failure modes, and that padding with nonrepeating $d_{\mathrm{eff}}$2 frames and correct boundary sets restores the intended strength, including $d_{\mathrm{eff}}$3 in the demonstrated plate examples (Milburn et al., 2012).

2. Thresholds, spacetime blocks, and asymptotic composability

A second line of work studies composable logical gate error through circuit-level thresholds. For two toric-code blocks undergoing a transversal CNOT, the decoding problem can be mapped to disordered statistical-mechanical models. With perfect syndrome extraction and persistent bit-flip errors, the mapping is to a $d_{\mathrm{eff}}$4D random Ashkin–Teller model; with bit-flip plus syndrome errors, it becomes a $d_{\mathrm{eff}}$5D random $d_{\mathrm{eff}}$6-body Ising model with a defect plane. In this picture, the circuit-level threshold can be lower than the memory threshold because the gate spreads errors and introduces correlations that decoding must exploit (Xu et al., 12 Oct 2025).

The quantitative reductions reported for the transversal CNOT are modest but explicit. In the bit-flip-only case, the target threshold is $d_{\mathrm{eff}}$7, compared with the toric memory threshold $d_{\mathrm{eff}}$8, while the control threshold is $d_{\mathrm{eff}}$9. With bit-flip plus syndrome errors, the target threshold is conservatively estimated as $\epsilon_L(W,U_L):=\|(W-U_L)\circ \Pi_L\|_\diamond$0 versus memory $\epsilon_L(W,U_L):=\|(W-U_L)\circ \Pi_L\|_\diamond$1. The same work states that an arbitrary transversal Clifford logical circuit can be mapped to a stat-mech model with localized defects in time, and that this yields a nonzero circuit threshold for composed transversal Clifford circuits (Xu et al., 12 Oct 2025).

Below threshold, the logical error rate is exponentially suppressed with code distance, $\epsilon_L(W,U_L):=\|(W-U_L)\circ \Pi_L\|_\diamond$2, and for a sequence of $\epsilon_L(W,U_L):=\|(W-U_L)\circ \Pi_L\|_\diamond$3 transversal gates with weak inter-gate correlations the reported approximation is $\epsilon_L(W,U_L):=\|(W-U_L)\circ \Pi_L\|_\diamond$4. This does not imply that gate application is free: the same paper emphasizes that gate-induced correlations can renormalize the effective decay and require joint decoding across blocks and across defect planes (Xu et al., 12 Oct 2025).

A complementary framework treats logical gates as $\epsilon_L(W,U_L):=\|(W-U_L)\circ \Pi_L\|_\diamond$5D spacetime objects called logical blocks. Here a block is a stabilizer instrument with logical ports, check generators on homologically trivial codimension-$\epsilon_L(W,U_L):=\|(W-U_L)\circ \Pi_L\|_\diamond$6 surfaces, and logical correlators represented by membranes. Fault distance is the minimum number of elementary faults that leave all checks satisfied but flip a logical membrane sign. In this framework, blocks are designed to have distance $\epsilon_L(W,U_L):=\|(W-U_L)\circ \Pi_L\|_\diamond$7 under IID Pauli and measurement errors, and distance is preserved under transversal composition of compatible ports (Bombin et al., 2021).

The resulting thresholds are reported to agree with the bulk memory threshold across identity, phase, Hadamard, and lattice-surgery blocks. For below-threshold operation, the logical block error rate is fit by

$\epsilon_L(W,U_L):=\|(W-U_L)\circ \Pi_L\|_\diamond$8

with $\epsilon_L(W,U_L):=\|(W-U_L)\circ \Pi_L\|_\diamond$9 strongly dependent on boundary conditions and defects. Composition is summarized by

$d=\min_{P\in L} w(P)$0

for small $d=\min_{P\in L} w(P)$1, while low-$d=\min_{P\in L} w(P)$2 lattice-surgery errors on different qubits are approximately independent to first order (Bombin et al., 2021).

This asymptotic perspective clarifies a common misconception. Static memory thresholds are not automatically gate thresholds, but neither do gates necessarily destroy threshold behavior. The cited results instead point to a geometry-dependent regime in which defects, boundaries, and time-local gate structures alter the prefactors and decay rates while preserving a nonzero threshold and exponential suppression when the full correlated decoding problem is treated correctly (Xu et al., 12 Oct 2025).

3. Circuit-level gate studies in the surface code

Concrete circuit-level analyses of individual gates show how composable logical gate error is realized in explicit schedules. For the logical Hadamard in the rotated planar surface code, two patch-deformation implementations were compiled to square-grid hardware and simulated under a circuit-level Pauli noise model. The paper defines effective distance as the minimum number of fault locations necessary to cause an undetectable logical failure, constructs syndrome-extraction schedules that preserve this distance under circuit-level noise, and reports that the logical Hadamard failure probability is only slightly worse than that of a logical memory experiment with the same number of rounds, with the ratio approaching $d=\min_{P\in L} w(P)$3 as distance increases or physical error decreases (Gehér et al., 2023).

The same study identifies the operational reason. Rectangular deformations create more pathways for failure, but careful scheduling keeps hook errors oriented so that they do not align with minimal logical strings, and the resulting tradeoff largely cancels. A further contribution is a compilation of the required SWAP-QEC round into four two-qubit layers, explaining from first principles how “stepping” circuits preserve performance comparable to standard syndrome extraction (Gehér et al., 2023).

For the logical $d=\min_{P\in L} w(P)$4 gate via twist-defect braiding, a recent circuit-level study compares prior spacetime volumes $d=\min_{P\in L} w(P)$5 and $d=\min_{P\in L} w(P)$6 with a proposed $d=\min_{P\in L} w(P)$7 protocol. Under circuit-level uniform depolarizing noise and minimum-weight matching, the reported fault distances are Bombín $d=\min_{P\in L} w(P)$8, Gidney $d=\min_{P\in L} w(P)$9, proposed non-local $w(P)$0, and proposed local $w(P)$1. Despite the constant-offset reduction in effective distance, the logical error rates remain comparable to existing methods for $w(P)$2 and physical error rates near $w(P)$3, and are also comparable to idling circuits of equal spacetime volume (Hirai et al., 15 Apr 2026).

The significance is not that fault distance ceases to matter, but that asymptotic distance and finite-parameter logical error rate need not be governed by the same rare events. The paper states that, at the tested parameters, the dominant error events remain length-$w(P)$4-like chains, so the shorter hook-error witnesses do not catastrophically increase $w(P)$5 (Hirai et al., 15 Apr 2026).

A third example is a transversal logical CNOT with multi-cycle error detection on IBM heavy-hex hardware using repetition-code blocks with flags. The experiments used $w(P)$6, $w(P)$7, and $w(P)$8 physical qubits for code distances $w(P)$9, respectively, and performed up to $P$0 rounds of error detection. The reported result is error suppression with increasing code size despite error propagation among logical qubits during the transversal CNOT, establishing the feasibility of combining logical CNOT gates with multi-cycle error detection on current superconducting hardware (Kim et al., 2024).

4. Channel-level formulations and approximate quantum error correction

In approximate quantum error correction, composable logical gate error is defined directly at the channel level. Let $P$1 be a code subspace with projector $P$2, and let $P$3 be a physical CPTP implementation of a target logical unitary $P$4. The composable logical gate error is

$P$5

where $P$6. In the more general setting of distinct input and output code spaces, the same definition is used with the corresponding projectors. The quantity captures both deviation of the logical action inside the code space and leakage out of the code space, and it is subadditive under circuit composition (Brenner et al., 18 Sep 2025).

This produces a direct composability theorem. If $P$7 and $P$8 implement successive logical unitaries $P$9 and $w_{\min}$0, then

$w_{\min}$1

The same work also gives tensor-product subadditivity and bounds in terms of matrix elements of

$w_{\min}$2

including the dimension-independent inequalities

$w_{\min}$3

where $w_{\min}$4 is the Crawford number (Brenner et al., 18 Sep 2025).

Applied to approximate GKP codes, this framework distinguishes sharply between gates that remain asymptotically accurate and gates that do not. For symmetrically squeezed truncated GKP codes, the paper proves $w_{\min}$5 and $w_{\min}$6, and obtains $w_{\min}$7. By contrast, the standard Gaussian implementation of the phase gate $w_{\min}$8, although exact for ideal GKP codes, has a constant logical gate error in the approximate setting: for $w_{\min}$9,

$d_{\mathrm{eff}}=w_{\min}$0

The paper states explicitly that findings applicable to ideal GKP codes do not always translate to physically realizable approximate GKP codes (Brenner et al., 18 Sep 2025).

A related but distinct strategy is to convert coherent synthesis errors into incoherent ones by randomization. If a target gate can be synthesized by randomly choosing among several nearby unitaries whose average is closer to the target than any individual option, the resulting errors can add incoherently, so that the per-gate synthesis precision requirement is relaxed from roughly $d_{\mathrm{eff}}=w_{\min}$1 to roughly $d_{\mathrm{eff}}=w_{\min}$2 over a circuit of length $d_{\mathrm{eff}}=w_{\min}$3. The same source notes that ordinary state-injection circuits for $d_{\mathrm{eff}}=w_{\min}$4 gates exhibit this effect automatically because measurement randomness averages over nearby implementations (Hastings, 2016).

Learning-based approaches generalize the channel viewpoint to arbitrary codes. A recent framework constructs physical realizations of logical gates from an encoding circuit alone, evaluates effective logical channels $d_{\mathrm{eff}}=w_{\min}$5, and uses exact two-design averages, process fidelity, average gate fidelity, and diamond-norm distance to assess composability. The reported composition bounds are the usual diamond-norm triangle inequality and approximately additive average-gate infidelity in the high-fidelity regime targeted by the optimization (Meyer et al., 27 May 2026).

5. Error-transparent and dynamically corrected operations

A stronger notion than ordinary fault tolerance is error transparency. In the quantum-jump picture, a gate is error-transparent if, for an error $d_{\mathrm{eff}}=w_{\min}$6 occurring at an unknown time $d_{\mathrm{eff}}=w_{\min}$7 during the gate window,

$d_{\mathrm{eff}}=w_{\min}$8

for all logical inputs, with $d_{\mathrm{eff}}=w_{\min}$9 an equivalent error in the error space. At the Hamiltonian level, the requirement is that the logical generator be identical on the code and error spaces up to a sector-dependent identity term (Ma et al., 2019).

This condition was demonstrated experimentally for a bosonic binomial code subject to single-photon loss. Using photon-number-resolved AC Stark shifts, the effective Hamiltonian was tuned so that its projection onto the logical code space and the single-loss error space implemented the same logical $w_{\min}$0 rotation up to an irrelevant identity term. The paper reports preservation of coherence in the error space, higher process fidelity for error-transparent than non-error-transparent phase gates, and a composable sequence property: under repeated error-transparent gates plus autonomous QEC, the logical channel behaves like the intended unitary interleaved with the same physical loss channel rather than acquiring unknown timing-dependent coherent over-rotations (Ma et al., 2019).

A related architecture-level realization is the Very Small Logical Qubit. There, single- and two-qubit logical gate Hamiltonians are engineered so that single photon losses remain correctable during the gate itself. The reported two-qubit $w_{\min}$1 gate exhibits

$w_{\min}$2

for a $w_{\min}$3 ns gate, yielding $w_{\min}$4 at $w_{\min}$5s, while the dominant logical error mechanism remains double loss between correction events. The same work states that the effective logical gate error displays superlinear error reduction with linear increases in single-qubit lifetime (Kapit, 2017).

Systematic coherent control errors can also be suppressed compositionally without invoking a code-space syndrome picture. Antisymmetric composite NOT gates can be nested so that the leading surviving error term after nesting level $w_{\min}$6 is order $w_{\min}$7, giving infidelity

$w_{\min}$8

with sequence length $w_{\min}$9 (Jones, 2013). For two-qubit entangling gates, dynamically corrected constructions produce CNOT gates that cancel arbitrary quasistatic systematic errors within the logical two-qubit subspace to arbitrary order by nesting composite $d_{\mathrm{seq}}=\min(d_1,d_2,w_{\mathrm{cross}}),$0-entangler modules, assuming access to high-fidelity single-qubit gates (Calderon-Vargas et al., 2016).

These results suggest a conceptual distinction. Error transparency preserves the logical action in the presence of a correctable physical error occurring during the gate, whereas composite and dynamically corrected gates suppress a prescribed systematic control-error model order by order. Both viewpoints address composability, but they do so by different mechanisms: one by matching dynamics across syndrome sectors, the other by forcing cancellation in the toggling frame (Ma et al., 2019).

6. Non-Clifford gates, resource trade-offs, and design principles

Non-Clifford gates are where composable logical gate error often becomes the dominant architectural constraint. In a DFS-encoded superconducting logical $d_{\mathrm{seq}}=\min(d_1,d_2,w_{\mathrm{cross}}),$1 gate, a two-transmon logical qubit is encoded as $d_{\mathrm{seq}}=\min(d_1,d_2,w_{\mathrm{cross}}),$2, $d_{\mathrm{seq}}=\min(d_1,d_2,w_{\mathrm{cross}}),$3, rendering it immune to collective dephasing to first order. An optimized composite geometric protocol then cancels first-, second-, and third-order contributions from Rabi amplitude error, detuning error, and residual inter-qubit crosstalk, leaving fourth-order leading terms. The reported expansions are

$d_{\mathrm{seq}}=\min(d_1,d_2,w_{\mathrm{cross}}),$4

$d_{\mathrm{seq}}=\min(d_1,d_2,w_{\mathrm{cross}}),$5

$d_{\mathrm{seq}}=\min(d_1,d_2,w_{\mathrm{cross}}),$6

and the paper states that this fourth-order suppression dramatically reduces cumulative error under composition (Ding et al., 1 May 2026).

A different route is magic-state-based non-Clifford logic. A recent trapped-ion experiment prepared logical magic states in a $d_{\mathrm{seq}}=\min(d_1,d_2,w_{\mathrm{cross}}),$7 code with experimental infidelity $d_{\mathrm{seq}}=\min(d_1,d_2,w_{\mathrm{cross}}),$8 and discard rate $d_{\mathrm{seq}}=\min(d_1,d_2,w_{\mathrm{cross}}),$9, then used them to implement a logical controlled-Hadamard with logical infidelity $d_{\mathrm{eff}}$00, outperforming the unencoded physical controlled-Hadamard infidelity of $d_{\mathrm{eff}}$01. Circuit-level stabilizer simulations of the self-concatenated $d_{\mathrm{eff}}$02 construction yielded logical error rates of $d_{\mathrm{eff}}$03 at two-qubit error rate $d_{\mathrm{eff}}$04 and $d_{\mathrm{eff}}$05 at $d_{\mathrm{eff}}$06 (Dasu et al., 17 Jun 2025).

Ancilla preparation can also destroy composability if not designed carefully. In Shor’s logical Toffoli construction for CSS codes with even-weight stabilizer generators and odd-weight logical operators, single faults in ancilla preparation can propagate into first-order logical errors. The cited remedy is the insertion of bit-flip error correction during ancilla preparation, which removes the single-fault logical paths so that the modified construction recovers the same accuracy threshold as transversal gates when ancillary systems can be prepared just in time (Aratsu, 2010).

Across these implementations, several design principles recur. Gate schedules should expose all temporal boundaries explicitly; decoders should exploit inter-block and inter-time correlations rather than discard them; heralding and post-selection can convert rare catastrophic events into throughput loss; and when exact implementation is unavailable, the metric used for budgeting should be subadditive under composition, whether it is $d_{\mathrm{eff}}$07, a circuit threshold, or a restricted diamond norm. A plausible implication is that “composable logical gate error” is not a single scalar native to all architectures, but a family of structure-preserving criteria whose common purpose is to guarantee that logical gates remain compatible with the suppression mechanism of the underlying code (Brenner et al., 18 Sep 2025).