Biased Noise Ancillas in Quantum Error Correction

• Biased noise ancillas are ancillary qubits engineered with deliberately asymmetric error channels, typically dominated by Z-errors, to maintain error bias in quantum circuits.
• They are integrated within tailored code designs such as XZZX and modified surface codes, supporting significant improvements in logical error rates and fault tolerance.
• Their design couples parameterized error models with controlled gate operations, ensuring that the dominant error remains localized and manageable during syndrome extraction and coherent control.

Searching arXiv for recent and relevant papers on biased-noise ancillas and related fault-tolerant constructions. Biased noise ancillas are ancillary qubits, ancillary modes, or ancillary resource states whose physical error channels are deliberately asymmetric, typically so that one Pauli sector dominates and the remaining sectors are strongly suppressed. In the literature summarized here, the dominant setting is dephasing-biased noise, where $Z$ errors are much more likely than $X$ or $Y$, and ancillas are engineered, scheduled, or encoded so that this asymmetry is preserved at the circuit level rather than erased by syndrome extraction, gate synthesis, or foliation. The concept spans several layers of the fault-tolerant stack: ancilla qubits for stabilizer measurement, flag qubits for fault diagnosis, hardware-level logical ancillas such as cat-like or dressed qubits, ancilla-mediated coherent control, and resource-state ancillas for cluster-state or measurement-free computation (Xu et al., 2022).

1. Definition and parameterizations

In the stabilizer and surface-code literature, biased noise is commonly formalized as an asymmetric Pauli channel

$$\mathcal{E}(\rho) = (1-p)\rho + p_x X\rho X + p_y Y\rho Y + p_z Z\rho Z,$$

with bias parameter

$\eta = \frac{p_z}{p_x+p_y},$

so that $\eta = 1/2$ corresponds to depolarizing noise and $\eta \to \infty$ to pure dephasing. This parameterization is used both in the modified surface-code construction of Tuckett, Bartlett, and Flammia and in later XZZX-based and Floquet constructions tailored to dephasing-dominated hardware (Tuckett et al., 2017).

A second parameterization, used for tailored XZZX codes, assigns an effective weight to each Pauli according to its probability, normalizing the most likely error to weight $1$. In the independent $X/Z$ model,

$$p_X = p_Z^\omega,\qquad p_Y = p_Xp_Z = p_Z^{\omega+1},$$

with effective single-qubit weights

$X$0

The corresponding effective distance $X$1 is “the minimum modified weight of logical operators,” and serves as a proxy for the logical failure rate under biased noise (Xu et al., 2022).

The same theme appears in hardware-level ancillas. In the anisotropic Rabi model, “noise bias” is defined through relaxation and dephasing susceptibilities of the logical doublet $X$2 under operators $X$3, with the anisotropy parameter $X$4 tuning which quadrature coupling dominates. In the spin-cat qubit, bias is extracted experimentally from dihedral randomized benchmarking as

$X$5

with $X$6 the dephasing-type error probability and $X$7 the non-dephasing probability per dihedral gate (Yu et al., 3 Jun 2026, Kusano et al., 26 Feb 2026).

These parameterizations support a common definition. A biased-noise ancilla is not merely an ancillary subsystem with long coherence; it is an ancillary subsystem whose dominant physical error channel is known, structured, and preserved by the gate set. This suggests that ancilla design is inseparable from the error model used by the decoder and from the choice of logical operators that are intended to absorb the dominant faults.

2. Ancillas in bias-tailored stabilizer and topological codes

In bias-tailored stabilizer extraction, ancillas are used so that the most likely faults either remain local dephasing events or are converted into syndrome-bit errors rather than high-weight data faults. This principle is explicit in tailored XZZX codes, where syndrome extraction employs a syndrome qubit $X$8 and a flag qubit $X$9. The flag circuit is designed so that dangerous $Y$0-type faults at specific locations propagate to controlled multi-qubit data errors while simultaneously flipping the flag outcome. The paper states that “by adding only one flag qubit, the XZZX codes can realize fault-tolerant QEC while preserving their large effective distance” (Xu et al., 2022).

The same logic appears in the modified surface code for $Y$1-biased noise. Replacing plaquette $Y$2-checks by $Y$3-checks doubles the number of useful syndrome bits associated with dominant $Y$4 errors. The ancilla prescription is then to place ancillas at vertices and face centers, initialize and measure all ancillas in the $Y$5 basis, and use controlled-$Y$6 and controlled-$Y$7 gates with ancilla as control. In that arrangement, an ancilla $Y$8 error commutes with the control projectors and does not propagate to the data qubits; it acts primarily as a measurement error, which can be handled by repeated syndrome extraction and space-time decoding (Tuckett et al., 2017).

For phenomenological and circuit-level settings, the decoder must retain the same asymmetry. In the fault-tolerant surface-code decoder for biased noise, data and ancilla qubits are assigned a high-rate dephasing error

$Y$9

and low-rate bit-flip–type errors

$$\mathcal{E}(\rho) = (1-p)\rho + p_x X\rho X + p_y Y\rho Y + p_z Z\rho Z,$$0

Measurement errors are modeled as syndrome-bit flips with probability $$\mathcal{E}(\rho) = (1-p)\rho + p_x X\rho X + p_y Y\rho Y + p_z Z\rho Z,$$1, typically set to $$\mathcal{E}(\rho) = (1-p)\rho + p_x X\rho X + p_y Y\rho Y + p_z Z\rho Z,$$2. The resulting matching weights

$$\mathcal{E}(\rho) = (1-p)\rho + p_x X\rho X + p_y Y\rho Y + p_z Z\rho Z,$$3

penalize symmetry-breaking steps relative to dominant dephasing-like steps, thereby encoding the ancilla bias directly into the decoder graph (Tuckett et al., 2019).

The central misconception in this area is that ancillas matter only through their raw fidelity. The literature instead treats ancillas structurally. An ancilla with high $$\mathcal{E}(\rho) = (1-p)\rho + p_x X\rho X + p_y Y\rho Y + p_z Z\rho Z,$$4-error rate can still be advantageous if $$\mathcal{E}(\rho) = (1-p)\rho + p_x X\rho X + p_y Y\rho Y + p_z Z\rho Z,$$5 faults do not spread through the extraction circuit, while a lower-error but symmetry-destroying ancilla circuit can erase the benefit of a biased code.

3. Hardware realizations of biased ancillas

Several recent works interpret biased ancillas as hardware-level logical qubits rather than merely physical syndrome qubits. In the anisotropic Rabi model,

$$\mathcal{E}(\rho) = (1-p)\rho + p_x X\rho X + p_y Y\rho Y + p_z Z\rho Z,$$6

so tuning $$\mathcal{E}(\rho) = (1-p)\rho + p_x X\rho X + p_y Y\rho Y + p_z Z\rho Z,$$7 reshapes the logical susceptibilities $$\mathcal{E}(\rho) = (1-p)\rho + p_x X\rho X + p_y Y\rho Y + p_z Z\rho Z,$$8 and $$\mathcal{E}(\rho) = (1-p)\rho + p_x X\rho X + p_y Y\rho Y + p_z Z\rho Z,$$9. In the deep-strong regime, the logical doublet can become nearly immune to $\eta = \frac{p_z}{p_x+p_y},$0- and $\eta = \frac{p_z}{p_x+p_y},$1-type relaxation for $\eta = \frac{p_z}{p_x+p_y},$2, while orthogonal channels remain larger. The authors therefore identify the dressed logical doublet as a candidate biased-noise ancilla, especially for superconducting platforms where $\eta = \frac{p_z}{p_x+p_y},$3 and $\eta = \frac{p_z}{p_x+p_y},$4 are dominant physical channels (Yu et al., 3 Jun 2026).

The spin-cat qubit provides an experimental realization of the same idea in an optical tweezer array. The logical basis is encoded in the stretched nuclear-spin sublevels

$\eta = \frac{p_z}{p_x+p_y},$5

The experiment implements covariant SU(2) control and a non-linear “cat rotation,” and reports an averaged single-Clifford gate fidelity of $\eta = \frac{p_z}{p_x+p_y},$6 under the level-2 coarse-grained readout. More importantly for ancilla use, dihedral randomized benchmarking yields

$\eta = \frac{p_z}{p_x+p_y},$7

and hence a finite bias

$\eta = \frac{p_z}{p_x+p_y},$8

whereas a two-level $\eta = \frac{p_z}{p_x+p_y},$9 qubit shows no bias within experimental uncertainty (Kusano et al., 26 Feb 2026).

Both works emphasize that not all channels can be suppressed simultaneously. In the anisotropic Rabi model, changing $\eta = 1/2$0 suppresses one pair of orthogonal channels while enhancing another. In the spin-cat setting, increasing $\eta = 1/2$1 shortens $\eta = 1/2$2 but lengthens $\eta = 1/2$3, so the bias is obtained by increasing dephasing relative to relaxation rather than by improving all coherence metrics at once. A plausible implication is that hardware-level biased ancillas are best understood as directional error filters, not universally protected qubits.

4. Ancilla circuit design beyond syndrome measurement

Biased-noise ancillas also appear in coherent-control protocols where the ancilla never becomes a full data register but still mediates nontrivial logical operations. In “path-independent” gates, the ancilla is noisy and strongly coupled, yet the logical action on the central system is engineered to be independent of the detailed ancilla error trajectory. For dephasing-type ancilla noise $\eta = 1/2$4, the path-independence condition implies robustness to all orders in the ancilla dephasing rates if the no-jump propagator has the appropriate factorized form and satisfies the loop condition $\eta = 1/2$5. For relaxation-type noise, the corresponding protection requires a noiseless ancilla subspace (NAS) in which conditional system Hamiltonians differ only by scalar phases (Ma et al., 2019).

In hybrid CV–DV protocols, the ancilla can be designed so that its dominant damping channel is aligned with the accepted branch of the protocol. A single qubit ancilla, prepared and postselected in $\eta = 1/2$6, is used in a controlled-Fourier interferometer to suppress bosonic thermal or Gaussian displacement noise from linear to quadratic scaling. For like-parity rotation-symmetric bosonic codes, the ancilla remains in the ground state throughout the no-error branch, so amplitude damping on the ancilla is effectively harmless in accepted runs. The qutrit extension makes this explicit: the successful branch is resilient to cascaded damping $\eta = 1/2$7 and selective phase damping on $\eta = 1/2$8, with first-order cancellation of ancilla noise after normalization (Shringarpure et al., 23 May 2026).

A different ancilla-centric perspective appears in scalable noisy circuits for bit-flip-biased qubits motivated by stabilized cat qubits. There the measured register qubit functions as a biased-noise ancilla in Hadamard-test variants, and all gates are required to be bias-preserving in the sense that they map $\eta = 1/2$9-string errors to $\eta \to \infty$0-string errors. Under this condition the ancilla state takes the form

$\eta \to \infty$1

with $\eta \to \infty$2 polynomially bounded when the number of direct ancilla interactions is $\eta \to \infty$3. The same restricted structure also makes the noisy circuits efficiently classically simulable, so the protocol becomes a benchmark of large-scale bias preservation rather than a route to quantum advantage (Fellous-Asiani et al., 2023).

These constructions share a common design rule. The ancilla should either remain in a noise-attracting state, such as $\eta \to \infty$4, or evolve inside a subspace where the dominant ancilla faults commute with the relevant controlled operations. This suggests that ancilla robustness under biased noise is often more about kinematic placement in Hilbert space than about suppressing every physical fault channel.

5. QLDPC, Floquet, and measurement-free uses of biased ancillas

In QLDPC syndrome extraction, biased ancillas address two distinct obstacles: hook errors and short loops in the detector error model. For bicycle bivariate codes and a cyclic hypergraph product code, conventional circuits use one ancilla per stabilizer, prepared and measured in the $\eta \to \infty$5-basis, with ancilla always the control of CZ or CX gates. Under depolarizing noise, ancilla $\eta \to \infty$6 or $\eta \to \infty$7 faults propagate to multiple data qubits, reducing effective circuit distance and generating many 4- and 6-cycles in the Tanner graph. Under ancilla-only bias or full bias, those propagating ancilla faults are strongly suppressed. The paper reports almost an order of magnitude improvement in the logical error rate at circuit noise $\eta \to \infty$8 when ancilla bit-flip errors are 50 times less likely than phase-flip errors, and an 8.5-fold reduction for the $\eta \to \infty$9 BB code at $1$0, $1$1 (Bi et al., 29 Jun 2026).

For dynamical codes, biased ancillas enter through bias-preserving parity-measurement gadgets. The X$1$2Z$1$3 Floquet code uses ancilla-assisted circuits for $1$4, $1$5, and $1$6 parity measurements built from CZ gates or CNOTs with data as control and ancilla as target. In these circuits, a $1$7 error on either ancilla or data remains $1$8-type on data, so the dominant dephasing channel is preserved even on hardware without native parity measurements. This ancilla design complements the code’s persistent symmetry under infinite bias and supports improved performance on honeycomb and heavy-hex architectures (Setiawan et al., 2024).

Measurement-free QEC pushes the role of ancillas further. In the Steane-code construction optimized for $1$9-biased Rydberg noise, ancillas coherently store stabilizer values, flags, and magic-state verification information, and feedback is applied with CZ, CCZ, and CCCZ gates rather than measurements. Because the multi-qubit gates and their dominant faults are diagonal,

$X/Z$0

$X/Z$1-errors on ancillas commute through the feedback network and do not create hook errors. The same framework yields a measurement-free T gate with leading logical noise that is entirely $X/Z$2-type, $X/Z$3, and remains fault-tolerant under sufficiently small fractions of non-$X/Z$4 gate faults (Brechtelsbauer et al., 21 May 2025).

These examples show that biased ancillas are not restricted to syndrome readout. They can also implement coherent feedback, logical switching, and universal gate injection, provided the ancilla-control gates preserve the dominant error sector rather than dispersing it across the data block.

6. Resource states, limitations, and scope of the concept

Biased-noise ancillas also appear at the level of fault-tolerant resource states. Standard foliation of a 2D stabilizer code into a 3D cluster state does not preserve a $X/Z$5-bias, because physical $X/Z$6 errors on measured qubits can induce logical $X/Z$7-type noise in the teleportation chain. The generalized cluster-state construction avoids this by introducing $X/Z$8-type qubits, prepared and measured in the $X/Z$9 basis, and $$p_X = p_Z^\omega,\qquad p_Y = p_Xp_Z = p_Z^{\omega+1},$$0-type qubits, prepared and measured in the $$p_X = p_Z^\omega,\qquad p_Y = p_Xp_Z = p_Z^{\omega+1},$$1 basis, with $$p_X = p_Z^\omega,\qquad p_Y = p_Xp_Z = p_Z^{\omega+1},$$2 edges between $$p_X = p_Z^\omega,\qquad p_Y = p_Xp_Z = p_Z^{\omega+1},$$3-type qubits and $$p_X = p_Z^\omega,\qquad p_Y = p_Xp_Z = p_Z^{\omega+1},$$4 edges from $$p_X = p_Z^\omega,\qquad p_Y = p_Xp_Z = p_Z^{\omega+1},$$5-type to $$p_X = p_Z^\omega,\qquad p_Y = p_Xp_Z = p_Z^{\omega+1},$$6-type qubits. In the resulting 1D teleportation chains, logical $$p_X = p_Z^\omega,\qquad p_Y = p_Xp_Z = p_Z^{\omega+1},$$7 is a pure-$$p_X = p_Z^\omega,\qquad p_Y = p_Xp_Z = p_Z^{\omega+1},$$8 string and logical $$p_X = p_Z^\omega,\qquad p_Y = p_Xp_Z = p_Z^{\omega+1},$$9 is a pure-$X$00 string, so dominant $X$01 noise is not converted into logical bit flips. Foliating the XZZX surface code this way yields the XZZX cluster state, whose threshold exceeds $X$02 at high bias and is more than double that of the usual RHG cluster state under strong dephasing bias (Claes et al., 2022).

The concept also extends to magic-state and distillation ancillas. In the low-overhead dephasing-biased scheme of Brooks and Preskill, the ancilla resource is an encoded $X$03 state prepared in a repetition code tailored to $X$04-errors, using only Clifford gates that preserve the noise bias plus a non-Clifford $X$05. The acceptance probability for the encoded $X$06 gadget with odd $X$07 is

$X$08

and for bias greater than a factor of 10 the full scheme has lower overhead than standard constructions across a broad range of relevant noise rates (Webster et al., 2015).

Several limitations recur across the literature. Full bias is not always optimal: in QLDPC decoding, the full-bias model can reduce short loops most aggressively but may still perform worse than ancilla-only bias because the code is not tailored to pure dephasing (Bi et al., 29 Jun 2026). Standard foliation can destroy the very bias that a code was designed to exploit (Claes et al., 2022). In hardware-level realizations, suppressing one pair of logical channels often enhances another (Yu et al., 3 Jun 2026). More fundamentally, dynamical codes with two-qubit parity measurements cannot reduce their $X$09-detector graph to a disjoint union of repetition-code chains, even when a persistent symmetry exists (Setiawan et al., 2024).

Biased-noise ancillas are therefore best regarded as a co-design principle rather than a single object class. The ancilla, gate set, decoder, and code geometry must be matched so that the dominant physical error remains dominant and intelligible at the logical level. Where that co-design succeeds, the literature reports large effective-distance gains, substantial threshold improvements, reduced decoder pathologies, and, in some settings, order-of-magnitude logical-error reductions at experimentally relevant circuit noise.