A $\boldsymbol{2d \times d \times d}$ Spacetime Volume Implementation of a Logical S Gate in the Surface Code
Abstract: The logical S gate implemented via twist defect braiding in the surface code is one of the major sources of overhead in fault-tolerant quantum computing, since an S-gate correction is required in every logical T-gate teleportation. Existing logical S-gate implementations require spacetime volumes of (2d \times 2d \times d) or (2d \times 1.5d \times d), where $d$ is the code distance of the surface code. To the best of our knowledge, their circuit-level implementations have not yet been shown, hindering quantitative comparisons of fault distances and logical error rates. In this work, we provide these missing circuit-level implementations. Additionally, we propose a novel twist defect braiding protocol that reduces the spacetime volume to (2d \times d \times d). First, we construct an implementation of the proposed method using constant-length non-local gates, and then refine it to utilize only nearest-neighbor two-qubit gates on a square grid, without requiring additional two-qubit gate depth beyond that of standard syndrome extraction circuits. Through numerical simulations, we evaluate the fault distances and logical error rates for both existing and proposed methods. Our results show that, although the proposed method reduces the fault distance by one or three, its logical error rates remain comparable to those of existing methods at large code distances ((d \ge 5)) and at physical error rates near (p = 10{-3}). This demonstrates that the proposed method is promising for near-term fault-tolerant quantum computing.
Summary
- The paper introduces a novel twist defect braiding protocol to implement a logical S gate with a reduced 2d×d×d spacetime volume compared to previous methods.
- It details explicit Stim-level circuit implementations for both non-local and local gate architectures, offering comprehensive resource and error analysis.
- Numerical benchmarks confirm that the proposed method sustains competitive logical error rates, making it practical for near-term quantum hardware deployment.
Efficient Logical S Gate Implementation in the Surface Code with a Spacetime Volume
Introduction
The implementation of logical Clifford gates, particularly the S gate, in the surface code is central to scalable, fault-tolerant quantum computation. Surface codes are prominent due to high threshold, efficient decoding, and local interaction requirements. However, overhead associated with non-Pauli Clifford gates, such as the S gate executed via twist defect braiding, remains a practical limiting factor. As T gate costs decline owing to protocols like magic state cultivation, optimization of the S gate becomes crucial for the fault-tolerance stack. Existing S-gate constructions require large spacetime volumes and lack full circuit-level implementations, hampering comparative studies of error behavior and synchronization in modular architectures.
This paper addresses these gaps by proposing a spacetime implementation for stationary logical S gates in surface codes, accompanied by explicit Stim-level circuits. Comparative analysis covers prior leading approaches and delivers fault-distance and logical error-rate benchmarks, supporting the method's practicality for near-term hardware deployment (2604.13632).
Preliminaries: Surface Code and Code Deformation Frameworks
The analysis targets the rotated surface code, leveraging its local stabilizer measurement circuits and separation between logical boundaries. Logical information is encoded via string operators connecting disjoint X or Z boundaries at a metric distance . Measurement circuits are decomposed into two-qubit and single-qubit gates, and error propagation (hook errors) constrains the effective fault distance. The detector diagram formalism encodes the syndrome extraction and is a tool to identify which detectors flip for given physical error patterns.
Figure 1: Rotated surface code.
To implement logical gates, code deformation techniques (patch modifications and twist defect manipulation) are employed. These processes admit graphical representations in both 2D and 3D, illustrating the movement and braiding of twist defects and any introduced domain walls (regions with modified stabilizer structure, enabling specific Clifford operations).
Figure 2: Detector diagram of the surface code.
Figure 3: 2D defect diagram of patch rotation.
Figure 4: 3D defect diagram of the memory configuration. The time goes upward.
Figure 5: Defect diagrams including domain walls, depicted as a transparent yellow membrane.
Existing Methods and Their Limits
Bombín et al.
Bombín et al. introduced a twist-defect braiding protocol with spacetime overhead . Their approach maintains clear separation between twist defects and code boundaries during the entire protocol to preserve the code distance.
Figure 6: 2D defect diagram for Bombín's method.
Figure 7: 3D defect diagram of Bombín's method. The time goes upward.
Circuit-level details reveal that, although spatial separation is maintained, syndrome extraction induces hook errors during defect transport through the bulk. Required SWAP gates introduce synchronization challenges and additional error channels, ultimately reducing the effective fault distance to .
Figure 8: Stim circuit diagram for Bombín's method at the moment when the twist defect is braided across the surface code.
Gidney
Gidney proposed an improvement ( volume) informed by a careful analysis of Y-type error chain asymmetry: logical Y operators require more extended chains in the time direction than Euclidean arguments suggest. By performing an inplace Y basis measurement and exploiting this property, the protocol achieves full code distance for logical Y measurement, but the fault tolerance for stationary logical qubits cannot be improved below this volume.
Figure 9: 2D defect diagram of Gidney's method.
Figure 10: 3D defect diagram of Gidney's method. The time goes upward.
Existing Methodological Challenges
Both prior methods lack open, circuit-level implementations—making empirical validation and detailed resource estimates elusive. Additionally, the synchronization with standard syndrome extraction cycles is nontrivial due to variation in gate depth. There remains an open question whether spacetime volume can be fundamentally reduced further for stationary S gates without degrading logical error resilience.
Proposed S Gate Implementation
The core contribution is a twist-defect braiding protocol with reduced spacetime volume, detailed in detector-diagram and circuit representations for both architectures supporting non-local and strictly local two-qubit operations.
Figure 11: 2D defect diagram of the proposed method.
Figure 12: 3D defect diagram of the proposed method.
Protocol Summary
The protocol proceeds as follows:
- Spatial expansion from the X boundary, combined with twist defect braiding toward the boundary, induces the necessary logical operator transformation while forming a domain wall (realized using XXZZ stabilizers).
- Sequential Y measurements along the central column move the twist defect in a direction orthogonal to the prior expansion (now possible due to the domain wall).
- The code region is contracted, returning to the initial configuration, with the result that the logical X operator is mapped to logical Y, effecting the S gate up to stabilizer transformation.
Error chain analysis confirms that, despite apparent geometric proximity of certain features, Y-type chains require a minimum of errors (non-local gates) or errors (only local gates with CXSWAPs) to produce a logical error. The number of such reduced-weight chains is extremely small, thus negligibly impacting logical error probabilities for the regime .
Figure 13: The error chains in the proposed method. The blue (red) strings represent Z (X) error chains in the left panel. The green strings represent Y error chains in the right panel.
Circuit-level Implementations
Non-local Gates Variant
This version incorporates interaction-length flexibility (e.g., in neutral atom arrays). Syndrome extraction circuits and detectors are arranged to track modified stabilizer regions resulting from twist defect dynamics.
Figure 14: Detector and syndrome extraction diagrams for the proposed method using some constant-length non-local gates. The detector diagram specifies the stabilizer generators, while the syndrome extraction diagram describes the measurement patterns used for syndrome extraction. In the syndrome extraction diagram, the measurements are allowed to mutually anticommute.
Figure 15: Stim circuit for the proposed method at the moment when the twist defect is braided across the surface code.
Only-Local Gates Variant
For architectures limited to nearest-neighbor couplings (e.g., superconducting circuits), parallelogram tilings and CXSWAP-based schedules enable the full protocol using only local gates. The circuit oscillates between two stabilizer-tiling regimes (before and after CXSWAP application), guaranteeing correct syndrome propagation for all stabilizer shapes encountered.
Figure 16: Detector and syndrome extraction diagrams for the proposed method using only local gates.
Figure 17: Partial detector diagram for implementing the proposed method using only local gates (i) before using CXSWAP gates and (ii) after using CXSWAP gates.
Numerical Analysis: Fault Distance and Error Rates
Fault Distance Benchmarks
Rigorous benchmarking of the circuit-level Stim implementations quantifies the minimum-weight undetectable error chains for each method as a function of code distance 0:
| Method | Fault Distance |
|---|---|
| Bombín et al. | 1 |
| Gidney | 2 |
| Proposed (non-local gates) | 3 |
| Proposed (local gates) | 4 |
Figure 18: The set of detectors triggered by each error in the shortest error chain that limits the fault distance to 5 for Bombín's method.
Figure 19: The set of detectors triggered by each error in the shortest error chain that limits the fault distance to 6 for the proposed (NL) method.
Figure 20: The set of detectors triggered by each error in the shortest error chain that limits the fault distance to 7 for the proposed (L) method.
For the proposed methods, the reduction in minimum-allowed logical error chain length is a constant, independent of code scaling—this is a negligible decrement for practical code distances.
Logical Error Rate Comparison
Logical error rates under circuit-level depolarizing noise were obtained via Monte Carlo sampling, decoded with PyMatching, and cross-referenced with idle circuits of equivalent spacetime volume as a baseline. For 8 and realistic physical error rates (9), logical error rates for proposed methods are statistically indistinguishable from previous approaches and closely track those of idling circuits.
Figure 21: Numerical results of logical error rates under circuit-level noise. The logical error rates are shown for the logical operator transformations (a)~X0Y and (b)~Z1Z.
Figure 22: Comparison of all methods and the idling circuits that have the same spacetime volumes as each method. The circuits were initialized in the X basis.
Theoretical and Practical Implications
The explicit circuit-level availability of the 2 S gate protocol fills a critical gap in surface code literature, providing a platform for direct empirical comparison, systematic resource auditing, and hardware-constraint mapping. The method achieves a clear reduction in spacetime resource requirements without incurring a prohibitive increase in logical error probability or creating synchronization conflicts with standard syndrome extraction schedules. This is essential as T gate cost reductions drive the focus toward other Clifford resource overheads in future quantum computation stacks.
The modular decomposition into local and non-local gate implementations allows the protocol to be mapped to a wide variety of hardware platforms—neutral atoms, trapped ions, or superconducting qubits.
The extensibility of the twist defect braiding approach is notable; future research may apply similar geometric and code-deformation techniques to optimize other Clifford gates (e.g., reducing the 3 cost of logical H).
Conclusion
This work presents the first detailed circuit-level protocol for a logical S gate in the surface code with 4 spacetime volume, achieving near-optimal overhead for stationary logical qubits. The construction is versatile, accommodating hardware with and without non-local interactions, and robustly maintains logical error rates competitive with prior, more costly schemes, even at moderate code distances. The public release of full Stim-level implementations (2604.13632) enables immediate benchmarking and adoption in large-scale QEC pipelines.
Open directions include recovery of full code distance with further scheduling refinements, extending twist-based code deformations to other logical gates, and integrating with optimized, asynchronous syndrome extraction for multi-qubit architectures.
References
Refer to (2604.13632) for detailed citations, circuit code, and full data.
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Easy-to-Understand Summary of the Paper
What is this paper about?
This paper is about making a specific operation in a quantum computer—the logical S gate—faster and less resource-hungry when using a popular error-correcting method called the surface code. The authors show a new way to do this gate that uses less “space and time” on the chip, and they provide concrete circuits so others can test and compare it.
What are the authors trying to figure out?
The authors focus on three main goals:
- Can we perform the logical S gate using less spacetime volume (fewer qubits for fewer time steps) than existing methods?
- Can we write down the full, realistic circuits (not just diagrams) so people can measure reliability and compare methods fairly?
- Can we keep the error rate low even if we save space and time?
How do they do it? (Methods in simple terms)
To understand the approach, here are a few plain-language ideas:
- Surface code: Think of your qubits (the basic units of quantum information) arranged like a grid. The surface code constantly checks for errors by measuring patterns across the grid, helping keep the information safe.
- Code distance (d): This is like the “thickness” of the code’s shield. A bigger d means the code can handle more errors without failing.
- Logical S gate: This is a “phase twist” gate that changes how the logical qubit behaves. It’s needed a lot in quantum algorithms—especially because every logical T gate usually needs an S correction. So if S is expensive, your whole computation slows down.
- Spacetime volume: How many qubits you use multiplied by how many time steps you use them for. Smaller spacetime volume = less hardware/time cost.
- Twist defects and braiding: Imagine placing two “anchor points” on the grid where certain kinds of errors begin or end. By carefully moving these anchors around each other (this movement is called braiding), you can make a logical gate happen without touching the data directly—like tying a knot in the code’s fabric.
- Nearest-neighbor vs. non-local gates: Nearest-neighbor means each qubit can only talk to its direct neighbors (common in chips like superconducting devices). Non-local means some qubits can interact over a small, fixed distance (easier on some platforms like neutral atoms).
What the authors did:
- They took a known trick (braiding twist defects) and redesigned the path and timing to make the S gate use less spacetime volume.
- They first showed a version that assumes short, non-local interactions to keep things simple and fast.
- Then they refined it so it works using only nearest-neighbor interactions—by carefully scheduling gates and using CXSWAPs—without increasing the per-cycle two-qubit gate depth beyond standard surface-code measurements.
- They wrote full circuit-level implementations (using a tool called Stim) for their method and for two existing methods, so everyone can compare them fairly.
What did they find, and why does it matter?
Previous best methods:
- A method by Bombín and colleagues used a spacetime volume of 2d × 2d × d.
- A method by Gidney reduced this to 2d × 1.5d × d by using a clever property of how certain errors behave.
This paper’s new method:
- Reduces the volume further to 2d × d × d for a stationary logical qubit.
- Has two versions:
- With some constant-length non-local gates: effective protection (“fault distance”) is about d − 1.
- With only nearest-neighbor gates: effective protection is about d − 3.
Why that still works well:
- Even though the “fault distance” is slightly reduced, simulations show that the actual logical error rates (the chance the logical qubit is wrong) are about the same as the existing methods when:
- The code distance is at least 5 (d ≥ 5), and
- The physical error rate is around 1 in 1000 (p ≈ 10⁻³).
- In other words, the rare, specific error chains that cause the slight drop in fault distance don’t happen often enough to matter at these practical settings.
Why this is important:
- The S gate is used very often, especially because every T gate usually triggers an S correction. If you make the S gate cheaper, you make the whole quantum program faster and more practical.
- The authors also publish the actual circuits (openly available), making it easier for the community to test, tweak, and build on this work.
What does this mean for the future?
- Near-term quantum computers (which still have noticeable error rates) could run useful programs faster and with fewer resources using this improved S gate.
- There’s still room to improve: eventually, people will want to keep the smaller volume and also recover the full fault distance.
- The techniques for moving and braiding twist defects more efficiently might help with other gates too—like the H (Hadamard) gate—which is also common and currently more expensive than we’d like.
Key takeaways
- The paper introduces a new logical S gate method for the surface code that cuts spacetime volume to 2d × d × d.
- It provides full circuits (not just sketches) for both old and new methods so others can test them.
- Despite a small drop in fault distance, the actual logical error rates remain comparable for practical settings.
- This makes the S gate cheaper and helps reduce overall overhead in fault-tolerant quantum computing.
Knowledge Gaps
Knowledge gaps, limitations, and open questions
Below is a concise list of unresolved issues and open directions that emerge from the paper’s methods, analyses, and assumptions. Each item highlights something missing, uncertain, or left unexplored that a future study could address concretely.
- Lack of a formal proof of fault distance for the proposed geometries: only empirical upper bounds (via Stim’s shortest_graphlike_error and heuristic search) are provided, leaving the possibility of undetected, non-graphlike fault paths unresolved.
- Limited scope of heuristic search: search_for_undetectable_logical_errors was only executed up to distance 7 with pruning parameters; robustness of conclusions at larger d or different pruning settings remains unverified.
- Decoder-model mismatch: hyperedge correlations are decomposed to graph-like edges for MWPM; the impact of using a true hypergraph decoder (or BP+OSD/tensor-network decoders) on logical error rates and distance claims is not assessed.
- No threshold or finite-size scaling analysis: results are reported near p≈10⁻³ without extracting pseudo-thresholds, asymptotic exponents, or prefactors; the comparative scaling at lower/higher error rates is unknown.
- Limited noise modeling: only uniform depolarizing circuit-level noise is considered; performance under realistic, hardware-specific noise (e.g., biased dephasing, measurement bias, leakage, crosstalk, correlated spatial/temporal errors) is not evaluated.
- Sensitivity to Y-error asymmetry: the method exploits asymmetry of Y-type error growth; robustness against noise models that alter this asymmetry (e.g., Y-biased or strongly dephasing-biased channels, dominant measurement errors) is not quantified.
- Scheduling-induced hook errors: constant-length hook-error chains set fault-distance caps (d−1 for non-local, d−3 for local variant); it remains open whether alternative gate orderings, additional layers, flagging, or ancilla routing can eliminate these hook paths without increasing per-cycle depth.
- Precise gate-depth accounting: the claim of “no additional two-qubit gate depth per cycle” for the local variant is not backed by a gate-scheduling audit that includes pre-rotations for Y-basis measurements, CXSWAP decompositions, and potential contention with neighboring patches.
- CXSWAP practicality and cost: the local implementation relies on CXSWAP (often realized as three CNOTs); the resulting increase in two-qubit gate count, correlated error mechanisms, and impact on logical error rates are not quantified.
- Non-local gate assumptions: constant-length non-local two-qubit gates are assumed feasible; their fidelity, crosstalk footprint, and hardware-specific penalties (e.g., in superconducting vs neutral-atom platforms) are not analyzed or compared to SWAP-based routing alternatives.
- Domain wall via XXZZ checks: the paper assumes anti-commuting multi-Pauli product measurements; a concrete local circuit decomposition with commuting layers, ancilla reset/readout timing, and its effect on depth and hook errors is not provided.
- Exact constant factors in spacetime volume: while the leading term is 2d × d × d, the d ± O(1) rounds and per-step constants (including domain wall thickness and sequential-Y-measure timing) are not enumerated, hindering precise resource comparisons.
- Even/odd distance and edge-case handling: the procedure relies on a “middle column” and coordinates like 2.5; adaptations for even d, patch aspect ratios, and corner/edge effects are not fully specified.
- Integration into multi-patch layouts: expansion to 2d width and domain walls may disrupt neighboring patches; required separations, synchronization constraints, and effects on lattice-surgery pipelines are not quantified.
- System-level throughput and latency: while per-operation spacetime volume is reduced, end-to-end latency for repeated S corrections (e.g., inside magic-state cultivation pipelines) and achievable pipeline throughput are not analyzed.
- Comparison to alternative S implementations: no resource/error-rate comparison to S via gate teleportation (|Y⟩ ancilla) or other schemes (e.g., folded/transversal variants) is provided; decision boundaries where each approach is preferable are unclear.
- Robustness to measurement and reset imperfections: the heavy use of Y measurements/resets and sequential operations is not stress-tested under asymmetric measurement error rates or slow/low-fidelity resets.
- Decoder-aware optimization: no exploration of decoders tailored to domain walls/twist motion, time-asymmetric Y chains, or hook-prone regions (e.g., using weighted matching or region-specific priors) is presented.
- Formal verification of logical action: although diagrams track X→Y and Z→Z, a circuit-level stabilizer proof that the full protocol implements S (including all byproduct/frame updates) is not given.
- H-gate and broader Clifford extensions: the paper notes potential to reduce H-gate volume (typically 2d × 3d × d) but does not propose or analyze concrete protocols; generalization to other twist-based Clifford operations remains open.
- Fault-distance consequences at ultra-low p: the claim that reduced-distance chains are rare at p≈10⁻³ may not hold at p≪10⁻³; crossover behavior and when the (d−1)/(d−3) cap materially degrades performance are not studied.
- Hardware timing heterogeneity: assumptions of identical gate durations and full parallelism do not reflect many architectures; adaptations to limited parallelism (e.g., heavy-hex constraints) and timing skews are not explored.
- Leakage and non-Pauli error handling: the impact of leakage or coherent control errors on the proposed domain-wall and twist-braiding procedures (including leakage containment and removal) is unaddressed.
- Constant-factor improvements: opportunities to further lower constants in space or time (e.g., fewer sequential Y steps, thinner domain walls, reduced temporary expansion) are not systematically explored.
- Reproducibility beyond provided circuits: while Stim circuits are released, complete configuration details (e.g., seeds, exact code versions, decoding parameters, circuit variants) for all figures and claims are not exhaustively documented for independent replication.
These gaps delineate concrete next steps: prove or tighten fault-distance bounds; broaden noise/decoder evaluations; audit gate-depth and scheduling; assess hardware-specific feasibility; and extend/compare to other Clifford operations and architectures.
Practical Applications
Overview
This paper introduces a 2d × d × d spacetime-volume implementation of a logical S gate for the surface code via twist-defect braiding, provides the first circuit-level (Stim) implementations for existing methods, and offers two deployable variants:
- A non-local-gate variant (fault distance ≈ d − 1), suitable for platforms with constant-length non-local interactions.
- A local-only variant using CXSWAPs (fault distance ≈ d − 3) that preserves standard per-cycle two-qubit depth, easing synchronization with other surface-code operations.
It also quantifies performance under circuit-level noise and shows logical error rates comparable to existing approaches for d ≥ 5 at p ≈ 10⁻³, despite the small reduction in fault distance. Below are actionable applications and their feasibility.
Immediate Applications
The following items can be pursued now using the paper’s circuits, methods, and findings, particularly where physical error rates are ~10⁻³ and surface-code distances d ≥ 5.
- Implement lower-volume logical S gates in surface-code controllers
- Sectors: software, quantum hardware (control systems), integration.
- What: Integrate the 2d × d × d S-gate schedule (choose NL or local variant) into surface-code control firmware to reduce S-gate overhead in T-teleportation pipelines and improve synchrony across patches (no added two-qubit depth in the local variant).
- Tools/workflows: Use the provided Stim circuits; update patch-scheduling and syndrome-extraction microcode; add configuration flags to choose NL vs local schedules per hardware.
- Assumptions/dependencies: Nearest-neighbor square grid or constant-length non-local gates; stable measurement orderings; reliable CXSWAP implementations; decoder compatibility (e.g., PyMatching).
- Adopt the non-local (d − 1) variant on platforms with native long-range gates
- Sectors: neutral atoms, trapped ions (with shuttling/ion-transport), modular architectures.
- What: Deploy the constant-length non-local S-gate schedule where non-nearest-neighbor interactions are hardware-native to gain volume reduction with only a one-step fault-distance penalty.
- Tools/workflows: Platform-calibrated non-local entangling gates; Stim-based verification; hardware-in-the-loop simulation.
- Assumptions/dependencies: High-fidelity non-local gates; calibration of domain-wall (XXZZ) checks; measurement latencies not bottlenecking.
- Deploy the local (d − 3) CXSWAP-based variant on nearest-neighbor devices
- Sectors: superconducting qubits, silicon spin qubits.
- What: Use the local-only schedule that avoids extra two-qubit depth per syndrome cycle (improves synchronization and reduces idling), with demonstrated comparable logical error rate at practical d and p.
- Tools/workflows: CXSWAP scheduling templates; detector-diagram validation; device-specific hook-error assessments.
- Assumptions/dependencies: Reliable CXSWAPs; stable four-layer (or chosen) two-qubit gate ordering for syndrome extraction; cross-talk management.
- Update resource estimators and architecture studies to reflect reduced S-gate cost
- Sectors: architecture, resource estimation, cloud quantum services.
- What: Incorporate 2d × d × d S-gate volume into cost models for algorithmic run-time and qubit counts, particularly in designs with magic-state cultivation where S corrections dominate per-T overhead.
- Tools/workflows: Modify existing estimators (e.g., custom architecture notebooks, open-source resource tools) and simulator pipelines using the released Stim circuits.
- Assumptions/dependencies: Assumes p ~ 10⁻³ regime and d ≥ 5; decoder performance (PyMatching) close to modeled behavior.
- Standardized benchmarking of decoders and schedules with public circuits
- Sectors: academia, industry R&D, standards/benchmarking consortia.
- What: Use the paper’s Stim circuits to benchmark competing decoders (graph-like and ML-based), schedule orderings, and domain-wall implementations; compare Bombín, Gidney, and proposed methods on identical noise models.
- Tools/workflows: Stim + PyMatching; dataset generation of detector error models; scripts for Monte Carlo comparisons.
- Assumptions/dependencies: Uniform depolarizing noise model used in comparisons; availability of compute for large sampling.
- Synchronization-aware patch orchestration in lattice-surgery workflows
- Sectors: compiler/runtime, cloud quantum orchestration.
- What: Replace S-gate subroutines with the 2d × d × d local variant to keep two-qubit depth per cycle unchanged and simplify global timing across many patches (reduces idling-induced errors).
- Tools/workflows: Patch scheduler updates, syndrome-cycle alignment tooling; regression tests using detector diagrams.
- Assumptions/dependencies: Stable clocking of syndrome cycles and compatible measurement latencies.
- Education and workforce development using open circuits
- Sectors: education, training programs, academic labs.
- What: Build labs and teaching modules on code deformation, twist-defect braiding, Y-error asymmetry, and domain walls using the released Stim circuits and diagrams.
- Tools/workflows: Notebooks demonstrating detector diagrams; small-scale Monte Carlo exercises.
- Assumptions/dependencies: Basic familiarity with surface codes and Stim.
Long-Term Applications
The following require further research, scaling, hardware co-design, or lower physical error rates.
- Full-stack FT libraries of low-volume Clifford gates with code deformation
- Sectors: compiler/runtime, software stacks, cloud services.
- What: Develop a production library of twist-defect-based H/S/CNOT routines co-optimized with decoders and schedulers, reducing overall Clifford overhead at scale.
- Tools/workflows: Domain-wall-aware compilers; auto-scheduling that reasons about hook errors and detector geometry; verification against Stim.
- Assumptions/dependencies: Mature hardware with stable low p and high d; standardized control APIs.
- Hardware co-design to support constant-length non-local operations
- Sectors: hardware design (neutral atoms, trapped ions, modular superconducting).
- What: Architect qubit layouts and interconnects (e.g., shuttling pathways, photonic links, crossbars) that make the non-local S-gate variant practical at scale with high fidelity.
- Tools/workflows: Co-simulation of control and decoding; hardware-in-the-loop tests of domain-wall/XXZZ stabilization.
- Assumptions/dependencies: High-fidelity non-local gates, low-latency measurement and feed-forward.
- Extending twist-defect/domain-wall techniques to lower-cost logical H gates
- Sectors: software, hardware control, algorithm execution.
- What: Apply similar ideas to reduce the cost of the logical H gate (typically 2d × 3d × d), a frequent operation in many circuits, yielding larger end-to-end gains than S alone.
- Tools/workflows: New deformation schedules and detector-diagram validation; upgraded resource estimators.
- Assumptions/dependencies: New schedules that retain high fault distance or minimize hook-error impact.
- Compiler auto-selection between NL and local variants based on hardware and error budgets
- Sectors: compilers, orchestration.
- What: Build compilers that dynamically pick S-gate implementations (NL d−1 vs local d−3) based on device capabilities, calibration data, and algorithmic error budgets.
- Tools/workflows: Cost-model driven passes; feedback loops from runtime telemetry.
- Assumptions/dependencies: Reliable, continuously updated hardware performance profiles.
- Fault-distance restoration via hook-error–aware gate orderings or check designs
- Sectors: hardware control, decoding research.
- What: Investigate alternative two-qubit gate orderings, additional check layers, or hook-canceling tactics to restore fault distance while preserving volume gains.
- Tools/workflows: Stim-based search (shortest_graphlike_error/search_for_undetectable_logical_errors); experimental trials.
- Assumptions/dependencies: Hardware flexibility in gate scheduling and check composition.
- Standards and policy for fault-tolerance claims requiring circuit-level artifacts
- Sectors: policy, standards bodies, government programs.
- What: Define benchmarks and reporting standards that require circuit-level implementations (Stim circuits, detector diagrams, fault-distance evidence) for FT claims and procurement.
- Tools/workflows: Community-maintained benchmark suites; reference circuits for S/H/CNOT/T pipelines.
- Assumptions/dependencies: Cross-vendor participation; alignment on noise models and decoder baselines.
- Sector-level acceleration via reduced overheads in FT pipelines
- Sectors: healthcare (drug discovery), materials, energy, finance (risk, portfolio), logistics.
- What: Over time, lower Clifford overheads (and thus total spacetime volume) shorten time-to-solution for algorithms heavy in T gates and Clifford interleaves, improving feasibility of early quantum advantage.
- Tools/workflows: End-to-end resource estimates for domain-specific workloads incorporating the new S-gate costs.
- Assumptions/dependencies: Availability of large FT logical qubit counts; mature magic-state cultivation; stable low error rates.
- Cloud “logical qubit” services with transparent S-gate metrics and SLAs
- Sectors: cloud providers, end-users.
- What: Offer logical qubits with published S-gate schedules, volumes, and error rates; enable users to select implementations based on workload risk tolerance and performance targets.
- Tools/workflows: Telemetry dashboards; workload-aware selection of S-gate variants; billing tied to logical volume.
- Assumptions/dependencies: Mature FT infrastructure and monitoring; customer demand for parameterized FT services.
Cross-Cutting Assumptions and Dependencies
- Physical error rates near 10⁻³ and code distances d ≥ 5, where logical error rates of the proposed schedules match existing methods despite small fault-distance reductions.
- Square-grid architectures with either nearest-neighbor gates (local-only variant) or constant-length non-local interactions (non-local variant).
- Stable domain walls implemented via temporary XXZZ checks and consistent syndrome-extraction timing.
- Decoder compatibility (e.g., PyMatching), and the ability to ingest detector error models produced from the provided Stim circuits.
- Measurement and classical feed-forward latencies that do not invalidate cycle-level synchronization.
- Noise models used in the paper (uniform depolarizing) approximate the target hardware well enough, or are appropriately re-parameterized during adoption.
By adopting these implementations and benchmarks, hardware and software teams can immediately lower S-gate spacetime overheads in surface-code stacks, improve synchronization, and accelerate realistic assessments of fault-tolerant performance—while setting a foundation for longer-term reductions across the full Clifford library.
Glossary
- code deformation: A technique that temporarily changes a code’s stabilizers and boundaries to implement logical Clifford gates using local interactions. "via a technique known as code deformation"
- code distance: The minimum weight of a nontrivial logical operator; sets how many physical errors can be detected or corrected (denoted by d). "where is the code distance of the surface code."
- constant-length non-local gates: Fixed-range, non-nearest-neighbor two-qubit interactions used to reduce overhead in certain protocols. "using constant-length non-local gates"
- CXSWAP gates: Composite two-qubit operations that implement a CNOT together with a SWAP, useful for localizing interactions while moving information. "using CXSWAP gates"
- decoding graph: A graph representation used by decoders to infer error configurations from detector outcomes. "including the surface code, code deformation, decoding graph, detector diagram, and the defect diagram."
- defect diagram: A 2D/3D topological depiction of code boundaries, twist defects, and their motion through spacetime during code deformation. "The process of code deformation can be represented with defect diagrams."
- depolarizing errors: A noise model where each operation can suffer a uniformly random Pauli error. "uniform depolarizing errors are applied to every gate and every reset, measurement, and idling operation."
- detector diagram: A schematic of detectors (parity checks over measurement outcomes) used to visualize and track how circuit-level errors trigger syndromes. "A detector diagram is a useful framework for explicitly representing implementations with physical gates and monitoring the fault distance"
- detector error models: Decoder-ready representations of how errors trigger detectors, potentially including multi-detector correlations. "with hyperedges in the detector error models decomposed into graph-like edges using Stim."
- domain wall: A membrane-like boundary in spacetime that swaps X- and Z-type error chains as they pass through. "this exchange boundary is represented as a transparent yellow membrane, referred to as a domain wall."
- error-correction threshold: The critical physical error rate below which increasing the code distance reduces the logical error rate exponentially. "has a high error-correction threshold"
- fault distance: The effective code distance under circuit-level noise, limited by hook and scheduling effects in real circuits. "fault distances (i.e., the effective code distance under circuit-level noise)"
- graph-like edges: Pairwise detector connections used by matching decoders after decomposing higher-order correlations. "with hyperedges in the detector error models decomposed into graph-like edges using Stim."
- hook errors: Correlated multi-qubit errors caused by propagation during stabilizer measurement circuits that can lower fault distance. "Such propagated errors, known as hook errors, can reduce the effective code distance"
- hyperedges: Multi-detector correlations in an error model that connect more than two detectors and must be handled or decomposed for decoding. "with hyperedges in the detector error models decomposed into graph-like edges using Stim."
- idling errors: Errors accrued while qubits wait during extended depth or synchronization steps. "inducing additional idling errors on the data qubits."
- inplace Y measurement: A method to measure the logical Y operator on a patch without moving the logical qubit. "Perform an inplace Y measurement on the right surface code patch."
- lattice surgery: A technique that merges/splits surface-code patches to enact logical operations via joint measurements. "Split the surface code into two patches via lattice surgery."
- logical Hadamard (H) gate: The encoded Hadamard operation implemented via code deformation (e.g., patch rotation). "This operation, known as patch rotation, is essential for implementing the logical Hadamard (H) gate"
- logical S gate: The encoded phase gate, here realized by braiding twist defects in the surface code. "The logical S gate implemented via twist defect braiding in the surface code"
- logical T-gate teleportation: A protocol for applying T using teleportation with a magic state, often requiring an S correction. "since an S-gate correction is required in every logical T-gate teleportation."
- magic-state cultivation: An approach that reduces the resource cost of T states compared to traditional distillation. "as T gates become less expensive through magic-state cultivation"
- magic-state distillation: A process that purifies noisy magic states to enable high-fidelity non-Clifford gates. "because they involve magic-state distillation."
- nearest-neighbor interactions: Hardware-restricted connectivity where gates act only between adjacent qubits. "requires only nearest-neighbor interactions for syndrome extraction"
- patch rotation: A deformation procedure that rotates a surface-code patch, exchanging X and Z boundaries. "This operation, known as patch rotation, is essential for implementing the logical Hadamard (H) gate"
- PyMatching: A fast minimum-weight matching decoder used to process detector data and infer errors. "We employed PyMatching~\cite{Higgott2025sparseblossom} as a decoder"
- rotated surface code: A high-threshold surface-code variant with a rotated lattice layout and efficient decoding. "This paper focuses on a specific variant of the surface code known as the rotated surface code."
- space-like errors: Error chains primarily extended across space; in diagrams, domain walls can permit their passage. "allowing space-like errors to pass through it."
- spacetime volume: The space-by-space-by-time resource footprint of a logical operation. "reduces the spacetime volume to ."
- stabilizer codes: Quantum codes defined by commuting Pauli operators whose +1 eigenspace encodes logical qubits. "stabilizer codes are the most common framework for constructing QEC codes."
- Stim circuits: Circuit descriptions in the Stim framework for simulating detectors, errors, and decoding performance. "Our Stim circuits are publicly available on GitHub~\cite{stimcircuit_github}."
- syndrome extraction: The sequence of measurements and gates used to obtain stabilizer outcomes each cycle. "without requiring additional two-qubit gate depth beyond that of standard syndrome extraction circuits."
- time-like errors: Error chains primarily extended along the time direction; domain walls can allow them through depending on orientation. "allowing time-like errors to pass through it."
- transversal H gate: Applying H to many qubits simultaneously in a way consistent with code constraints, represented as a domain wall in time. "The transversal H gate corresponds to a domain wall slicing through time"
- twist defect: A point-like topological feature where X/Z boundaries interchange and Y-type chains can end. "the twist defects at which Y-type error chains terminate."
- twist-defect braiding: Moving twist defects around each other to enact logical Clifford gates such as S. "which we refer to as twist-defect braiding."
- XXZZ checks: Mixed-type stabilizer checks that effectively exchange X and Z error types across a domain wall. "temporarily introduce XXZZ checks"
- Y-type error asymmetry: The asymmetry in how Y errors propagate in space vs. time, impacting fault distance arguments. "through a careful analysis of Y-type error asymmetry"
- Y-type error chains: Connected sequences of Y errors whose endpoints can terminate at twist defects. "Y-type error chains terminate."
- two-qubit gate depth: The number of sequential layers of two-qubit gates per cycle, affecting idle time and errors. "the logical Y measurement on the square surface code inherently requires a two-qubit gate depth of five"
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