Heavy-Hex Superconducting Qubit Architecture

• Heavy-Hex superconducting qubit architecture is a planar, low-degree connectivity scheme derived from hexagonal tiling with added link qubits to minimize crosstalk and fabrication complexity.
• It supports bespoke quantum error-correcting codes—including 3CX surface, Bacon–Shor, and dynamic compass codes—tailored to its sparse connectivity for improved fault tolerance.
• The architecture enables high-fidelity two-qubit gates, efficient syndrome extraction, and logical entanglement protocols via transversal CX operations and lattice-surgery techniques.

The heavy-hex superconducting qubit architecture is a planar, low-degree connectivity scheme for solid-state quantum processors in which qubits are arranged on a graph derived from a hexagonal tiling, with degree constrained to 2 or 3 rather than the degree-4 or degree-6 connectivity typically assumed by square-lattice surface codes or triangular-lattice color codes. In current IBM quantum processors, this architecture is implemented with fixed-frequency transmons and nearest-neighbor couplings, and it has motivated a family of heavy-hex-specific quantum error-correcting constructions, including overlaid 3CX surface and Bacon–Shor codes, the dynamic compass code, and flag-assisted magic-state injection protocols (Hetényi et al., 2024, Lee et al., 15 Apr 2026, Kim et al., 2024).

1. Geometry and graph-theoretic structure

The heavy-hex lattice is constructed by starting from a regular hexagonal tiling and then placing an extra “link” qubit at the midpoint of every edge. Qubits originally on the hexagon vertices are “vertex qubits,” while the midpoint qubits are “link qubits.” In the resulting planar graph, interior vertex qubits have degree 3, boundary vertex qubits have degree 2, and all link qubits have degree 2; equivalently, the graph has maximum degree $\Delta = 3$. A $d \times d$ patch for a distance-$d$ construction contains $d^2$ vertex qubits and approximately $2d(d-1)$ link qubits (Hetényi et al., 2024).

A complementary description used in later work characterizes heavy-hex as a 3-valent graph obtained from the conventional hexagonal tiling by “thickening” each edge into a two-qubit link. The motivation for this graph-theoretic choice is architectural rather than purely coding-theoretic: a square-lattice surface code requires degree-4 connectivity, and a triangular-lattice color code requires degree-6 connectivity, both of which are more difficult to wire in planar superconducting technology (Lee et al., 15 Apr 2026).

Local adjacency can be written explicitly. For one truncated hexagon cell, with vertices $A,B,C$ and link qubits $1,2,3$, the nonzero adjacency entries are $A_{A,1}=A_{B,1}=A_{B,2}=A_{C,2}=A_{C,3}=A_{A,3}=1$, together with the symmetric reverse entries; all others are zero. This local pattern exemplifies the degree-2/3 constraint that distinguishes heavy-hex from a regular square grid (Hetényi et al., 2024).

The significance of this geometry is twofold. First, it enforces planarity and bounded valency at the hardware level. Second, it makes standard lattice-code embeddings nontrivial, since well-known fault-tolerant constructions are often formulated assuming denser nearest-neighbor connectivity.

2. Physical realization in superconducting transmon processors

In the heavy-hex implementations described in the cited work, the physical qubits are fixed-frequency transmons with $\omega_i/2\pi \sim 4.5$–$5.2\,\mathrm{GHz}$, anharmonicity $d \times d$0 to $d \times d$1, coherence times $d \times d$2–$d \times d$3, and $d \times d$4–$d \times d$5. Each coupled pair shares either a superconducting bus resonator or a direct capacitive link, yielding an effective exchange coupling $d \times d$6–$d \times d$7 (Hetényi et al., 2024).

Keeping only computational levels in the rotating frame, one standard effective Hamiltonian is

$d \times d$8

A closely related transmon description writes the local nonlinearity as $d \times d$9 in an anharmonic-oscillator model; both formulations encode the same architecture-level facts that the qubits are transmons and the interactions are nearest-neighbor on the heavy-hex graph (Hetényi et al., 2024, Kim et al., 2024).

Two-qubit gates are implemented by cross-resonance (CR) or echoed CR pulses that realize CX or CZ with typical fidelity $d$0 in the device model summarized for the 2024 entangled-logical-qubit experiment. In the dynamic-compass implementation on the IBM “Heron” 156-qubit processor (revision 3, ibm_pittsburgh), each edge is a capacitively coupled bus resonator of approximately $d$1, mediating a high-fidelity $d$2 CZ gate; readout resonators are multiplexed in groups of six and each resonator provides $d$3 signals for soft readout (Hetényi et al., 2024, Lee et al., 15 Apr 2026).

The central hardware rationale for heavy-hex is that planarity and low-degree connectivity minimize microwave-line crossings and lithographic complexity, improve fabrication yield, and reduce crosstalk between resonators. The architecture therefore exchanges denser direct connectivity for manufacturability and robustness in a planar multi-chip module (Hetényi et al., 2024).

3. Heavy-hex-tailored quantum error-correcting codes

Because the heavy-hex graph is sparse, error-correcting codes must be adapted to it rather than transplanted directly from square-lattice layouts. Three representative constructions appear in the cited literature: an overlaid 3CX surface code and Bacon–Shor code, a heavy-hex subsystem code generalized into the dynamic compass code, and flag-assisted adaptations used for magic-state injection (Hetényi et al., 2024, Lee et al., 15 Apr 2026, Kim et al., 2024).

Construction	Heavy-hex realization	Quantitative note
3CX surface code	Data qubits on the vertex sublattice; 4-body $d$4 or $d$5 plaquettes plus 2-body boundary checks	Minimum-weight perfect-matching threshold $d$6 under circuit-level noise
Bacon–Shor code	Data qubits on the link sublattice in an effective square grid; 2-qubit horizontal $d$7 and vertical $d$8 gauge checks	Distance $d$9; pseudo-threshold $d^2$0
Dynamic compass code	Weight-4 $d^2$1-checks and weight-2 $d^2$2-checks on a heavy-hex patch with a 4-step schedule	Threshold $d^2$3; distance-5 experiment used 49 data qubits and 36 ancillas

In the 3CX surface code, the $d^2$4 array of vertex qubits serves as the data layer, with ancilla qubits for each plaquette on the same vertex sublattice and a standard $d^2$5–$d^2$6 interleaved schedule. In the Bacon–Shor construction, the link qubits form an effective square grid in which each heavy-square edge hosts one link qubit; the gauge checks are two-qubit $d^2$7 parities on horizontal neighbor pairs and two-qubit $d^2$8 parities on vertical neighbor pairs, and these can be measured in one parallel round. Logical operators are $d^2$9 over any one full row of data qubits and $2d(d-1)$0 over any one full column, with distance $2d(d-1)$1 (Hetényi et al., 2024).

The dynamic compass code is a subsystem code tailored to heavy-hex connectivity. Its plaquettes comprise weight-4 $2d(d-1)$2-checks, with four data qubits at the corners of a distorted rhombus spanning two hexagonal faces, and weight-2 $2d(d-1)$3-checks linking pairs of data qubits along single heavy edges. For the distance-$2d(d-1)$4 implementation, a logical patch contained 49 data qubits arranged in an approximate $2d(d-1)$5 hex layout, with ancilla qubits placed on alternating edges so that every check operator could be measured using only nearest-neighbor couplings (Lee et al., 15 Apr 2026).

These constructions show that heavy-hex does not merely host a single adapted code. Rather, its geometry supports multiple code families with different threshold behavior, operator geometry, and circuit schedules.

4. Overlay coding and entangled logical qubits

A distinctive heavy-hex result is the simultaneous embedding of two distance-$2d(d-1)$6 topological codes on disjoint qubit sets of the same chip: the 3CX surface code on vertices and the Bacon–Shor code on links. Because the vertex and link qubit sets are disjoint, unused qubits of one code can execute the other, so that two logical qubits are implemented “on top of each other” (Hetényi et al., 2024).

This overlay enables fault-tolerant entangling primitives. By choosing appropriate products of stabilizers for 3CX or gauges for Bacon–Shor, a transversal qubit-by-qubit CX maps $2d(d-1)$7 and $2d(d-1)$8, thereby enacting a logical $2d(d-1)$9 for odd $A,B,C$0. In parallel, lattice-surgery-style merge measurements of logical $A,B,C$1 or $A,B,C$2 are available by introducing extra ancillas between the two patches and measuring edge parities in one stabilizer round (Hetényi et al., 2024).

The logical-Bell-state preparation protocol proceeds in four explicit steps. First, vertex qubits are prepared in $A,B,C$3 and link qubits in $A,B,C$4, which is equivalent to preparing $A,B,C$5 Bell pairs. Second, one round of merged check measurements completes logical-Bell preparation. Third, $A,B,C$6 additional rounds of single-code stabilizer extraction are executed for error correction. Fourth, the two logical qubits are measured either by disentangling them through a second transversal $A,B,C$7 and reading out in the Bell basis, or by simultaneous lattice-surgery $A,B,C$8 and $A,B,C$9 checks followed by individual logical readout (Hetényi et al., 2024).

In circuit-level depolarizing-noise simulations, the resulting pseudo-thresholds are at $1,2,3$0–$1,2,3$1 without post-selection, with subthreshold scaling $1,2,3$2. With additional boundary-matching post-selection, the even-$1,2,3$3 scaling improves to $1,2,3$4 at modest yield loss. On the 133-qubit ibm_torino device, physical error rates were approximately single-qubit $1,2,3$5, two-qubit $1,2,3$6, and readout $1,2,3$7; code distances up to $1,2,3$8 and stabilizer rounds up to $1,2,3$9 were run, and even at $A_{A,1}=A_{B,1}=A_{B,2}=A_{C,2}=A_{C,3}=A_{A,3}=1$0 the logical $A_{A,1}=A_{B,1}=A_{B,2}=A_{C,2}=A_{C,3}=A_{A,3}=1$1 survival exceeded $A_{A,1}=A_{B,1}=A_{B,2}=A_{C,2}=A_{C,3}=A_{A,3}=1$2. For the $A_{A,1}=A_{B,1}=A_{B,2}=A_{C,2}=A_{C,3}=A_{A,3}=1$3 logical Bell state, the reported fidelity was approximately $A_{A,1}=A_{B,1}=A_{B,2}=A_{C,2}=A_{C,3}=A_{A,3}=1$4 without post-selection and approximately $A_{A,1}=A_{B,1}=A_{B,2}=A_{C,2}=A_{C,3}=A_{A,3}=1$5 with post-selection, with CHSH values approximately $A_{A,1}=A_{B,1}=A_{B,2}=A_{C,2}=A_{C,3}=A_{A,3}=1$6 and $A_{A,1}=A_{B,1}=A_{B,2}=A_{C,2}=A_{C,3}=A_{A,3}=1$7 respectively (Hetényi et al., 2024).

The same work reports that the nonplanar coupling between the qubits allows simultaneous measurement of the logical $A_{A,1}=A_{B,1}=A_{B,2}=A_{C,2}=A_{C,3}=A_{A,3}=1$8, $A_{A,1}=A_{B,1}=A_{B,2}=A_{C,2}=A_{C,3}=A_{A,3}=1$9, and $\omega_i/2\pi \sim 4.5$0 observables, and that Bell’s inequality was violated both for the $\omega_i/2\pi \sim 4.5$1 case with post-selection and for the $\omega_i/2\pi \sim 4.5$2 instance using only quantum error correction. This is significant because it links an architecture-level connectivity constraint directly to a logical-level entanglement primitive.

5. Syndrome extraction, noise characterization, and decoder tailoring

The dynamic compass code uses a 4-step repeating syndrome-extraction schedule. In steps 1 and 3, all weight-4 $\omega_i/2\pi \sim 4.5$3-checks are measured simultaneously; in steps 2 and 4, two complementary subsets of the weight-2 $\omega_i/2\pi \sim 4.5$4-checks are measured. For each $\omega_i/2\pi \sim 4.5$5-check, the ancilla is prepared in $\omega_i/2\pi \sim 4.5$6, CZ gates are applied to up to four data qubits using two CZs per sub-step by routing, then an $\omega_i/2\pi \sim 4.5$7 gate is applied, followed by measurement in the $\omega_i/2\pi \sim 4.5$8 basis and reset. Representative timings are CZ $\omega_i/2\pi \sim 4.5$9, $5.2\,\mathrm{GHz}$0, and measurement plus reset $5.2\,\mathrm{GHz}$1. By interleaving the four sub-steps, a full $5.2\,\mathrm{GHz}$2 syndrome round requires only two sequential mid-circuit-measurement layers, which minimizes data-qubit idle times (Lee et al., 15 Apr 2026).

The heavy-hex coupler pattern itself constrains the schedule: simultaneous measurement of all $5.2\,\mathrm{GHz}$3-checks in a single layer is forbidden because some checks would collide. This device-specific restriction is a direct instance of how graph structure shapes fault-tolerant control flow (Lee et al., 15 Apr 2026).

For uniform circuit-level noise, the reported threshold is

$5.2\,\mathrm{GHz}$4

with phenomenological logical-error scaling

$5.2\,\mathrm{GHz}$5

where $5.2\,\mathrm{GHz}$6 is the physical error rate. A central heavy-hex advantage here is that limited degree constrains error propagation: any single fault during a CZ can feed into at most two syndrome detectors, producing an “edge-like” error compatible with efficient minimum-weight matching. The three-valent nodes also reduce idle-qubit dephasing because fewer cross-couplings run adjacent to any resonator (Lee et al., 15 Apr 2026).

Noise mitigation in this setting is explicitly device-aware. Averaged Circuit Eigenvalue Sampling (ACES) is used to learn a layer- and gate-specific Pauli channel for every CZ, idling period, reset, and mid-circuit measurement in the 4-step schedule; ACES requires approximately 30 minutes of QPU time to build a scalable, high-fidelity noise model. Supplying ACES data to a matching decoder such as BeliefMatching reduces logical error rates by approximately $5.2\,\mathrm{GHz}$7 in the $5.2\,\mathrm{GHz}$8 basis and approximately $5.2\,\mathrm{GHz}$9 in the $d \times d$00 basis relative to naive calibration-snapshot models. Soft decoding then uses each readout resonator’s $d \times d$01 point to fit a 3-component Gaussian mixture model for $d \times d$02, $d \times d$03, and leakage $d \times d$04, and updates the shot-specific flip probability according to

$d \times d$05

Measurements with $d \times d$06, typically $d \times d$07, are flagged as leaked and excluded by post-selection; rejecting $d \times d$08 of shots yields an additional $d \times d$09–$d \times d$10 drop in logical error rate. The complete noise-informed pipeline yields up to $d \times d$11 improvement in the logical error rate for the distance-5 experiment (Lee et al., 15 Apr 2026).

6. Flag qubits, biased noise, and magic-state injection

A separate line of heavy-hex adaptation concerns magic-state injection. Because no heavy-hex vertex has degree 4, a weight-4 stabilizer cannot be coupled directly to one syndrome qubit. The stated heavy-hex solution is to interpose flag qubits so that data-to-syndrome interactions become data $d \times d$12 flag and flag $d \times d$13 syndrome chains in symmetric order. Flag qubits are measured immediately after the stabilizer cycle, and their readout is used in Chamberland–Reichardt-style flag-fault-tolerant decoding so that no weight-2 errors can masquerade as no-error in a distance-$d \times d$14 code (Kim et al., 2024).

The same work models the hardware with a biased Pauli channel, motivated by the statement that real superconducting qubits typically have $d \times d$15, leading to $d \times d$16-biased decoherence. For a single-qubit gate with total error probability $d \times d$17 and bias parameter $d \times d$18,

$d \times d$19

For two-qubit noise with total probability $d \times d$20, the error weights are redistributed to favor $d \times d$21-type faults, and higher $d \times d$22 reduces logical $d \times d$23 errors preferentially; the text notes that codes like XZZX can exploit this bias (Kim et al., 2024).

The magic-state injection protocol is an “inject then extend” procedure. In Stage I, a physical

$d \times d$24

is placed on one corner data qubit of a distance-$d \times d$25 patch; the rest of the first row or column is initialized in $d \times d$26 or $d \times d$27 to match logical $d \times d$28 and $d \times d$29, using one of four region-division strategies: down-triangle, right-triangle, down-square, or right-square. Two rounds of stabilizer plus flag measurement are then performed, and shots are post-selected on all syndrome bits and all flags equal to zero. In Stage II, additional data qubits are initialized around the $d \times d$30 patch to reach $d \times d$31, $d \times d$32 rounds of full stabilizer extraction are run on the enlarged patch, and minimum-weight perfect matching is used for correction; all data qubits are then measured in the $d \times d$33 or $d \times d$34 basis to estimate logical fidelity (Kim et al., 2024).

The reported resource count for a $d \times d$35 example is approximately $d \times d$36 data qubits, syndrome qubits roughly equal to data in a heavy-hex patch at about $d \times d$37, and a flag-qubit overhead of 10–20\%. The logical infidelity is defined as

$d \times d$38

with injection fidelity $d \times d$39. Under the paper’s numerics, heavy-hex with flags gives $d \times d$40 at $d \times d$41 and $d \times d$42, versus lattice $d \times d$43 under the same physical error. The optimized heavy-hex recipe combines a ZXXZ-type XZZX code, down-triangle initialization, and the two-stage extension strategy; at $d \times d$44 and $d \times d$45, the ZXXZ heavy-hex construction yields $d \times d$46 versus $d \times d$47 for XZZX type and approximately $d \times d$48 for the standard surface code, while the two-stage strategy gives an approximately $d \times d$49 improvement in success-verdict rate at fixed overall fidelity (Kim et al., 2024).

7. Architectural trade-offs, recurring misconceptions, and research significance

The heavy-hex architecture is defined by a clear engineering trade-off. Its advantages are a high-yield, manufacturable planar architecture with very low crosstalk between qubits, degree-3 connectivity sufficient to host both a surface-code-like construction and a Bacon–Shor code, and support for transversal logical $d \times d$50 together with lattice surgery for logical-Bell preparation, measurement, and entanglement verification. Its limitations are equally explicit: sparse connectivity forces many next-nearest-neighbor gates, including the cited example of a next-nearest-neighbor CX synthesized from four physical CXs, which increases circuit depth; the resulting thresholds are relatively low, around $d \times d$51–$d \times d$52 in the overlay-Bell protocols; and the Bacon–Shor component has only a pseudo-threshold and benefits only modestly from increased $d \times d$53 (Hetényi et al., 2024).

A recurrent misconception is that degree-3 heavy-hex connectivity is simply too sparse for practical topological fault tolerance. The reported results do not support that simplification. Heavy-hex has been used to realize a surface code and a Bacon–Shor code on the same 133-qubit processor, to run code distances up to $d \times d$54 with five rounds of stabilizer measurements, to implement a distance-5 dynamic compass code with 49 data qubits and 36 ancillas on a 156-qubit Heron processor, and to support a flag-assisted magic-state injection workflow explicitly optimized for biased superconducting noise (Hetényi et al., 2024, Lee et al., 15 Apr 2026, Kim et al., 2024).

At the same time, the architecture does not erase the cost of reduced connectivity. Sparse graphs must be compensated by tailored check geometries, specialized schedules, code overlays, flag subcircuits, and decoder customization. This suggests that heavy-hex is best understood not as a generic substrate for transplanting square-lattice methods, but as a hardware-specific regime in which fabrication robustness and planar simplicity are leveraged through bespoke QEC design. Within the cited results, that regime already supports logical entanglement with Bell-inequality violation, a true threshold in the dynamic compass setting, and optimized state-injection strategies under biased noise (Hetényi et al., 2024, Lee et al., 15 Apr 2026, Kim et al., 2024).