Fermionic Color Code Processors

• Fermionic color code processors are fault-tolerant quantum architectures that combine topological color codes with fermionic degrees of freedom such as Majorana zero modes.
• They implement logical operations via techniques like lattice surgery, twist defects, and anyonic braiding, leveraging both qubit and fermion resources.
• These processors integrate hybrid qubit–fermion couplings and concatenated code constructions to achieve high encoding rates with controlled stabilizer weights.

Searching arXiv for relevant papers on fermionic color codes, Majorana color codes, twist-defect color-code processors, and related architectures. Fermionic color code processors denote a family of fault-tolerant architectures in which color-code structure is combined with fermionic degrees of freedom, including Majorana zero modes, physical fermions, and fermionic anyons. The literature uses the phrase across several closely related settings: scalable Majorana-hardware realizations of open-boundary color codes, intrinsically fermionic color codes whose logical operators satisfy Majorana algebra, twist-defect processors obtained from the color code’s anyon symmetries, hybrid qubit–fermion processors, and higher-dimensional chiral extensions with single-shot features (Litinski et al., 2017, Li, 2017, Kesselring et al., 2018, Schuckert et al., 2024, Lee et al., 22 Sep 2025). A plausible implication is that the subject is best understood as a design space rather than a single canonical code family.

1. Architectural scope and code-theoretic setting

One line of work implements ordinary color-code quantum computation on fermionic hardware. In a representative architecture, networks of voltage-controlled Majorana Cooper pair boxes supply hexagonal-cell physical qubits, while a triangular open-boundary $6.6.6$ color code provides the fault-tolerant layer. In that setting, the topologically protected gate set available from Majorana hardware coincides with the Clifford gates, and the color code supplies ancilla-free syndrome readout together with logical $T$-gates via magic-state distillation (Litinski et al., 2017).

A second line of work is intrinsically fermionic. In the triangular Majorana color code of the fermionic-computation proposal, one places one physical Majorana mode $\gamma_j$ on each vertex of a two-dimensional three-colorable lattice, defines plaquette stabilizers as products of Majoranas, and obtains a logical mode because the total number of vertices is odd. The encoded information is then a logical Majorana mode rather than a conventional logical qubit, and the native logical gate set is organized around exchanges, parity measurements, and magic-state injection for fermionic universality (Li, 2017).

A third line treats Majorana color codes as concatenated constructions. In that framework, Majorana surface codes on three-colorable tilings are concatenated with small Majorana fermion codes $[[n_m,k,d_m]]_m$, producing new code families with reduced space overhead and modified stabilizer weight. The construction explicitly relates tetrons, hexons, and higher-order Majorana color codes, and emphasizes Pauli-product measurements and lattice surgery as the computational primitives (Litinski et al., 2018).

A fourth line starts from weakly self-dual CSS qubit color codes and maps them directly to fermionic codes by the substitutions $X_i\to\gamma_i$ and $Z_i\to\tilde\gamma_i$. In that setting the fermionic color code corrects both phase and loss errors, supports transversal Clifford gates in fermionic language, and interfaces with qubit color codes through transversal qubit–fermion controlled operations. The same framework is then used for qubit-controlled fermionic time evolution and fermionic fast Fourier transform subroutines (Schuckert et al., 2024).

A fifth line embeds the processor into a larger fault-tolerant stack. In the fermion-to-fermion LDPC proposal, a high-rate fermionic LDPC memory transfers logical fermions to two-dimensional fermionic color-code processor blocks by lattice surgery; logical operations are performed on the processor, and the state can be returned to memory without breaking fermionic parity or reducing distance. This identifies the processor as a locality-optimized compute module rather than as the sole storage layer (Xu et al., 21 Aug 2025).

2. Topological data, three-fermion layers, and twist defects

A central topological description views the two-dimensional color code as two copies of the three-fermion model $3F$. One copy has label set

$\mathcal C^{3F}=\{1,f_1,f_2,f_3\},$

with fusion

$f_i\times f_i=1,\qquad f_i\times f_j=f_k$

for $\{i,j,k\}$ a permutation of $T$0, topological spins

$T$1

and braiding

$T$2

For one copy, the modular data are

$T$3

The doubled theory $T$4 contains $T$5 anyons $T$6, and one finds exactly the $T$7 color-code excitations. Fusion and braiding are inherited layerwise,

$T$8

so the color-code modular data are

$T$9

This gives a fermionic description of the color code’s excitations and makes its symmetry structure unusually explicit (Kesselring et al., 2018).

The corresponding anyon-symmetry group is

$\gamma_j$0

of order $\gamma_j$1. A convenient generating set is $\gamma_j$2, $\gamma_j$3, and $\gamma_j$4: $\gamma_j$5 swaps two colors, $\gamma_j$6 swaps two Pauli labels, and $\gamma_j$7 implements color–Pauli duality via the “domino” wall. Each symmetry $\gamma_j$8 corresponds to a transparent domain wall in the color-code lattice, and each endpoint of an open $\gamma_j$9-wall is a twist $[[n_m,k,d_m]]_m$0 of type $[[n_m,k,d_m]]_m$1. Up to gauge, the $[[n_m,k,d_m]]_m$2 twists decompose into $[[n_m,k,d_m]]_m$3 conjugacy classes $[[n_m,k,d_m]]_m$4–$[[n_m,k,d_m]]_m$5 (Kesselring et al., 2018).

Twists admit local stabilizer descriptions. For a single twist $[[n_m,k,d_m]]_m$6 at plaquette $[[n_m,k,d_m]]_m$7,

$[[n_m,k,d_m]]_m$8

where $[[n_m,k,d_m]]_m$9 is the minimal closed Wilson loop of Pauli operators encircling $X_i\to\gamma_i$0, chosen so that $X_i\to\gamma_i$1 commutes with all other stabilizers. On the $X_i\to\gamma_i$2 lattice, a $X_i\to\gamma_i$3-twist at a valence-$X_i\to\gamma_i$4 plaquette has

$X_i\to\gamma_i$5

On the $X_i\to\gamma_i$6 lattice, a $X_i\to\gamma_i$7-twist at a valence-$X_i\to\gamma_i$8 plaquette has

$X_i\to\gamma_i$9

The defect Hamiltonian is

$Z_i\to\tilde\gamma_i$0

This topological picture is directly computational. Twists can be created and moved by single-qubit and $Z_i\to\tilde\gamma_i$1-$Z_i\to\tilde\gamma_i$2-$Z_i\to\tilde\gamma_i$3-$Z_i\to\tilde\gamma_i$4 Pachner-move measurements; braiding $Z_i\to\tilde\gamma_i$5-type twists implements a subgroup of the Clifford group determined by $Z_i\to\tilde\gamma_i$6; braiding two color-swap twists yields a logical Controlled-$Z_i\to\tilde\gamma_i$7 on the encoded qubit pair; and the summary statement is that braiding these defects implements the full Clifford group with distance-$Z_i\to\tilde\gamma_i$8 protection, where the effective distance is set by twist separation or twist-to-boundary separation. The stated threshold is $Z_i\to\tilde\gamma_i$9, against a color-code baseline of $3F$0 (Kesselring et al., 2018).

3. Code constructions and logical encodings

In the triangular Majorana color code, one starts from a two-dimensional three-colorable lattice such as the $3F$1 Archimedean lattice, removes one vertex so that the total number of vertices is odd, and places one physical Majorana mode $3F$2 on each vertex $3F$3. For each plaquette $3F$4,

$3F$5

with all $3F$6 even, so $3F$7 is Hermitian and $3F$8. Because any two faces share an even number of vertices,

$3F$9

Since the number of vertices is $\mathcal C^{3F}=\{1,f_1,f_2,f_3\},$0, there are $\mathcal C^{3F}=\{1,f_1,f_2,f_3\},$1 independent stabilizers and one logical mode

$\mathcal C^{3F}=\{1,f_1,f_2,f_3\},$2

which commutes with all $\mathcal C^{3F}=\{1,f_1,f_2,f_3\},$3 and satisfies $\mathcal C^{3F}=\{1,f_1,f_2,f_3\},$4. Boundary-supported logical strings $\mathcal C^{3F}=\{1,f_1,f_2,f_3\},$5 connect distinct color boundaries and obey

$\mathcal C^{3F}=\{1,f_1,f_2,f_3\},$6

so the logical algebra is explicitly Majorana rather than Pauli (Li, 2017).

A closely related fermionic color-code construction begins with a weakly self-dual CSS qubit color code, with face stabilizers

$\mathcal C^{3F}=\{1,f_1,f_2,f_3\},$7

and replaces $\mathcal C^{3F}=\{1,f_1,f_2,f_3\},$8, $\mathcal C^{3F}=\{1,f_1,f_2,f_3\},$9. The fermionic stabilizers become

$f_i\times f_i=1,\qquad f_i\times f_j=f_k$0

while the odd-weight logical Majoranas are

$f_i\times f_i=1,\qquad f_i\times f_j=f_k$1

For the triangular family, the code distance $f_i\times f_i=1,\qquad f_i\times f_j=f_k$2 is odd, the number of physical fermionic sites is

$f_i\times f_i=1,\qquad f_i\times f_j=f_k$3

and the code can correct up to $f_i\times f_i=1,\qquad f_i\times f_j=f_k$4 loss or phase errors (Schuckert et al., 2024).

In processor-oriented formulations, each vertex $f_i\times f_i=1,\qquad f_i\times f_j=f_k$5 of a three-colorable tiling carries a complex fermion $f_i\times f_i=1,\qquad f_i\times f_j=f_k$6, equivalently split into two Majoranas

$f_i\times f_i=1,\qquad f_i\times f_j=f_k$7

Rough boundaries support endpoints of $f_i\times f_i=1,\qquad f_i\times f_j=f_k$8-type logical strings, smooth boundaries support $f_i\times f_i=1,\qquad f_i\times f_j=f_k$9-type logical strings, and a single logical complex fermion is encoded by two anticommuting logical Majoranas $\{i,j,k\}$0 and $\{i,j,k\}$1 running across the patch. For each face $\{i,j,k\}$2,

$\{i,j,k\}$3

If $\{i,j,k\}$4 is the face–vertex incidence matrix, then

$\{i,j,k\}$5

and one checks $\{i,j,k\}$6 because any two faces share an even number of vertices. The code distance is the minimum weight of any odd-parity nullspace vector; in a regular $\{i,j,k\}$7 rhombus patch of the $\{i,j,k\}$8 fermionic color code, the distance equals the side length (Xu et al., 21 Aug 2025).

4. Logical operations, lattice surgery, and universality

The fermionic gate set in direct-Majorana color-code proposals is built from code deformations and parity measurements. For Majorana modes $\{i,j,k\}$9, the phase gate is

$T$00

The exchange gate $T$01 is realized by state-transfer subcircuits, and the non-Clifford gate

$T$02

is obtained by magic-state injection using a $T$03-mode magic state and adaptive $T$04-gates. Two forms of lattice surgery measure or prepare $T$05 on neighboring triangles, and a four-mode parity projection $T$06 is performed with an $T$07-face patch. The stated outcome is a universal, parity-preserving gate set on logical Majoranas (Li, 2017).

In Majorana-surface and Majorana-color-code architectures, all logical Clifford gates are implemented with zero time overhead by Pauli-product measurements. The basic hardware measurement is a local $T$08-Majorana parity, and arbitrary $T$09-qubit Pauli-product measurements are assembled through a GHZ-ancilla protocol using tetrons. At the fault-tolerant level, the same logic is implemented by lattice surgery on code patches, still requiring only local few-Majorana parity measurements. The formalism also introduces twist defects in Majorana fermion surface codes and adapts twist-based lattice surgery to fermionic codes (Litinski et al., 2018).

Hybrid fermionic color codes admit transversal logical operations written directly in fermionic language. For two logical blocks $T$10, the logical braid is

$T$11

and the fermionic controlled-$T$12 is

$T$13

The qubit–fermion controlled-$T$14 interface is

$T$15

These operations preserve the stabilizers by symmetry, and the qubit–fermion coupling is used to teleport qubit $T$16-gates onto the fermion block. The same framework presents a full universal gate set consisting of $T$17, $T$18, $T$19, $T$20, $T$21, together with qubit $T$22, $T$23, $T$24 and the hybrid $T$25 (Schuckert et al., 2024).

When fermionic color codes are used as processors in a memory–processor hierarchy, lattice surgery transfers logical fermions between code blocks. To move a logical fermion from a memory block $T$26 to a processor block $T$27, one measures

$T$28

applies a conditional logical $T$29, then measures

$T$30

followed by conditional $T$31 gates. The fault-tolerant implementation merges the patches along the support of their $T$32-type logicals, introduces $T$33 ancilla complex fermions, adds seam checks $T$34 and gauge checks $T$35, and repeats syndrome measurement for at least $T$36 rounds so that the joint parity is measured without reducing code distance (Xu et al., 21 Aug 2025).

5. Physical implementations and syndrome extraction

In Majorana-Cooper-pair-box hardware, the elementary qubit is built from two superconducting islands carrying four Majorana zero modes $T$37. For one island,

$T$38

where $T$39 is the island charge, $T$40 its phase, $T$41 the charging energy, and $T$42 the Josephson coupling. In the Majorana regime $T$43, the effective low-energy Hamiltonian reduces to a two-level system $T$44, with

$T$45

This provides an explicit Pauli–Majorana map at the hardware level (Litinski et al., 2017).

The corresponding code architecture uses a triangular open-boundary $T$46 color code of odd distance $T$47. Each vertex is a physical qubit, each face is a hexagon or rectangle, and the stabilizer generators are

$T$48

On colored boundaries, omitting the opposite-color stabilizers yields logical boundary strings such as $T$49 and $T$50 along a red edge. Single-qubit $T$51 and $T$52 are implemented by Majorana braiding, while CNOT is realized by parity measurements with one ancilla prepared in $T$53 (Litinski et al., 2017).

A notable feature of that architecture is ancilla-free syndrome extraction. For a six-qubit $T$54-stabilizer, the six surrounding hex cells move the relevant Majoranas onto a central island, and the total $T$55-Majorana parity

$T$56

is read out dispersively through an LC resonator. The same cell can be reused for $T$57-stabilizers by pre- and post-Hadamard rotations. The stated threshold under pure Pauli noise with ancilla-free readout is $T$58. The nanowire layout has hex-cell pitch $T$59, qubit footprint $T$60 per cell, Majorana movement times $T$61, parity-measurement time $T$62 per stabilizer, and full-cycle time $T$63–$T$64 (Litinski et al., 2017).

Neutral-atom and semiconductor implementations target intrinsically fermionic color codes. In neutral atoms, syndrome measurement uses an ancilla qubit and a Hadamard-test sequence to measure $T$65, while non-number-conserving fermionic braiding is generated by a photodissociation-based neutral-atom braiding gate. For a distance-$T$66 code, the stated resource count is $T$67 fermions $T$68 $T$69 qubit ancillas $T$70 $T$71 molecule modes per logical fermion; longer codes follow

$T$72

The same proposal gives expected gate times $T$73–$T$74 in neutral atoms, and for quantum dots or donors in silicon quotes $T$75 with gate times $T$76–$T$77 (Schuckert et al., 2024).

6. Resource tradeoffs, high-rate variants, and higher-dimensional extensions

Several resource regimes have been stated explicitly for fermionic color-code processors and related code families.

Construction	Stated parameters	Remark
Fermionic-twist stellated color code	$T$78	$T$79 for $T$80
Fermionic-twist stellated color code	$T$81	$T$82
4.8.8 $T$83 stellated fermion code	$T$84	single logical qubit
4.8.8 Majorana color code with $T$85	overhead $T$86	max stabilizer $T$87
4.8.8 Majorana color code with $T$88	overhead $T$89	max stabilizer $T$90
Concatenated fermion-to-qubit code	$T$91	stabilizer weight $T$92

For twist-based two-dimensional processors, the holographic-bound quantity $T$93 reaches $T$94 for triangular $T$95 color codes, $T$96 for triangular $T$97 color codes, and tends to $T$98 for fermionic-twist stellated color codes with $T$99. The explicit family of $\gamma_j$00 stellated fermion codes satisfies

$\gamma_j$01

so

$\gamma_j$02

The comparison given in the source is that standard color code $\gamma_j$03 has $\gamma_j$04 for $\gamma_j$05, whereas fermionic stellated codes have $\gamma_j$06; the abstract further states that these new topological codes have the highest encoding rate of local stabilizer codes with bounded-weight stabilizers in two dimensions (Kesselring et al., 2018).

In direct-Majorana fault tolerance, Monte Carlo decoding yields a threshold $\gamma_j$07. For target physical error rate $\gamma_j$08 and target logical error per gate $\gamma_j$09, the stated estimate is $\gamma_j$10, with each logical Majorana triangle containing $\gamma_j$11 physical Majoranas and each lattice-surgery measurement taking $\gamma_j$12 rounds of face measurements, giving $\gamma_j$13 logical-gate time (Li, 2017).

In fermion-to-qubit concatenations, a small-distance physical fermion-to-qubit code is concatenated with a high-distance fermionic color code. The overall distance is

$\gamma_j$14

all stabilizer generators remain constant weight $\gamma_j$15, and at fixed $\gamma_j$16 each local fermionic interaction maps to an $\gamma_j$17-depth, $\gamma_j$18-weight Pauli circuit. A stated implication is scalable, locality-preserving fault-tolerant simulation of $\gamma_j$19 and $\gamma_j$20 fermionic Hamiltonians with arbitrarily large distance at constant stabilizer weight (Wei et al., 29 Aug 2025).

Three-dimensional chiral color codes extend the processor concept into subsystem-code territory. Defined on a four-colorable $\gamma_j$21 lattice and embedded in the $\gamma_j$22 gauge color code, they realize the fermionic toric-code phase in the qubit case and $\gamma_j$23 Walker–Wang–type models more generally. Because $\gamma_j$24, they admit single-shot error correction and code switching to both the $\gamma_j$25 stabilizer color code and a $\gamma_j$26 boundary color code. The stated performance summary gives bulk code distance $\gamma_j$27, one logical qudit per boundary in open geometry, $\gamma_j$28–$\gamma_j$29, and a universal gate set obtained by sequential code switching; the boundary code has $\gamma_j$30, but is protected by the bulk (Lee et al., 22 Sep 2025).

A plausible synthesis is that fermionic color code processors occupy a spectrum of tradeoffs. Two-dimensional twist and Majorana constructions emphasize locality and native fermionic operations; concatenated Majorana color codes optimize overhead and stabilizer weight; memory–processor stacks separate storage rate from gate locality; and three-dimensional chiral variants add single-shot correction and code switching. Across these variants, the common organizing principle is the use of color-code geometry to preserve fermionic algebra while keeping logical operations topological, local, or transversal.