Co-Packaged Optics: Integration & Scaling

• Co-packaged optics is the integration of photonic devices with electronic ASICs within a single package, enabling ultra-high bandwidth (≥1 Tb/s per chip) and energy-efficient optical links.
• It leverages advanced photonic components such as VCSEL arrays, microring modulators, and polymer waveguide redistribution layers to overcome the limitations of traditional copper-based interconnects.
• System architectures incorporate precise flip-chip integration, robust thermal management, and fine-pitch optical coupling, paving the way for scalable, low-latency interconnects in AI and datacenter applications.

Co-packaged optics (CPO) refers to the monolithic or close-proximity integration of photonic devices directly with electronic ASICs (such as switch, accelerator, or processor dies) at the package level to achieve ultra-high bandwidth, low-energy, low-latency optical interconnections. Originating from datacenter scaling imperatives, CPO has become essential for circumventing the physical and power-density constraints of traditional copper-based electrical I/O at aggregate bandwidths ≥1 Tb/s per chip, especially for AI training clusters and high-radix compute fabrics. Key CPO manifestations encompass vertical-cavity surface-emitting laser (VCSEL) arrays, microring modulator (MRM)-based silicon photonic transmitters, and dense polymer or glass waveguide redistribution layers, with a diversity of coupling and packaging strategies adapted for parallel, broadband, and thermally-managed operation. Metrics of merit include energy per bit (E_bit), spatial bandwidth density (D_bw), pitch scalability, reach, insertion loss, and reliability subjected to data-center environmental and JEDEC stress standards.

1. Motivation, System-Level Constraints, and Paradigms

The primary driver for CPO is the exhaustion of electrical lane performance at aggregate bandwidths >10 Tb/s and per-lane speeds >100 Gb/s, where PCB, package substrate, and connector losses force high-power digital signal processing (DSP) and severely limit spatial bandwidth density (D_bw, in Tb/s/mm²). In contemporary AI clusters, scale-up networks (intra-pod, 0.3–30 m reach, >80% of datacenter bandwidth during training) cannot be efficiently realized with copper, even using retimed active copper cables (ACC) with power cost ≈1.1 pJ/bit for 3 m at 200 Gb/s, reach limited to <1 m, and severe footprint constraints (Kohli et al., 20 Jan 2026). Removing long board-level SerDes copper runs in favor of co-located optics eliminates ≳3.5 pJ/bit SerDes overhead, slashing both total channel energy and package area.

CPO architectures integrate ASICs (e.g., GPUs, custom NPU/TPU dies) on silicon interposers, which also host UCIe-compliant electronic I/O chipsets and large-scale optical engines—VCSEL arrays, microring or slow-light modulators, and photodetector arrays—at pitches down to 50 µm, yielding D_bw >6 Tb/s/mm² (Kohli et al., 20 Jan 2026, Knickerbocker et al., 2024). To fully leverage these densities, vertical stacking, fine-pitch edge (beachfront) coupling, and wafer-scale passive assembly are essential, with polymer, GRIN, or free-form coupling elements implemented for toleranced, sub-dB-loss interfacing (Yu et al., 2021, Weninger et al., 28 Feb 2025, Knickerbocker et al., 2024).

2. Photonic Device Technologies and Modulation Formats

CPO modules exploit a range of optical sources and modulators chosen for their wall-plug efficiency, bandwidth, footprint, manufacturability, and compatibility with integration flows:

• VCSEL Arrays: Directly modulated at f–3 dB >15 GHz (I_bias ≈0.5 mA), with η_WP >20% across 4–100 Gb/s; single-emitter FIT ≲0.07 at 85 °C/5 mA (Kohli et al., 20 Jan 2026). Achieved per-lane 108 Gb/s (PAM4, 0.9 pJ/bit), with prototyped 32 Gb/s NRZ at <0.5 pJ/bit (no DSP required). Current development targets >200 Gb/s per lane with EE <1 pJ/bit.
• Microring Modulators (MRMs) and Coherent Formats: Compact (≈0.02 mm² for 4-λ WDM “IQ” pair) silicon photonics transmitters support advanced formats. MRM-based offset-QAM-16 enables 400 Gb/s at <10 dBm optical power, with input-normalized field contrast 0.64 per dimension; the offset constellation design facilitates DSP-free carrier-phase recovery at nanosecond-scale latency, critical for energy- and area-efficient AI packages (Sturm et al., 13 Jun 2025).
• Slow-Light Photonic Crystal Waveguides (PCWs): Integrated with open-collector drivers to exploit increased group index (n_g) for reduced drive voltage and capacitance, achieving E_bit = 0.78 pJ/bit at 64 Gbaud in a 0.66 mm² active footprint (Kawahara et al., 5 Jun 2025).
• Electro-Absorption Modulated Lasers, InP/Si Integration: Flip-chipped EMLs/PDs on Si interposers enable O-band operation, with measured EO bandwidth ≈40 GHz, insertion loss <1.2 dB/fiber, BER ≤ 10⁻⁷ at OMA ≈0 dBm, and robust WDM/thermal stability (Hou et al., 9 Feb 2026).

3. High-Density Optical Coupling and Packaging Strategies

Bandwidth and energy scaling in CPO is fundamentally linked to beachfront density (ρ, in fibers/mm) and coupling loss budgets. Multiple strategies address the necessity for dense, passive, broadband, and robust couplers:

• Polymer Waveguide Redistribution Layers (PWG RDLs): 50 µm pitch polymer waveguides (n₁≈1.51 core; Δn≈0.04–0.06) yield beachfront density 51 fibers/mm—sixfold over 250 µm-pitch SMF arrays—supporting per-channel insertion loss <1.1 dB and bandwidth density >10 Tbps/mm (with scaling to >80 Tbps/mm at sub-20 µm pitch) (Knickerbocker et al., 2024, Asch et al., 4 Mar 2025). Lithography- or flip-chip-based integration with Si-photonic die ensures adiabatic coupling, sub-dB PDL, and process compatibility with FOWLP, BEOL and micro-BGA attaches (Asch et al., 4 Mar 2025).
• Free-Form Reflective Micro-Optics: 3D-printed polymer TIR couplers bonded directly to SiN/Si facets achieve 0.5 dB coupling loss (1-dB BW = 300 nm), passive spatial alignment, and solder-reflow resilience, allowing >4 channels/mm and alignment tolerances ±2.2 µm (Yu et al., 2021).
• GRIN and Overlapping Double-Taper Couplers: SiON or SiN/Si vertical couplers exploit adiabatic inverse double taper or GRIN/evanescent schemes, delivering <0.27 dB chip-to-chip loss (11 µm gap), 1-dB tolerance ±2.4 µm, >360 nm bandwidth, and PDL < 1 dB for universal fiber-to-chip and chip-to-chip integration (Weninger et al., 28 Feb 2025, Weninger et al., 2022).

4. Module Integration, Thermal, and Reliability Considerations

Integration approaches prioritize flip-chip die placement, micro-bump attach (<1 µm X–Y accuracy), and coplanar or vertical optical coupling. Module-level CPO packages co-locate photonic engines, electronic I/O chipsets, microfluidic cold plates, and copper heat-spreaders to address ≳1 W/100 Gb/s lane heat flux with R_th,jc ≈50 K/W (VCSEL array) and R_th,cs ≈10 K/W (case-to-sink) (Kohli et al., 20 Jan 2026). Advanced packages employ microfluidic cold plates under both ASIC and optical engines. JEDEC reliability—encompassing 1000 cycles −40 °C↔+125 °C, 85 °C/85%RH/1000 h, and solder reflow—has been demonstrated for <+0.25 dB post-stress loss and no fiber detachment for polymer waveguide modules (Knickerbocker et al., 2024).

Monolithic, passively aligned, and high-yield integration flows (chip-first and chip-last FOWLP, flip-chip, wafer-scale pick-and-place) are compatible for the lithographically patterned and flip-chip ORDL schemes, ensuring manufacturability at >10⁴ I/O per cm² and strong electrical-optical co-fanout (Asch et al., 4 Mar 2025). Passive coupler alignment tolerance (±2.7 µm) (Weninger et al., 2022), broadband operation, and solder-reflow compatibility are industry-validated.

5. System Architectures, Performance Metrics, and Scaling Laws

CPO systems model energy per bit as $E_{bit} = \frac{V_{drive} \times I_{drive}}{R_b}$, targeting ≤1 pJ/bit including SerDes/UCIe/optics at >3.2 Tb/s per tile (Kohli et al., 20 Jan 2026); measured optical engine EEs reach 0.5–0.9 pJ/bit in advanced VCSEL and PCW platforms (Kohli et al., 20 Jan 2026, Kawahara et al., 5 Jun 2025). Bandwidth density is maximized at 6–10 Tbps/mm² with 50 µm pitch (and projected >20 Tbps/mm² at 20 µm pitch), with the following scaling relationship: $B_d = N \times M \times R_{1}$ where N is channel count per mm, M the WDM multiplicity, and $R_1$ per-channel rate (Knickerbocker et al., 2024). System latency reduces to <50 ns per link, with system throughput scaling as $T_{sys} = N_{nodes} \times B_{link} \times U$ (U = utilization factor), far surpassing NVLink/PCIe by factors of 20–30× in energy and 2–4× in latency per equal bandwidth (Moazeni, 2023). Reach exploits multimode VCSEL for up to 150 m and single-mode (slow-and-wide) for >1 km (Kohli et al., 20 Jan 2026).

Yield, scalability, and reliability are demonstrated in SiON-based 2.5D interposer modules for 4×100 Gb/s channels (fiber-to-fiber loss <1.2 dB), with channel crosstalk < –20 dB, AWG tolerances σ = 1.2 nm across 240 channels, and 10⁷ device-hour reliability (Hou et al., 9 Feb 2026). Polymer waveguides and SiN/SiN tapers eliminate sub-100 nm lithography requirements, vital for manufacturing yield at >10⁴ I/O per cm² (Asch et al., 4 Mar 2025).

6. Applications, Implications, and Roadmap

CPO underpins high-radix, low-latency optical fabrics for disaggregated memory/compute architectures, enabling remote HBM pooling, multi-rack all-to-all interconnects, and dynamic AI workload scaling at ≥100 Tb/s per rack and ≤1 pJ/bit (Moazeni, 2023). Datacenter-scale bandwidth densities in excess of 10 Tbps/mm, model-training latency reductions (e.g., for T-parameter LLMs), and >90% electrical I/O power reduction for generative AI workloads exemplify the transformative I/O scaling afforded (Knickerbocker et al., 2024).

Future research priorities include scaling single-lane rates to >200 Gb/s PAM4 (no DSP), further lowering threshold currents and parasitics for VCSEL/PCW/EIML/PIC, increasing array yield, developing error correction/hot-swap for FIT < 1, and universal fiber/coupler standards for sub-20 μm pitch. Roadmaps project >100 Tbps/mm² density, monolithic EIC–optical engine integration, and automated wafer-level assembly for Pbps class interconnects (Knickerbocker et al., 2024, Moazeni, 2023).

7. Challenges and Open Issues

CPO faces challenges in:

• Achieving uniform and reliable large-scale emitter arrays (hundreds–thousands of VCSELs or modulator lanes)
• Manufacturing and assembly at sub-20 μm density with <500 nm alignment tolerances and controlled crosstalk
• Ensuring long-term reliability of optical-electrical transitions under thermal and mechanical stress
• Fundamental limits of power and system-level heat removal at extreme densities
• Standardization (UCIe, OIF CEI-112G, JEDEC) for optical lanes and integration formats (Moazeni, 2023)
• Polymer aging, environmental stability, and scaling throughput for 3D/TPP-printed micro-optics (Yu et al., 2021)

Continued innovation in process integration, packaging, thermal management, passive alignment, and electronic-photonic circuit co-design is expected to define the trajectory of co-packaged optics toward exascale AI clusters, optical memory pools, and energy-efficient compute fabrics (Kohli et al., 20 Jan 2026, Knickerbocker et al., 2024, Moazeni, 2023, Asch et al., 4 Mar 2025).