Co-Packaged Optics (CPO) Technology

Updated 3 September 2025

Co-Packaged Optics (CPO) is an integration paradigm that co-locates photonic components and CMOS electronics to overcome interconnect bottlenecks in high-performance systems.
CPO employs advanced low-temperature fabrication, scalable lithography, and innovative optical packaging to achieve ultra-dense optical I/O with high bandwidth and energy efficiency.
Applications of CPO span data center switches, AI accelerators, and neuromorphic processors, driving next-generation high-throughput computing architectures.

Co-Packaged Optics (CPO) Technology is an integration paradigm wherein photonic components (modulators, detectors, waveguides, and packaging interfaces) are co-located and co-fabricated with high-performance electronics, such as CMOS circuits, within a shared module or at the wafer-level. This proximity and integration alleviate the electrical interconnect bottleneck in bandwidth scaling and energy efficiency, enabling ultra-high density optical I/O at package edges and beyond. CPO leverages advancements in photonic device technology, innovative coupling schemes, and compatibility with high-yield electronic packaging methodologies to satisfy the requirements of contemporary data center switches, AI accelerators, neuromorphic processors, and future high-throughput computing architectures.

1. Principles of Co-Packaged Optics Integration

CPO technology relies on heterogeneous integration, enabling photonic and electronic elements to coexist closely. The foundational principles include:

Low-Temperature, Back-End-of-Line (BEOL)-Compatible Fabrication: Photonic devices such as low-loss SiN waveguides and superconducting nanowire detectors are deposited at sub-65 °C temperatures, allowing post-CMOS fabrication without thermal degradation of electronics (Shainline et al., 2016).
Scalable Lithography: The use of 365 nm i-line stepper lithography facilitates cost-effective, high-throughput patterning, supporting mass production for dense optical interconnects (Shainline et al., 2016).
Process-Agnostic Packaging: Solutions such as SU-8 epoxy-based fiber collars and pedestals enable robust, temperature-resistant fiber alignment and attachment, independent of the underlying photonic process (Shainline et al., 2016).

By permitting photonic device integration directly atop fully processed electronics, CPO supports advanced configurations: vertical chip stacking, beachfront waveguides with micron-scale pitch (Knickerbocker et al., 9 Dec 2024), and flip-chip bonding of polymer waveguides for electrical and optical redistribution (Asch et al., 4 Mar 2025).

2. Photonic Device Technologies for CPO

Several classes of photonic devices are central to CPO implementations:

Waveguides: Silicon nitride (SiN) waveguides exhibit low-loss propagation and broad transparency (visible to infrared). They are deposited via PECVD under near-ambient conditions and allow high-fidelity routing among optical functional blocks (Shainline et al., 2016).
Resonators and Interferometers: High- $Q$ ring resonators and Mach-Zehnder Interferometers (MZIs) provide frequency selection and modulation with high channel density and extinction ratio (ER > 25 dB, deviation < 1.5%) (Shainline et al., 2016, Gui et al., 2021).
Electro-Optic Modulators: Recent innovations include micrometer-scale, ITO-plasmonic MZI modulators with sub-3 dB insertion loss, 100 GHz bandwidth, voltage-length product $V L_{\pi} \approx 90$ V·mm, and energy consumption near 380 fJ/bit (Gui et al., 2021).
Microring Modulators (MRMs): For ultra-dense wavelength division multiplexing (DWDM), MRMs can realize coherent modulation formats (e.g., offset QAM-16) efficiently in compact areas (10–100 $\times$ smaller than MZIs), supporting 400 Gbps data rates at 9.65 dBm laser power (Sturm et al., 13 Jun 2025).

The device density and operational fidelity of these elements assure high aggregate bandwidth with minimized area and power consumption.

3. Optical Coupling and Packaging Strategies

Advances in coupling schemes underpin scalable, low-loss optical I/O in CPO systems:

Free-Form Micro-Optics: Deterministically designed 3D reflective couplers (via Fermat’s principle) enable <1 dB insertion loss over >180 nm bandwidth with ±2.2 μm misalignment tolerance, compatible with surface-normal fiber interfaces and solder-reflow electronic packaging (Ranno et al., 2023, Yu et al., 2021).
Fusion Splicing and Adhesive Reinforcement: Permanent, CO $_2$ laser-induced fusion bonds achieve 1.0 dB facet losses with 0.6 dB penalty over 160 nm bandwidth, simplifying assembly and eliminating reliance on bulky mechanical fixtures (Nauriyal et al., 2018).
Pitch-Optimized Polymer Waveguides: Beachfront density is improved 6 $\times$ with 50 μm pitch polymer waveguide arrays, adiabatically coupled to on-chip waveguides, meeting JEDEC reliability standards and supporting bandwidth densities upwards of 10 Tbps/mm (Knickerbocker et al., 9 Dec 2024).
Graded Index (GRIN) Couplers: GRIN-based “on-chip lenses” with parabolic index profiles ( $n(z) = n_H (1 - \frac{\alpha^2 z^2}{2})$ ) enable versatile fiber-to-chip and chip-to-chip coupling. These designs achieve <0.27 dB losses across 360 nm bandwidth and permit automated, passive flip-chip assembly at 20 μm pitch (Weninger et al., 28 Feb 2025).
Vertical Double-Taper Couplers: Overlapping SiN/Si reverse tapers result in <0.13 dB insertion loss, >300 nm bandwidth, and alignment tolerances of ±2.7 μm, enabling high-density, passive vertical stacking for multi-chip CPO architectures (Weninger et al., 2022).

These approaches relax alignment precision requirements, enhance scalability, and maintain performance across thermal and mechanical stress.

4. Advanced Modulation and Coherent Interconnects

Performance scaling necessitates moving beyond simple amplitude modulation:

Intensity-Modulated Direct Detection (IM/DD): Technologies such as high-speed Mach-Zehnder and DFB-TWEAM modulators enable 140 Gbaud OOK links, achieving operation over several kilometers without dispersion compensation (Ozolins et al., 2018).
High-Order Coherent Modulation: Offset-QAM-16 formats realized with MRMs (via RAMZI architectures) permit phase-constant amplitude modulation. Carrier phase recovery is simplified (DSP-free designs with analog feedback loops), lowering power far below conventional DSP-based systems (down to ~280 fJ/bit for 400 Gbps links) (Sturm et al., 13 Jun 2025, Rezaei et al., 24 May 2025).
DSP-Free Carrier Phase Recovery: Laser-forwarded coherent links employing analog CPR for offset-QAM architectures operate at 100 GBaud with modulation/scaling independence, validated with GF45nm monolithic silicon photonics ICs (Rezaei et al., 24 May 2025).

This transition to coherent modulation and advanced CPR architectures is essential to further data rate and efficiency scaling for CPO deployments.

5. System-Level Scaling and Bandwidth Density

CPO implementation directly addresses the limitations of transceiver density, optical port scaling, and aggregate bandwidth:

Beachfront Density: Polymer waveguide interfaces at 50 μm pitch enable a sixfold increase in optical fiber ports per chip edge, supporting up to 10 Tbps/mm and projections toward 80 Tbps/mm for sub-20 μm pitch (Knickerbocker et al., 9 Dec 2024).
Pitch and I/O Channel Density: GRIN coupler arrays at 20 μm pitch yield ~50 couplers/mm, compared to conventional 8 fibers/mm in 127 μm pitch V-groove assemblies (Weninger et al., 28 Feb 2025).
Integration with Electrical Redistribution: Face-up and flip-chip approaches allow optical waveguides to coexist with electrical redistribution layers, facilitating high-density interconnects in chiplet and wafer-level packaging (Asch et al., 4 Mar 2025).
JEDEC and Environmental Reliability: Next-generation modules meet thermal cycling, damp heat, and extended storage requirements, enabling robust operation in data center settings (Knickerbocker et al., 9 Dec 2024).

The scaling of CPO systems is governed by the achievable optical I/O channel density, insertion loss budget, and the compatibility of photonic assembly with existing electronic packaging.

6. Applications in High-Performance Computing and AI Systems

CPO is foundational for current and next-generation computing architectures, notably:

AI/ML Accelerator Interconnects: CPO mitigates bandwidth bottlenecks in GPU racks and AI accelerators, supporting bidirectional bandwidths exceeding 7.2 Tbps per GPU and aggregate fiber bandwidths >1 Tbps via DWDM (Moazeni, 2023).
Disaggregated Architectures: The low-latency, high-throughput links enabled by CPO permit memory and compute resource disaggregation (dynamic CPU/GPU/HBM allocation), reducing memory access latency from ~8 μs to ~6 μs and increasing flexibility for cloud computing (Moazeni, 2023).
Generative AI Model Training: CPO technology leads to up to 5 $\times$ improvement in training throughput for trillion-parameter models, reducing three-month training cycles to three weeks and yielding significant energy savings (Knickerbocker et al., 9 Dec 2024).
Photonic Computing and Neuromorphic Systems: Ultra-broadband, low-loss, multiport packaging solutions (<0.78 dB total loss, >100 nm bandwidth) enable scalable integration of photonic processors for neuromorphic, quantum, and optical tensor core applications (Jung et al., 27 May 2025).

A plausible implication is that the maturation of CPO supports not only communications but photonic computing and emerging AI-driven workflow demands.

7. Future Directions and Challenges

Key areas for future research and industry deployment include:

Further Bandwidth and Energy Scaling: Targeting 5–10 $\times$ improvements in energy efficiency (toward sub-pJ/bit) and port density. Innovations required in silicon photonics device integration, laser cost management, low-parasitic packaging, and advanced equalization circuits (Moazeni, 2023, Sturm et al., 13 Jun 2025).
Wafer-Level and Passive Assembly: Automated, passive flip-chip and lithographic assembly for optical waveguides and couplers (with alignment tolerances >2 μm) boost production yield and scalability (Weninger et al., 28 Feb 2025, Weninger et al., 2022).
Universal Coupling Interfaces: Material-agnostic graded-index and polymer waveguide couplers adaptable to chip-to-chip and fiber-to-chip scenarios are crucial for versatile design (Weninger et al., 28 Feb 2025, Asch et al., 4 Mar 2025).
Thermal Management and Reliability: Advanced packaging must maintain performance across extended temperature ranges and meet JEDEC standards, ensuring suitability for real-world deployment (Knickerbocker et al., 9 Dec 2024).
Switching Networks and On-Chip Photonic Processing: The addition of processing functionality (such as direct memory access or optical switching) to co-packaged optical modules underpins future computing paradigms (Moazeni, 2023).

Continued innovation in fabrication, device design, packaging, and system integration is required to meet forthcoming data center, AI/ML, and photonic computing performance targets.

Co-Packaged Optics technology synthesizes advancements across photonic devices, packaging architectures, modulation formats, and system integration, offering a robust foundation for bandwidth scaling and energy efficiency in next-generation high-performance computing. The collective research demonstrates that with optimized fabrication, coupling, and packaging, CPO can realize the necessary functional density and reliability for distributed AI systems, large-scale interconnects, and emerging photonic computing domains.