Trench-Based Die-to-Wafer Bonding in Photonics

• Trench-based die-to-wafer bonding is a heterogeneous integration method that uses lithographically defined oxide trenches to attach pre-patterned TFLN dies to fully processed silicon photonics wafers.
• The process employs precise trench formation, controlled BCB adhesive bonding, and strict thermal budgets to maintain CMOS compatibility and achieve bond yields over 95%.
• This integration technique enables efficient vertical optical coupling with insertion losses as low as 0.11 dB and supports >100 GHz electro-optic modulation for advanced photonic interconnects.

Trench-based die-to-wafer bonding is a back-end-of-line (BEOL) heterogeneous integration methodology in which pre-patterned thin-film lithium niobate (TFLN) dies are locally attached to fully processed silicon photonics wafers by embedding them in lithographically defined oxide trenches. This process enables co-packaging of high-performance active and passive photonic components—such as high-speed modulators and photodetectors—on a single platform, while preserving complementary metal-oxide-semiconductor (CMOS) compatibility and large-scale manufacturability. The approach is particularly suited to next-generation optical interconnects demanding bandwidth, density, and energy efficiency that exceed the limits of monolithic silicon photonics (Wu et al., 8 Dec 2025).

1. Trench-Based Bonding Workflow and Fabrication

The trench-based die-to-wafer strategy consists of a multistep process with tight constraints on temperature, material interfaces, and dimensional tolerances, as outlined below:

1. Silicon Photonics Front-End: Waveguides, epitaxial Ge PIN photodetectors, doping, and couplers are fabricated on a 220 nm Si/3 µm BOX wafer using a 130 nm CMOS process design kit (PDK). PECVD SiO₂ over-cladding is deposited and planarized to ~180 nm above the waveguides. TiN (∼20 nm) is deposited as an etch-stop above modulator regions. Additional layers, such as SiN edge couplers, TiN resistive heaters, and Al/Cu metallization, are patterned. All steps maintain a maximum $T \leq 400^\circ\text{C}$ for BEOL compatibility.
2. Trench Formation: Lithographically patterned SiO₂ trenches are opened above modulator locations. Dry etching (e.g., CHF₃/O₂ inductively coupled plasma at 200 W/50 W, 10 mTorr, ~100 nm/min) removes the over-cladding down to the TiN stop. Trenches are ≃ 5 µm deep with sidewall angles $\geq 85^\circ$ and widths of 10–20 µm, sized for vertical adiabatic couplers (VACs) and TFLN ridge devices.
3. Wafer Cleaning and BCB Application: Standard RCA and piranha clean processes remove contaminants. Cyclotene® 3022-35 benzocyclobutene (BCB) is spin-coated at 3,000 rpm for an 85 nm-thick adhesive film and pre-baked at $180^\circ\text{C}$ for 20 min in N₂.
4. Die-to-Wafer Bonding: Diced X-cut LNOI dies (LN/SiO₂/Si) are aligned and placed into the trenches. The wafers are bonded in vacuum (< $10^{-3}$ Torr) with 600 N applied force at room temperature, followed by post-bake at $300^\circ\text{C}$ for 1 h in N₂ to cure the BCB.
5. TFLN Substrate Removal: Mechanical grinding thins the Si handle to ~50 µm, and selective etches (e.g., KOH or TMAH for Si, buffered HF for BOX) expose the 500-nm TFLN layer.
6. TFLN Device Fabrication: Contact lithography defines TFLN ridge waveguides (350 nm ridge, 150 nm slab). Reactive ion etching (Ar/CHF₃, 50 W/50 mTorr) and SU-8 over-clad application follow. Traveling-wave electrodes are realized by Ti (for 50 Ω terminations) and Au evaporation, with pad openings for Si heaters and Ge PDs.

Each stage is engineered for dimensional accuracy and thermal budget, with BEOL steps capped at $300^\circ\text{C}$ to protect front-end devices (Wu et al., 8 Dec 2025).

2. Trench Geometry, Adhesive Properties, and Interface Integrity

The vertical trenches are essential for enabling tight integration of dissimilar materials. Typical values are:

• Depth: ≈ 5 µm (oxides fully removed)
• Width: 10–20 µm (sufficient for two VACs and TFLN ridge)
• Length: 6.4 mm (full modulator)
• Sidewall Angle: $\geq 85^\circ$ (near-vertical, ensuring BCB uniformity)

The adhesive interface utilizes Cyclotene® BCB, chosen for its process compatibility:

• Young’s modulus: $E_{\mathrm{BCB}} \simeq 2$ GPa
• Glass transition temperature: $T_g \simeq 350^\circ\text{C}$
• Thermal expansion coefficient: $\alpha_{\mathrm{BCB}} \simeq 40$ ppm/°C

Bond strength metrics:

• Bond energy per area: $G \simeq 0.5–1$ J/m² ($G = F_\text{peel}/A$)
• Shear strength: $\tau \simeq 5–10$ MPa ($\tau = F_\text{shear}/A$)

Trench cleanliness and geometry, together with BCB thickness tolerance (±20 nm), yield bond yields exceeding 95% across 8-inch wafers. Thermal mismatch stress on cooling after BCB cure is $$\sigma = E_\text{eff} \cdot (\alpha_\text{Si} - \alpha_\text{LN})\Delta T/(1-\nu_\text{eff})$$, yielding $\sigma \lesssim 10$ MPa for $\Delta T = 275^\circ\text{C}$, below the fracture thresholds of both LiNbO₃ and BCB (Wu et al., 8 Dec 2025).

3. Vertical Optical Coupling and Mode Engineering

Trench-based bonding facilitates vertical adiabatic optical coupling between Si and TFLN domains without requiring sub-100 nm bonding gaps or etched tapers. Key parameters for the implemented VAC:

• Si taper: width narrows from 450 nm to 180 nm over 200 µm
• TFLN ridge: width expands from 1.5 µm (in VAC region) to 2.5 µm in modulator region
• Coupling efficiency: measured insertion loss $\sim$0.11 dB per coupler ($>97\%$), confirmed by overlap integral

$$\kappa = \frac{\iint E_\mathrm{Si}(x, y) E^*_\mathrm{LN}(x, y)\,dx\,dy} {\sqrt{\iint |E_\mathrm{Si}|^2\,dx\,dy\;\iint |E_\mathrm{LN}|^2\,dx\,dy}}$$

Finite-difference mode simulations show $\kappa \simeq 0.99$ for fundamental TE mode transitions over the 200 µm taper length. The vertical separation, set by the sum of BCB and any residual oxide, directly controls the evanescent field overlap, with sub-micron precision critical for low-loss hybrid operation (Wu et al., 8 Dec 2025).

4. Electrical Routing, BEOL Parasitics, and CMOS Compatibility

Bonded TFLN dies require electrical accessibility for high-speed modulation and detection. This is achieved via:

• Vias through SU-8/SiO₂: formation tolerates ±200 nm misalignment
• Al/Cu metal routing: single BEOL layer, 2 µm line/spacing
• Traveling-wave electrode parasitic capacitance: $C_p \simeq \epsilon_0 \epsilon_r W_\text{gap}/d$, where $W_\text{gap} \simeq 5\,\mu$m, $d \simeq 2\,\mu$m, $\epsilon_r(\mathrm{SU}\text{-}8) \simeq 3$, yielding $C_p \simeq 50$ fF/mm

The total BEOL process stays within a $300^\circ\text{C}$ thermal budget, preserving multilayer metallization and preventing degradation of either Si or Ge active devices. Empirically, no change in Ge photodiode IV or responsivity is detected post-bonding, nor is there modulator quadrature drift over 30 min at bias (Wu et al., 8 Dec 2025).

5. System Performance and Yield Metrics

System metrics linked directly to the trench-based integration and mode engineering include:

Metric	Value	Notes
VAC (per coupler) loss	0.11 dB	$>97\%$ efficiency
Modulator 3-dB electro-optic bandwidth	$\sim$100 GHz	6.4 mm length, $V_\pi = 4.4$ V
E-E bandwidth (modulator $\to$ Ge PD)	$\sim$60 GHz
Data rate (OOK/PAM4)	128 GBd/100 GBd	BER $<2.4\times 10^{-4}$/ $<3.8\times 10^{-3}$
Insertion loss (modulator)	4 dB	Dominated by contact litho
Bond yield (8")	$>95\%$	±20 nm BCB, ±300 nm alignment

The optical insertion loss consists of 2×VAC losses, 2×MMI losses (~0.3 dB each), and TFLN propagation ($\sim$1 dB/cm over 0.64 cm). High speed is supported by optimized traveling-wave electrodes and low parasitics, with system-level OOK and PAM-4 error rates well below FEC thresholds (Wu et al., 8 Dec 2025).

6. Integration Advantages and Significance

Trench-based die-to-wafer bonding offers several important advantages in photonic integration:

• Full preservation of CMOS BEOL Si photonics, including active Ge photodiodes and multilayer interconnects, by avoiding pre-bond modifications.
• Local oxide removal in trenches enables sub-micron Si–LN proximity, necessary for efficient vertical mode hybridization without throughput loss.
• The BCB adhesive absorbs residual topography and promotes a robust bond, with mechanical reliabilities above industry standards.
• Trench confinement localizes TFLN only to intended modulation regions, reducing die cost and simplifying placement.
• The thermal budget accommodates sensitive front-end metallic and dielectric structures, ensuring overall system and process integrity.

In summary, trench-based die-to-wafer bonding enables integration of >100 GHz bandwidth TFLN modulators and >60 GHz Ge photodetectors with low insertion loss and high mechanical yield, demonstrating a scalable technology foundation for energy-efficient, high-capacity photonic interconnects (Wu et al., 8 Dec 2025).

7. Context and Prospects for Scalable Photonic Systems

These methods directly address long-standing integration limits in silicon photonics by permitting active TFLN attachment to fully functional, fabricated Si photonics dies. The ability to combine TFLN, Si, Ge, and multilayer BEOL products in a post-fabrication step supports rapid scaling for next-generation optical links suited to AI, cloud, and data-center workloads. The process also provides a versatile template for the inclusion of additional photonic materials in future platforms, conditional on similar bond/oxide etch strategies and within thermal/metallurgical budgets (Wu et al., 8 Dec 2025).

A plausible implication is that trench-based bonding, owing to its tolerance for topographical and dimensional non-idealities, will facilitate diversified hybrid photonic platforms with bandwidths and link densities unattainable in monolithic systems.