Circuit Varieties in Mathematics & Engineering

• Circuit varieties are classifications of circuit behaviors defined by invariant structures such as dependencies and topologies across fields like matroid theory, quantum, and electrical engineering.
• They capture configurations that over-realize dependencies, classify equivalent quantum circuits, and characterize edge directions in polyhedral projections.
• Applications span from algebraic-geometric modeling and minimal dependency extensions to engineered topolectrical circuits and circuit discovery in transformer models.

Circuit varieties are studied under several distinct meanings across contemporary mathematics, physics, computer science, and machine learning. In matroid theory, the term has a precise algebraic-geometric meaning: for a matroid $M$ of rank $n$ on $[d]$ and $r\ge \operatorname{rk}(M)$, the circuit ideal is

$$I_{\mathcal{C}(M),r} = \big\langle [A|B]_X : B\in \mathcal{C}(M),\, A\subseteq [r],\, |A|=|B| \big\rangle,$$

and its zero set $V_{\mathcal{C}(M),r}=V(I_{\mathcal{C}(M),r})$ is the circuit variety; equivalently, it is the set of collections of vectors in $\mathbb{C}^r$ whose dependencies include those of $M$ (Liwski et al., 2024). In other literatures, “circuit varieties” denotes taxonomies of topolectrical and topological LC architectures (Sahin et al., 25 Feb 2025), families of equivalent quantum circuits generated by rewrite rules (Garcia-Escartin et al., 2011), formulation-dependent families of polyhedral circuits under projection (Borgwardt et al., 2022), and task-dependent subgraphs in transformer models (Wu et al., 15 Jun 2026). This suggests that the common thread is classification by invariant structure—dependency, topology, equivalence, or functional role—rather than by hardware alone.

1. Matroid-theoretic and algebraic-geometric meaning

For a matroid $M$, the circuit variety is larger than the matroid variety because it encodes only the requirement that every circuit of $M$ remain dependent. By construction,

$n$0

so the circuit variety contains the Zariski closure of exact realizations as a distinguished subvariety (Liwski et al., 2024). In the minimal ambient dimension $n$1, the notation is typically shortened to $n$2 for the realization space, $n$3 for the matroid variety, and $n$4 for its defining ideal (Liwski et al., 2024).

In rank $n$5, where simple matroids correspond to point-line configurations, the circuit variety admits a particularly transparent interpretation. The circuit ideal is generated by the $n$6 minors attached to collinear triples, and the circuit variety parametrizes point configurations obeying the prescribed collinearity constraints but possibly carrying additional dependencies (Clarke et al., 2024). In that setting, the paper identifies the circuit variety with the combinatorial closure

$n$7

so it is the union of matroid varieties of all matroids $n$8 extending the dependency structure of $n$9 (Clarke et al., 2024).

This distinction between exact realization and over-realization is the central structural feature of circuit varieties. The matroid variety records configurations whose dependence relations match $[d]$0 exactly, whereas the circuit variety records configurations whose dependence relations contain those of $[d]$1. In general, understanding when the two coincide, and when extra components appear, is the main geometric problem (Liwski et al., 2024).

2. Liftability, nilpotency, and defining equations

A major line of work analyzes circuit varieties through liftability. For rank-$[d]$2 point-line configurations, liftability is defined by asking whether any $[d]$3-tuple of distinct collinear points in $[d]$4 arises as the projection of a non-degenerate realization of the configuration, and the condition is encoded by a collinearity matrix $[d]$5 whose kernel describes possible lifts (Clarke et al., 2024). Forest configurations are liftable, and for configurations with no triplets of concurrent lines, liftability forces equality

$[d]$6

For connected quasi-liftable configurations in which every point lies on at most two lines, the circuit variety has exactly two irreducible components,

$[d]$7

where $[d]$8 is the matroid variety of a line with $[d]$9 marked points (Clarke et al., 2024).

The higher-rank generalization uses nilpotent, weak-nilpotent, strong-nilpotent, and solvable matroids. Nilpotent matroids are realizable and have irreducible realization spaces, and for nilpotent $r\ge \operatorname{rk}(M)$0-paving matroids with no points of degree greater than two one has

$r\ge \operatorname{rk}(M)$1

For forest point-line configurations, even when points of degree greater than two occur, the matroid ideal is controlled by the circuit ideal together with a Grassmann–Cayley ideal $r\ge \operatorname{rk}(M)$2,

$r\ge \operatorname{rk}(M)$3

and for strong-nilpotent matroids the circuit and matroid varieties again coincide (Liwski et al., 2024).

For paving matroids, a third method constructs defining equations by combining the circuit ideal with lifting polynomials and graph polynomials. When $r\ge \operatorname{rk}(M)$4 is an $r\ge \operatorname{rk}(M)$5-paving matroid with no points of degree greater than two,

$r\ge \operatorname{rk}(M)$6

and the graph-ideal formulation yields a finite generating set (Liwski et al., 2024). In the same class, if all submatroids of hyperplanes are liftable then $r\ge \operatorname{rk}(M)$7, while if all proper submatroids of hyperplanes are liftable then

$r\ge \operatorname{rk}(M)$8

with $r\ge \operatorname{rk}(M)$9 the uniform rank-$$I_{\mathcal{C}(M),r} = \big\langle [A|B]_X : B\in \mathcal{C}(M),\, A\subseteq [r],\, |A|=|B| \big\rangle,$$0 component (Liwski et al., 2024).

3. Minimal extensions and irreducible decomposition

Recent work treats circuit varieties through the dependency poset of matroids. For matroids $$I_{\mathcal{C}(M),r} = \big\langle [A|B]_X : B\in \mathcal{C}(M),\, A\subseteq [r],\, |A|=|B| \big\rangle,$$1 on the same ground set, the dependency order is defined by

$$I_{\mathcal{C}(M),r} = \big\langle [A|B]_X : B\in \mathcal{C}(M),\, A\subseteq [r],\, |A|=|B| \big\rangle,$$2

and the minimal extensions $$I_{\mathcal{C}(M),r} = \big\langle [A|B]_X : B\in \mathcal{C}(M),\, A\subseteq [r],\, |A|=|B| \big\rangle,$$3 are the minimal elements above $$I_{\mathcal{C}(M),r} = \big\langle [A|B]_X : B\in \mathcal{C}(M),\, A\subseteq [r],\, |A|=|B| \big\rangle,$$4 in this order (Liwski et al., 23 Apr 2025). The key structural proposition is

$$I_{\mathcal{C}(M),r} = \big\langle [A|B]_X : B\in \mathcal{C}(M),\, A\subseteq [r],\, |A|=|B| \big\rangle,$$5

which turns the study of a circuit variety into an inductive study of minimal extensions and their own circuit varieties (Liwski et al., 23 Apr 2025).

This leads to explicit irreducible decompositions for classical examples. For the Vámos matroid,

$$I_{\mathcal{C}(M),r} = \big\langle [A|B]_X : B\in \mathcal{C}(M),\, A\subseteq [r],\, |A|=|B| \big\rangle,$$6

and for the dual of the graphic matroid of $$I_{\mathcal{C}(M),r} = \big\langle [A|B]_X : B\in \mathcal{C}(M),\, A\subseteq [r],\, |A|=|B| \big\rangle,$$7,

$$I_{\mathcal{C}(M),r} = \big\langle [A|B]_X : B\in \mathcal{C}(M),\, A\subseteq [r],\, |A|=|B| \big\rangle,$$8

with both components irreducible and incomparable (Liwski et al., 23 Apr 2025). The same algorithmic framework computes minimal irreducible decompositions for the Steiner quadruple system $$I_{\mathcal{C}(M),r} = \big\langle [A|B]_X : B\in \mathcal{C}(M),\, A\subseteq [r],\, |A|=|B| \big\rangle,$$9 and the dual of the Fano matroid (Liwski et al., 23 Apr 2025).

For rank-$V_{\mathcal{C}(M),r}=V(I_{\mathcal{C}(M),r})$0 point-line configurations, the analogous statement uses $V_{\mathcal{C}(M),r}=V(I_{\mathcal{C}(M),r})$1, the minimal matroids above $V_{\mathcal{C}(M),r}=V(I_{\mathcal{C}(M),r})$2 in dependency order: $V_{\mathcal{C}(M),r}=V(I_{\mathcal{C}(M),r})$3 This formula underlies explicit decompositions for the Fano matroid, the MacLane configuration, the affine plane of order three, the Pappus configuration, and the second $V_{\mathcal{C}(M),r}=V(I_{\mathcal{C}(M),r})$4 configuration (Liwski et al., 2 Feb 2025). In the Fano case, for example,

$V_{\mathcal{C}(M),r}=V(I_{\mathcal{C}(M),r})$5

and each component is an irreducible matroid variety (Liwski et al., 2 Feb 2025).

Algorithmically, these decompositions rely on systematic generation of minimal matroids via formulas encoding identifications and non-identifications of points, together with hypergraph procedures that merge lines when new circuits are introduced (Liwski et al., 2 Feb 2025). A plausible implication is that the geometry of circuit varieties is governed less by arbitrary determinantal elimination than by the local combinatorics of minimal dependency extensions.

4. Polyhedral circuits under projection

In linear programming theory, the word “circuit” denotes elementary directions of a polyhedron rather than subcircuits of an electrical or logical device. For a polyhedron

$V_{\mathcal{C}(M),r}=V(I_{\mathcal{C}(M),r})$6

its circuits are the nonzero vectors $V_{\mathcal{C}(M),r}=V(I_{\mathcal{C}(M),r})$7 such that $V_{\mathcal{C}(M),r}=V(I_{\mathcal{C}(M),r})$8 has inclusion-minimal support among all nonzero vectors $V_{\mathcal{C}(M),r}=V(I_{\mathcal{C}(M),r})$9 with $\mathbb{C}^r$0 (Borgwardt et al., 2022). Every edge direction of $\mathbb{C}^r$1 is a circuit, but the set of circuits is generally larger and describes potential edge directions across right-hand-side perturbations (Borgwardt et al., 2022).

For an extended formulation $\mathbb{C}^r$2 with linear projection $\mathbb{C}^r$3, edge directions are always inherited from $\mathbb{C}^r$4, but general circuits are not. The paper proves that there exist full-dimensional pointed polyhedra $\mathbb{C}^r$5, $\mathbb{C}^r$6, with $\mathbb{C}^r$7, such that

$\mathbb{C}^r$8

and the difference between inherited and non-inherited circuit directions can be exponentially large in the dimension (Borgwardt et al., 2022). In this sense, the “variety” of circuit directions is formulation-dependent rather than intrinsic to the projected object alone.

The structural results are sharp. A linear map $\mathbb{C}^r$9 satisfies $M$0 for all polyhedra $M$1 if and only if $M$2 is injective, and a pointed polyhedron $M$3 inherits circuits from every extension if and only if all circuits of $M$4 are edge directions (Borgwardt et al., 2022). This establishes a clear distinction between the stable core of polyhedral circuit theory—edge directions—and the unstable part created or destroyed by projection.

5. Equivalence classes in quantum circuits and algebraic circuit complexity

In quantum information, “circuit varieties” can mean families of circuits related by explicit equivalence rules and implementing the same overall transformation. The rules cataloged in “Equivalent Quantum Circuits” include null gates, control reversal, the principle of deferred measurement, quantum-classical substitution, distributed CNOT, the CNOT mirror rule, and the parallel-to-$M$5 CNOT rule (Garcia-Escartin et al., 2011). These identities generate equivalence classes of circuits for SWAP, teleportation, dense coding, and gate teleportation, so that visually distinct circuits can be treated as members of the same variety when they realize the same unitary transformation up to global phase and the same measurement statistics (Garcia-Escartin et al., 2011).

In circuit complexity, the term enters through varieties of languages recognized by circuit families. A base of gate types is defined by a variety $M$6 of regular commutative languages, and the corresponding constant-size circuit class is described by the block-product construction

$M$7

the Boolean algebra generated by languages $M$8 for finite partitions $M$9 of $M$0 and languages $M$1 (Czarnetzki et al., 2015). The paper proves that these are exactly the languages recognized by constant-size circuits over the base defined by $M$2, and it derives equations for the circuit class from equations for the gate variety (Czarnetzki et al., 2015).

The main theorem states that $M$3 is defined by equations of the form

$M$4

where $M$5 is a profinite identity holding in $M$6 and $M$7 are ultrafilters satisfying the stated compatibility conditions on lengths, substituted words, and position filters (Czarnetzki et al., 2015). This makes circuit classes themselves into variety-like objects in the sense of Stone duality and Boolean algebras of languages.

6. Topolectrical and topological LC circuit varieties

In condensed-matter-inspired electrical engineering, topolectrical circuits are electrical networks deliberately arranged as metamaterials so that their nodal voltages and currents realize the band structures and eigenmodes of lattice Hamiltonians (Sahin et al., 25 Feb 2025). Their linear steady-state behavior is encoded by the circuit Laplacian

$M$8

and the review classifies contemporary implementations into passive circuits, active operational-amplifier circuits, non-Hermitian circuits, nonlinear circuits, Floquet or time-modulated circuits, and synthetic or quantum-inspired circuits (Sahin et al., 25 Feb 2025). In that literature, “circuit varieties” denotes a taxonomy organized by the emulated physics: SSH chains, Chern and higher-order insulators, Weyl and Dirac semimetals, PT-symmetric dimers, exceptional points, non-Hermitian skin modes, nonlinear topological modes, Floquet frequency lattices, hyperbolic graphs, synthetic dimensions, and integrated high-frequency topological ICs (Sahin et al., 25 Feb 2025).

A closely related but more specialized construction appears in topological LC circuits built purely from inductors and capacitors. There the entire analysis is organized around a Lagrangian formalism and a Hermitian dynamical $M$9-matrix,

$M$0

which plays the role of a tight-binding Hamiltonian (Zhao, 2018). Zhao develops a modular design language based on loops, stars, and $M$1-shift permutation wiring, from which one obtains emergent pseudo-spin degrees of freedom and synthetic gauge fields (Zhao, 2018).

This framework realizes a sequence of topological circuit varieties: the SSH transmission line, the braided ladder analogous to the $M$2-flux ladder, two-dimensional Haldane and Hofstadter analogs, and a four-dimensional quantum Hall insulator with finite second Chern numbers (Zhao, 2018). The classification is controlled by winding numbers, Zak phases, first Chern numbers, and second Chern numbers computed from the $M$3-matrix, and the protected observables are electromagnetic edge modes localized at boundaries and interfaces (Zhao, 2018).

7. Engineered and learned systems

In technology studies, “circuit varieties” can denote different styles of information-processing hardware. “Evolution of Technologies and Multivalued Circuits” places multivalued logic within a larger taxonomy including binary digital circuits, multivalued digital circuits, analog circuits, and quantum circuits (Etiemble, 2019). The paper argues that classical multivalued circuits face fundamental disadvantages because the signal levels are totally ordered, extra levels require extra thresholds and more circuitry, and the reduction of $M$4 in modern CMOS further shrinks noise margins (Etiemble, 2019). It treats multilevel flash as the main practical exception and concludes that quantum devices are probably the only actual M-valued devices (Etiemble, 2019). In this usage, circuit varieties are technology-centered categories rather than algebraic varieties.

In mechanistic interpretability, a circuit is a subgraph of a transformer chosen to be necessary and sufficient for reproducing behavior on a task, and recent work studies the “varieties” of such circuits across data and prompt families (Wu et al., 15 Jun 2026). The paper distinguishes resampling variance, rephrasing variance, and sample-wise variance, and introduces CEAP, a conductance-based circuit discovery method with additive order preservation that reduces resampling variance relative to EAP-IG (Wu et al., 15 Jun 2026). It also shows that prompts with different templates tend to activate different circuits, so rephrasing variance reflects genuine multiplicity of task circuits rather than merely estimator noise (Wu et al., 15 Jun 2026).

The resulting picture is not that of a single canonical task circuit. Different prompt templates cluster into distinct circuits, sparsity fails to eliminate that dependence, and sample-wise extremes in unfaithfulness are often driven by the definition of unfaithfulness and by selective contribution scaling rather than by defective circuits (Wu et al., 15 Jun 2026). This suggests that, in learned systems, “circuit varieties” names a family of prompt-conditioned computational subgraphs rather than a unique mechanism for a semantic task.