Circuit-Level Decomposition

• Circuit-level decomposition is a systematic strategy that partitions circuits into submodules while preserving key behaviors like information-losslessness and native gate realizability.
• It finds applications in diverse areas such as logic synthesis, quantum compilation, and mechanistic interpretability, each with tailored criteria such as sparsity, depth reduction, and fidelity.
• By leveraging both discrete and continuous methods, this approach optimizes gate counts, routing overhead, and simulation complexity in practical circuit designs.

Circuit-level decomposition denotes a family of transformations in which a circuit, a circuit-derived object, or a circuit-relevant computational graph is split into structured subobjects whose composition preserves a target behavior while exposing optimization leverage. In the literature, this includes functional decomposition of switching functions through partitions and bipartite graphs, sparse decomposition of traffic matrices into switching configurations for circuit switches, lowering of quantum operations into native or elementary gate sets, partition-aware decompositions for circuit cutting, contextual decomposition of transformer circuits, and structure-preserving operator splitting or topological reduction for circuit models 0611024. This suggests that the phrase does not name a single algorithmic template; rather, it names a recurrent strategy in which the decomposition is judged by criteria such as information-losslessness, sparsity, depth, throughput, sampling overhead, faithfulness, or preservation of Hamiltonian and network structure.

1. Scope, objects, and invariants

Across the cited work, the decomposed object ranges from a switching function to a doubly stochastic matrix, a multi-qubit gate, a full unitary, a transformer computational graph, or a modified nodal analysis model. What remains stable is the insistence that the decomposition expose latent structure without discarding the property that matters for the task at hand. In logic circuits that property is information-losslessness; in circuit switching it is approximation quality under reconfiguration overhead; in quantum compilation it is native-gate realizability under depth or gate-count constraints; in mechanistic interpretability it is circuit faithfulness; and in circuit simulation it is preservation of energy-conserving and dissipative structure 0611024.

Domain	Decomposed object	Primary criterion
Logic circuits	Switching function	Information-lossless decomposition
Circuit switches	Traffic matrix	Sparse switching configurations
Quantum compilation	Gates or unitaries	Depth, CX-count, fidelity
Circuit cutting	Multi-qubit gates across a cut	Sampling-overhead reduction
Transformer circuits	Computational graph contributions	Faithfulness and pruning
Circuit models	pH-DAE or network matrix	Structure preservation

A common misconception is to treat circuit-level decomposition as synonymous with exact factorization into smaller pieces. The record here is broader. Some methods are exact, such as the classical Birkhoff–von Neumann representation of a doubly stochastic matrix with up to $(n-1)^2+1$ permutations or exact unitary decompositions via Quantum Shannon Decomposition. Others are explicitly approximate, such as $\epsilon$-approximate sparse switch scheduling, approximate gate decomposition traded against fault rate, or circuit discovery procedures that aim to recover model behavior with a strict subset of nodes (Valls et al., 2020, Krol et al., 2021, McKinney et al., 2023, Hsu et al., 2024).

2. Discrete and combinatorial decompositions in digital settings

In classical logic synthesis, functional decomposition is presented as parallel to the normalization of relational databases and governed by the same concepts of functional dependency (FD) and multi-valued dependency (MVD). Partitions play an important role, and the interdependency of two partitions can be represented by a bipartite graph. FD and MVD can themselves be represented by bipartite graphs with specific topological properties delineated by partitions of minterms, so the decomposition algorithms become procedures for constructing those specific bipartite graphs to meet information-lossless criteria [0611024].

In high-speed circuit switches, the decomposition target is a scaled doubly stochastic traffic matrix $T$. The scheduling problem is to find permutation matrices $P_1,\dots,P_K$ and durations $\alpha_1,\dots,\alpha_K$ such that

$$\left\|T-\sum_{k=1}^K \alpha_k P_k\right\|_F \le \epsilon,$$

with each $P_k$ representing a switching configuration and each $\alpha_k$ the fraction of the time window spent in that configuration. The classical Birkhoff–von Neumann decomposition gives an exact representation but does not quantify how well an incomplete sum approximates $T$. The 2020 revisit establishes that, by using a subset of the admissible permutation matrices, Birkhoff’s algorithm obtains an $\epsilon$-approximate decomposition with at most $\epsilon$0 permutations, and Theorem III.3 gives linear convergence with a uniform lower bound $\epsilon$1 (Valls et al., 2020).

The same work introduces Birkhoff+, which combines Frank–Wolfe with Birkhoff’s approach. Its barrier objective is

$\epsilon$2

and each iteration chooses the steepest admissible permutation according to the current gradient, then applies the largest feasible Birkhoff step. Numerically, Birkhoff+ is reported as 10–100× faster in practice, and at the circuit level Birkhoff+(10) yields 7% higher throughput than the best prior heuristic for $\epsilon$3 and $\epsilon$4; when the configuration-computation time is counted as lost transmission time, the throughput gain increases to 34%. The baselines include Solstice [Liu et al’15], Eclipse [Bavarian et al’16], classical Birkhoff, Frank–Wolfe, and fully-corrective Frank–Wolfe (Valls et al., 2020).

A related logical-computational notion appears in CNF decomposition of global-constraint propagators. There, a propagator has a polynomial size decomposition if and only if it can be computed by a polynomial size monotone Boolean circuit, and lower bounds on monotone Boolean circuits translate to lower bounds on decomposition size. The cited consequence is that there is no polynomial sized decomposition of the domain consistency propagator for the ALLDIFFERENT constraint (0905.3757). This suggests that, in discrete settings, circuit-level decomposition is often limited not only by synthesis heuristics but by structural lower bounds.

3. Quantum gate-set lowering, routing, and unitary synthesis

In quantum compilation, circuit-level decomposition is frequently the problem of lowering a target operation into a basis gate set while co-optimizing routing, gate count, and execution fidelity. MIRAGE makes this explicit by combining decomposition and routing through mirror gates. For any two-qubit unitary $\epsilon$5, the mirror gate is defined by

$\epsilon$6

where $\epsilon$7 is the SWAP permutation matrix. MIRAGE focuses on the $\epsilon$8 family, uses mirror gates to reduce routing pressure and reduce true circuit depth instead of just minimizing $\epsilon$9s, and evaluates $T$0 and $T$1 with mirror substitutions at different aggression levels. For square-lattice topologies, it provides an average of 29.6% reduction in circuit depth by eliminating an average of 59.9% $T$2 gates; on IBM’s heavy-hex 57-qubit topology, the depth fell by 31.2% and SWAPs by 56.2% (McKinney et al., 2023).

MIRAGE also frames decomposition geometrically through Weyl coordinates and monodromy polytopes. In the reported coverage analysis, allowing mirrors changes the volume of two-qubit unitaries reachable in $T$3 layers of a fixed basis gate. For $T$4 at $T$5, the Haar-weighted chamber coverage rises from 79.0% to 94.4% when mirrors are allowed. For the approximate-plus-mirror setting, the reported Haar and fidelity table gives, for example, $T$6 with Haar 0.9165 and mirror Haar 0.8453, while mirror fidelity is 0.9913. The paper summarizes these results as mirrors plus approximation reducing the Haar score by up to 8–9% relative (McKinney et al., 2023).

At the opposite end of the compilation stack, Quantum Shannon Decomposition provides a recursive exact decomposition of an arbitrary $T$7-qubit unitary. The implementation cited bases itself on Quantum Shannon Decomposition and states that it generates $T$8 controlled-not gates for an $T$9-qubit input gate. The exact recurrence given is

$P_1,\dots,P_K$0

with closed form

$P_1,\dots,P_K$1

The same source reports that the resulting circuits are up to 10 times shorter than other methods in the field, and that compared to Qubiter the implementation generates circuits with half the number of CNOT gates and a third of the total circuit length, while also being up to 10 times as fast (Krol et al., 2021).

A third line replaces discrete synthesis by continuous optimization. Adaptive circuit compression parameterizes the approximating circuit using single-qubit $P_1,\dots,P_K$2 gates and parametric two-qubit $P_1,\dots,P_K$3 gates, minimizes a Frobenius-norm or Hilbert–Schmidt cost, and then compresses the circuit by sequentially removing two-qubit blocks and re-optimizing the remaining parameters. In the reported benchmarks, SQUANDER achieved more than 50% reduction in CNOT count in 21% of cases and more than 10% reduction in 68% of cases while keeping $P_1,\dots,P_K$4; the 4-qubit adder was compressed from 66 CNOTs to 8 CNOTs (Rakyta et al., 2022). This suggests that quantum circuit-level decomposition spans both constructive exact recursions and variationally compressed approximations.

4. Partition-aware and multilevel decomposition in quantum compilers

A separate quantum use of circuit-level decomposition appears when the circuit is to be cut into subcircuits. The partition-aware method for circuit cutting changes the decomposition strategy of multi-qubit gates before they are expanded into single-qubit and two-qubit gates. Standard practice decomposes MCX or CCCX into CNOTs and single-qubit rotations and then cuts the resulting two-qubit gates, paying quasi-probability overhead per cut. The proposed strategy instead recasts each multi-qubit gate so that only a minimal number of two-qubit gates, ideally a single CNOT, crosses the chosen bipartition boundary by inserting a small number of ancilla qubits, one on each side of the cut (Tamura et al., 27 Mar 2026).

The paper gives explicit decompositions. For CCCX, dec2A uses two ancillas and two cross-boundary CNOTs, with total CNOT count 20 and overhead $P_1,\dots,P_K$5 without classical communication or $P_1,\dots,P_K$6 with. The variant dec2Ad omits the uncomputing CNOT on the target side, leaves one ancilla dirty, reduces the total CNOT count to 18, and uses only one cross-boundary CNOT. Its sampling overhead is

$P_1,\dots,P_K$7

improving on the prior direct ZX-cut overhead $P_1,\dots,P_K$8 (Tamura et al., 27 Mar 2026).

Multilevel Circuit Optimization (MLCO) generalizes the same principle from cutting to compiler design. Rather than immediately expanding every multi-controlled gate to single- and two-qubit gates, MLCO introduces a hierarchy of gate sets and alternates simplification with selective lowering:

$P_1,\dots,P_K$9

The cited case study uses three levels: HiGS, MiGS, and LoGS. The v-chain decomposition of a $\alpha_1,\dots,\alpha_K$0-controlled $\alpha_1,\dots,\alpha_K$1 into MiGS uses $\alpha_1,\dots,\alpha_K$2 CCX gates and one CRZ, and only later decomposes CCX and CRZ into LoGS (Onodera et al., 14 May 2025).

The central compiler claim is that MLCO makes visible higher-level circuit structures, providing insights about how to simplify the circuits and how to decompose the gates. In the reported Hamiltonian-simulation case study, the source circuit is densely populated with multi-controlled gates and is transformed by a state-of-the-art circuit compiler to a target circuit with the quadratic number of CX gates in the number of qubits. By putting the right circuit structure in place and selecting the right decomposition algorithm, the authors report massive cancellation of entangling gates and a quadratic reduction in the number of CX gates. The asymptotic contrast stated in the detailed account is from $\alpha_1,\dots,\alpha_K$3 in the naive DETO route to $\alpha_1,\dots,\alpha_K$4 after MLCO simplification and lowering, with about 37 CX per step for $\alpha_1,\dots,\alpha_K$5 versus about 100 CX per Trotter step under DETO (Onodera et al., 14 May 2025).

5. Contextual decomposition and circuit discovery in transformers

In mechanistic interpretability, circuit-level decomposition refers to isolation of a computational subgraph in a model that is responsible for a specific behavior. Contextual Decomposition for Transformers (CD-T) treats a transformer as a directed acyclic graph whose nodes are activations of components such as token embeddings, attention heads, and feed-forward networks. Each activation is split into a feature-of-interest component and a remainder:

$\alpha_1,\dots,\alpha_K$6

The method then propagates this split recursively through linear layers, ReLUs, and self-attention. For a linear layer $\alpha_1,\dots,\alpha_K$7, the split is

$\alpha_1,\dots,\alpha_K$8

For self-attention, the values are decomposed while the attention weights themselves are not split, so the head output is written as

$\alpha_1,\dots,\alpha_K$9

These equations define a fine-grained contribution analysis at the level of attention heads and specific sequence positions (Hsu et al., 2024).

CD-T uses those propagated contributions to score candidate nodes and then prune the graph recursively. The contribution score reported in the detailed description is

$$\left\|T-\sum_{k=1}^K \alpha_k P_k\right\|_F \le \epsilon,$$0

where $$\left\|T-\sum_{k=1}^K \alpha_k P_k\right\|_F \le \epsilon,$$1 is a candidate component and $$\left\|T-\sum_{k=1}^K \alpha_k P_k\right\|_F \le \epsilon,$$2 is the current receiver set. The abstract states that CD-T can produce circuits of arbitrary level of abstraction, is the first able to produce circuits as fine-grained as attention heads at specific sequence positions efficiently, and reduces circuit discovery runtime from hours to seconds compared to state-of-the-art baselines (Hsu et al., 2024).

The evaluation claims are unusually strong and sharply formulated. On three standard circuit evaluation datasets—indirect object identification, greater-than comparisons, and docstring completion—CD-T outperforms ACDC and EAP by better recovering the manual circuits with an average of 97% ROC AUC under low runtimes. The same abstract reports that the discovered circuits are 80% more faithful than random circuits of up to 60% of the original model size, and that CD-T circuits can perfectly replicate original models’ behavior, with faithfulness $$\left\|T-\sum_{k=1}^K \alpha_k P_k\right\|_F \le \epsilon,$$3, using fewer nodes than the baselines for all tasks (Hsu et al., 2024). This suggests that circuit-level decomposition in interpretability is less about synthesis into primitive operations than about isolating causal contribution paths inside an existing computation graph.

6. Structure-preserving decomposition of circuit models

For circuit models in simulation and quantization, the decomposition target is often not a gate sequence but a dynamical or topological representation. In modified nodal analysis formulated as a port-Hamiltonian DAE,

$$\left\|T-\sum_{k=1}^K \alpha_k P_k\right\|_F \le \epsilon,$$4

the classical JR decomposition splits the right-hand side into a purely conservative part and a dissipative-plus-input part. Because standard JR decomposition is restricted for circuit models, an enhanced JR-decomposition is introduced for MNA. It moves voltage-source terms so that both split operators remain solvable as index-1 subsystems:

$$\left\|T-\sum_{k=1}^K \alpha_k P_k\right\|_F \le \epsilon,$$5

The stated properties are $$\left\|T-\sum_{k=1}^K \alpha_k P_k\right\|_F \le \epsilon,$$6 and $$\left\|T-\sum_{k=1}^K \alpha_k P_k\right\|_F \le \epsilon,$$7, and the numerical recipe is a Strang splitting with half-step conservative solve, full-step dissipative solve, and half-step conservative solve (Bartel et al., 4 Jun 2026).

The theoretical claims attached to this split are explicit. Proposition 3.1 states that, under the case-(a) or case-(b) assumptions for an index-1 pH-DAE, any splitting method of ODE order $$\left\|T-\sum_{k=1}^K \alpha_k P_k\right\|_F \le \epsilon,$$8 applied to the enhanced JR-decomposition yields overall order $$\left\|T-\sum_{k=1}^K \alpha_k P_k\right\|_F \le \epsilon,$$9 for both differential and algebraic components. Theorem 3.2 states that if the underlying solvers in the Strang steps are at least second order, then the global method achieves second-order convergence on $P_k$0 in both differential and algebraic components. The numerical example on coupled transmission lines reports that midpoint-based variants preserve the discrete dissipation inequality, while 3-mid and 3-Radau variants exhibit clear second-order convergence (Bartel et al., 4 Jun 2026).

A complementary topological decomposition appears in reciprocal lumped-element superconducting circuits. There, the central object is the network matrix $P_k$1, an integer matrix encoding how inductive loops pass capacitive nodes. The goal is to find unimodular integer transformations $P_k$2 and $P_k$3 such that

$P_k$4

with $P_k$5. By successive row and column pivots on $P_k$6, the circuit model is transformed into a simplest equivalent “fundamental” form in which the harmonic degrees of freedom are separated out from the Josephson junctions and phase slip wires (Smitham et al., 2024).

The resulting Hamiltonian decomposes into continuous-spectrum modes, discrete-charge modes, and discrete-flux modes. The significance claimed for this pivoting procedure is that structure-preserving integer pivots on $P_k$7 map the circuit to an equivalent one without changing its Hamiltonian, identify and isolate harmonic modes from nonlinear junction and phase-slip elements, and can dramatically reduce the size of the simulation Hilbert space (Smitham et al., 2024). This suggests that, in physical circuit models, circuit-level decomposition functions as a structure-preserving change of variables rather than as a mere partition into smaller simulation blocks.