Circuit Discovery Techniques

• Circuit discovery techniques are algorithmic methods that extract and characterize sparse, directed sub-networks essential for specific behaviors in neural, quantum, and physical models.
• They employ methods such as activation patching, gradient-based attributions, and differentiable masking to optimize for faithfulness, sparsity, and computational efficiency.
• These techniques enhance mechanistic interpretability and model reduction, enabling targeted auditing and applications in language processing, vision systems, quantum computing, and physical chip analysis.

Circuit discovery techniques encompass the suite of algorithmic methods and theoretical frameworks designed to extract, characterize, and validate sparse, functionally causal sub-networks—“circuits”—that implement particular behaviors or represent specific concepts within neural networks. The impetus spans mechanistic interpretability in large-scale language and vision models, quantum circuit synthesis, and even physical chip analysis. Circuit discovery is central to understanding, auditing, and potentially controlling complex model behaviors, as well as advancing efficient, mechanistically faithful model reduction.

1. Formal Definition and Problem Formulation

A circuit, across most domains, is rigorously defined as a sparse, directed acyclic subgraph of either a computational model (e.g., neural network, quantum algorithm) or a physical integrated circuit, whose internal flow or computations are necessary and sufficient for a particular behavior or concept (Kwon et al., 3 Aug 2025, Conmy et al., 2023).

Given a model's computational graph $G = (V, E)$, a circuit $C = (V_C, E_C)$ is a subgraph minimizing $|C|$ such that the behavior of interest—quantified by a metric $M$ over a distribution of relevant inputs—is preserved within $\epsilon$ loss of the original. Typical formalizations include: $\min_{C \subseteq G} \; F(C) + \lambda |E_C|$ where $F(C)$ measures discrepancies (e.g., $D_{\mathrm{KL}}$ between model and circuit outputs) (Conmy et al., 2023, Bian et al., 26 Feb 2026).

In quantum circuit discovery, the circuit is a gate sequence or diagram that achieves a task-specific input-output mapping at minimal width/depth/gate count under hardware constraints (Potoček et al., 2018, Zen et al., 2024).

In physical IC analysis, circuits are subregions or blocks identified as responsible for observed or manipulated behaviors through spatially resolved external measurements (Saß et al., 2023).

2. Core Algorithmic Methodologies

Principal circuit discovery algorithms span intervention-based methods (patching, ablation), gradient- and relevance-based attributions, information-theoretic optimization, and combinatorial search.

2.1 Activation-Based and Patching Methods

Activation Patching (AP) modifies intermediate activations along candidate edges by replacing (patching) them with values from ablated/counterfactual inputs, then quantifies output change under each intervention (Conmy et al., 2023). Patching is sequentially performed, and edges for which ablation does not degrade task performance are iteratively pruned, typically yielding circuits that closely match hand-labeled ground truth but at immense computational cost.

Automated Circuit DisCovery (ACDC) formalizes this as a greedy edge-removal process. Each edge $e$ is pruned if the metric drop $\Delta M_e$ is below threshold $\tau$ (Conmy et al., 2023). Subnetwork probing extends this by learning continuous masks, optimized to trade off performance fidelity and sparsity.

Path-level ablation further accounts for combinatorial dependencies by identifying entire chains/pathways rather than individual edges (Chen et al., 2024).

2.2 Fast Approximations: Attribution and Relevance

Attribution Patching (AP/AtP, EAP) replaces the patching intervention with a first-order Taylor approximation, computing edge importance as the dot product between the activation difference and the gradient of the metric with respect to that edge's input. This method dramatically reduces compute, requiring just two forwards and one backward pass per batch (Syed et al., 2023).

Relevance Patching (RelP) substitutes local gradients in AP with Layer-wise Relevance Propagation coefficients, delivering substantially more faithful attributions—particularly in deep, nonlinear locations—while matching the AP computational profile (Jafari et al., 28 Aug 2025).

2.3 Information-Bottleneck and Differentiable Masks

Information Bottleneck Circuit Discovery (IBCircuit) formulates circuit extraction as a minimization of the mutual information between the compressed circuit and the remainder of the graph, while retaining predictive information about the target (Bian et al., 26 Feb 2026). Stochastic, differentiable “information gates” parameterized by continuous masks (often hard-concrete) are optimized via gradient descent to jointly minimize spurious capacity and maximize task faithfulness.

Differentiable Graph Pruning (DiscoGP, Multi-Granular Node Pruning) employs straight-through estimators or stochastic binary masks across weights, edges, or nodes, training via backpropagation to optimize a composite objective targeting functional faithfulness, completeness (minimizing the residual utility of the complement subgraph), and sparsity (Haider et al., 11 Dec 2025, Yu et al., 2024).

2.4 Circuit Probing and Auxiliary Objectives

Circuit Probing uses auxiliary optimization objectives (e.g., contrastive or partitioning losses) to isolate subnetworks that compute hypothesized intermediate variables. After mask optimization, ablation of the identified subnet yields causal verification via performance collapse (Lepori et al., 2023).

2.5 Contextual Decomposition and Linear Approaches

Contextual Decomposition for Transformers (CD-T) linearly decomposes activations into streams attributable to different sources and recursively propagates this separation through all modules. CD-T enables single-pass extraction of circuit subgraphs at arbitrary granularity while preserving dataflow correctness (Hsu et al., 2024, Ge et al., 2024).

2.6 Quantum and Physical Circuit Discovery

Reinforcement learning automates quantum circuit synthesis by sequentially proposing gate operations subject to hardware constraints and maximizing a task-specific reward designed to penalize resource use and lack of robustness (Zen et al., 2024).

Physical IC circuit discovery leverages external stimuli—such as voltage modulation, lock-in thermography, and laser logic-state imaging—to empirically map active regions corresponding to targeted functions. These techniques reduce the in-die search space for further analysis by over 90% (Saß et al., 2023).

3. Evaluation Protocols and Empirical Metrics

Faithfulness, completeness, and sparsity are core evaluation axes for discovered circuits:

• Faithfulness: Output preservation when only the circuit is active, typically measured as task accuracy, top-1 stability, recovered logit fraction, or divergence from the full model (Kwon et al., 3 Aug 2025, Yu et al., 2024).
• Completeness: Drop in output performance when the circuit is removed, quantifying whether the circuit is necessary for function (Yu et al., 2024).
• Minimality/Sparsity: Number or density of surviving edges/nodes/weights (Haider et al., 11 Dec 2025, Potoček et al., 2018).
• Robustness guarantees: Verified circuits maintain behavior across continuous input or patching domains (Hadad et al., 18 Feb 2026).
• AUC/ROC: Fraction of ground-truth or hypothesized circuit components correctly recovered versus spurious inclusions (Conmy et al., 2023, Syed et al., 2023).
• User study: Human raters assess coverage, relevance, and interpretability (e.g., in concept circuits) (Kwon et al., 3 Aug 2025).

Example outcomes:

• In Granular Concept Circuits, circuit ablation caused an 8.60 pp logit drop on ResNet50 and 33.85 pp accuracy drop on Vision Transformers; random ablations yielded <2.5 pp drop (Kwon et al., 3 Aug 2025).
• In RelP, Pearson correlation with full activation patching (AP) on MLP outputs rose from 0.006 (AtP) to 0.956 (RelP) (Jafari et al., 28 Aug 2025).

4. Architectural Scope, Extensions, and Scalability

Circuit discovery techniques are designed to generalize across architectures:

• CNNs, Vision Transformers, and multi-modal models: GCC operates on both channel-based (CNN) and dimension-based (ViT, Swin-Tiny, CLIP-ViT) units (Kwon et al., 3 Aug 2025).
• LLMs and Transformers: Edge patching, node pruning, and relevance-based methods all explicitly target attention heads, MLP subunits, or even individual neurons (Haider et al., 11 Dec 2025, Hatefi et al., 16 Jun 2025, Hsu et al., 2024).
• Quantum: RL-based circuit discovery is adapted to hardware-specific constraints, e.g., connectivity graphs, gate sets (Zen et al., 2024).
• Physical circuits: LIT and LLSI work regardless of IC node technology (applied up to sub-100 nm CMOS) (Saß et al., 2023).

Major advances in computational scalability include mixed-precision inference (PAHQ achieves 80% runtime, 30% memory reduction over ACDC) (Wang et al., 27 Oct 2025), multi-granular fine-tuning (node/edge-level masking in a single run), and single-pass linear decompositions.

5. Comparisons, Strengths, and Limitations

A spectrum of approaches yields different trade-offs:

Methodology	Faithfulness/Completeness	Sparsity	Computational Cost	Key Limitation
Activation Patching / ACDC	High (Edge/Node)	Moderate	O(	E
Attribution Patching / Relevance	High (approximate)	High	2F + 1B	May miss higher-order dependencies
Information Bottleneck (IBCircuit)	High (joint node/edge)	High	Single pass, backprop	β parameter tuning, thresholding
Differentiable Node/Edge Pruning	High (multi-level)	Very High	Single fine-tuning run	Mask initialization, global minima
Path-level/Contextual methods	Very High (pathwise)	High	Pruning + mediation	O(N²) time, agnostic to metric variants
Reinforcement Learning (Quantum)	Variable	High	Millions of episodes	Reward shaping, scalability
LIT / LLSI (Physical)	High (spatial mapping)	N/A	Hours (LIT), Days (LLSI)	Limited to accessible regions/signals

Notable limitations include the need for careful metric and threshold selection (Conmy et al., 2023), inadequate representation of inhibitory/negative-contribution units in patching-based methods, potential for over- or under-estimation in gradient-based scores (Syed et al., 2023), and computational intractability of full verification for very large-scale models (Hadad et al., 18 Feb 2026).

6. Impact, Generalization, and Applications

Circuit discovery methods have realized several research and practical impacts:

• Mechanistic interpretability: Prompted mechanistic reversals of LLM behaviors (e.g., identification of name-mover heads in indirect object identification (Jafari et al., 28 Aug 2025)).
• Model compression and auditing: Ultra-sparse, faithful circuits are adopted for efficient deployment and targeted correction of spurious model outputs (Hatefi et al., 16 Jun 2025, Haider et al., 11 Dec 2025).
• Novel behavioral auditing: Circuits highlighting concepts (e.g., via GCC) facilitate fine-grained audit of model misclassifications and disentanglement of overlapping or distributed representations (Kwon et al., 3 Aug 2025).
• Quantum circuit optimization: RL-based frameworks discover hardware-efficient, fault-tolerant logical state preparation circuits not previously found by hand (Zen et al., 2024).
• Physical security and reverse engineering: LIT/LLSI enable mapping of custom, undocumented ICs, reducing search overhead for physical security analyses by up to 98% (Saß et al., 2023).

Extensions are recommended for self-supervised, multi-modal, and generative models, dynamic and compositional circuit discovery, and for the principled integration of verification guarantees into practical pipelines (Hadad et al., 18 Feb 2026, Kwon et al., 3 Aug 2025).

7. Future Directions and Open Problems

Ongoing research aims to address the following:

• Provable Guarantees: Integrating neural network verification tools (e.g., α-3-CROWN) to certify circuit robustness over input and patching domains, at the expense of computational practicality for very large models (Hadad et al., 18 Feb 2026).
• Hybridization: Combining rapid pruning (Attribution/RelP) with slower but more precise patching or verification on reduced subgraphs (Syed et al., 2023, Jafari et al., 28 Aug 2025).
• Holistic and Multi-skill Circuits: Path-level/skill-path frameworks (Chen et al., 2024) and holistic mutual-information objectives (Bian et al., 26 Feb 2026) to capture the compositional and multi-functional nature of circuits.
• Physical/Hardware Generalization: Expansion of modulation, lock-in, and laser-based methods for heterogeneous and increasingly opaque IC technologies (Saß et al., 2023).
• Automated Semantic Labeling: Integrating circuit discovery with semantic labeling and causal “scrubbing” could bridge low-level circuit mechanics and high-level behavior explanation (Conmy et al., 2023).

These developments collectively define a rapidly evolving landscape, pushing circuit discovery from heuristic and noisy subgraph isolation towards precise, robust, and holistic mechanistic modeling across neural, quantum, and physical computation.