Bit-Serial Enable Stage Fusion (BESF)

• BESF is a novel approach that unifies the prediction and execution stages of dynamic sparsity attention using bit-serial processing.
• It employs progressive, just-in-time pruning with adaptive token selection (LATS) to dramatically reduce memory traffic and computational workload.
• Experimental results in the BitStopper accelerator demonstrate up to 3.2× speedup and enhanced energy efficiency with minimal impact on LLM quality.

Bit-Serial Enable Stage Fusion (BESF) is an algorithmic and architectural mechanism introduced in the BitStopper accelerator to improve the efficiency of dynamic sparsity (DS) attention in LLMs. BESF fuses the traditional prediction and execution stages of DS attention by interleaving them at bit-level granularity, allowing for progressive, just-in-time pruning of trivial tokens and direct reuse of partial dot-product computations. This enables substantial reductions in memory traffic and computational workload, leading to marked improvements in throughput and energy efficiency over prior Transformer accelerators (Wang et al., 6 Dec 2025).

1. Conventional Dynamic-Sparsity Attention: Structure and Limitations

Traditional DS attention operates using a two-stage workflow:

• Prediction Stage: Computes a low-bitwidth approximation of the attention score matrix $A = QK^T$ using quantized queries ($Q$) and keys ($K$), typically with a 4-bit precision. A selection (e.g., top-$k$ or thresholding) then retains high-scoring $K$ vectors. However, this stage must read the entire $K$ matrix from DRAM, leading to high memory IO and power consumption.
• Execution Stage: Performs high-precision (e.g., INT12) dot-products on the retained $Q$-$K$ pairs to compute attention output $\mathbf{O} = \mathrm{softmax}(A/\sqrt{d_h}) V$. Despite reduced arithmetic, this stage duplicates certain compute and cannot reuse work from the predictor due to decoupling.

Fundamental constraints include excessive predictor IO, a lack of computational reuse between stages, and insufficient adaptivity due to static pruning thresholds.

2. BESF Algorithmic Principle and Pipeline

BESF replaces the two-stage DS pipeline with a single, bit-serial process that unifies prediction and execution:

• Bit-Serial Pruning: Both $Q$ and $Q$0 are quantized as $Q$1-bit signed integers. Each $Q$2 is decomposed into $Q$3 bit-planes:

$Q$4

• For each query $Q$5, a running partial inner-product $Q$6 is formed as the sum over received bit-planes:

$Q$7

• After each round $Q$8, BESF computes for each surviving token:
  • The exact partial sum $Q$9,
  • An upper-bound margin $K$0 reflecting the possible contribution of unprocessed lower bit-planes.
  • Any candidate $K$1 satisfying $K$2 (threshold) is pruned.

No separate predictor is invoked; each dot-product partial result is directly reused for final attention weight computation in surviving tokens.

3. Algorithmic Steps and Pseudocode

The BESF process can be formalized as follows:

1. Precompute bit-margins (for each query $K$3): For $K$4 to $K$5, compute possible min/max dot-product contributions for unknown remaining bits.
2. Initialize survivors: Set all $K$6 possible tokens as candidates.
3. Bit-plane rounds ($K$7 to $K$8):
   • For each candidate $K$9, fetch $k$0 and update $k$1; compute margin.
   • Determine dynamic pruning threshold $k$2 (see LATS below).
   • Prune any $k$3 where $k$4.
4. Final computation: For survivors, complete the high-precision dot-product and output attention with $k$5.

The above is operationalized in highly parallel hardware. The bit-uncertainty margins are computed based on the process order and the sign of $k$6 (Wang et al., 6 Dec 2025).

4. Mathematical Analysis: Complexity and Memory-Access Gains

Analytical complexity for various attention architectures is summarized below:

Attention Type	Compute Operations	Memory Reads
Dense	$k$7	$k$8, $k$9 (size $K$0), outputs
Two-stage DS	$K$1	All $K$2 for prediction, survivors $K$3 for execution
BESF	$K$4	$K$5 bit-planes of $K$6

In practice, BESF achieves a $K$7 reduction in both bit-planes fetched and computation, as for optimized $K$8, $K$9. BESF keeps average perplexity degradation below 0.1 for LLaMA2-7B (INT12 quant, $K$0 sequence), confirming negligible model quality loss (Wang et al., 6 Dec 2025).

5. Adaptive Token Selection and Early Termination (LATS)

The LATS (Lightweight and Adaptive Token Selection) mechanism complements BESF by dynamically deriving the pruning threshold $K$1 at each bit-plane round:

• The threshold is set as

$K$2

where $K$3 is a lower bound on score given processed bits.

• This ensures that pruning adapts to the current score distribution, avoiding over- or under-pruning.
• Only tokens whose upper-bounded scores cannot surpass $K$4 are removed, eliminating memory fetches for their remaining bits.

The LATS module operates in tandem with the BESF pipeline, broadcasting $K$5 per round to all processing elements.

6. Hardware Realization and Microarchitectural Features

BitStopper, the hardware implementation of BESF, is partitioned into specialized processing units:

• QK-PU (Query-Key Processing Unit):
  • 32 bit-serial PE lanes, each processing a candidate key.
  • A bit-serial reusable AND-tree (BRAT) for $K$6 operations.
  • Scoreboard (on-chip buffer) and pruning engine coordinating partial sums, margins, and dynamic thresholding.
  • Bit Margin Generator and LATS module for bit-level adaptivity and early token termination.
• V-PU (Value Processing Unit):
  • Lookup-table-based softmax computation and 64× INT12 MAC array for final attention output.

Bit-level asynchronous processing (BAP) enables per-lane, out-of-order fetching for bit-planes, increasing PE utilization from $K$7 to $K$8 by overlapping memory access with computation.

Hardware cost: Margin generator plus LATS adds $K$9 area and $Q$0 power, while Scoreboard plus pruning engines add $Q$1 area and $Q$2 power. The total die area is $Q$3 at 28 nm, 1 GHz. Peak energy efficiency is $Q$4.

7. Quantitative Performance and System-Level Impact

BESF, as realized in BitStopper, demonstrates the following system-wide benefits on LLaMA2-7B (INT12 quant, $Q$5 token sequence):

• Memory Access Reduction:
  • $Q$6 (Sanger), $Q$7 (SOFA w/o fine-tune), $Q$8 (SOFA* w/ fine-tune)
• Throughput Gains:
  • $Q$9 (dense baseline), $K$0 (Sanger DS), $K$1 (SOFA DS)
• Energy Efficiency:
  • $K$2 (dense baseline), $K$3 (Sanger), $K$4 (SOFA)
• Ablation Breakdown (LLaMA-7B, Dolly, $K$5 tokens):
  • BESF core fusion: $K$6 speedup
  • +BAP (async fetching): $K$7 (increased PE utilization)
  • +LATS (adaptive pruning): total $K$8 speedup
• Model Quality: Perplexity penalty remains below $K$9 for appropriate $\mathbf{O} = \mathrm{softmax}(A/\sqrt{d_h}) V$0, with $\mathbf{O} = \mathrm{softmax}(A/\sqrt{d_h}) V$1 of bit-planes retained on average.

In summary, BESF unifies prediction and execution in DS attention, realizes significant memory and computation reductions via bit-serial progressive pruning, and, with LATS and BAP, underpins the efficiency of the BitStopper accelerator. These advances establish a new standard for fine-grained Transformer optimization, delivering $\mathbf{O} = \mathrm{softmax}(A/\sqrt{d_h}) V$2–$\mathbf{O} = \mathrm{softmax}(A/\sqrt{d_h}) V$3 speedups and $\mathbf{O} = \mathrm{softmax}(A/\sqrt{d_h}) V$4–$\mathbf{O} = \mathrm{softmax}(A/\sqrt{d_h}) V$5 energy efficiency improvements with negligible hardware overhead (Wang et al., 6 Dec 2025).