BitStopper: Transformer Accelerator & Optical Buffer

• BitStopper is a dual-purpose technology combining a transformer-attention accelerator for dynamic sparsity and an optical pulse buffer using engineered Bragg gratings.
• In digital deep-learning hardware, BitStopper employs BESF, LATS, and BAP to reduce memory traffic and enhance energy efficiency by up to 2.4× over existing accelerators.
• In silicon photonics, BitStopper uses chirped and uniform Bragg gratings with a defect for robust optical pulse trapping, enabling buffering at 50–100 Gbit/s.

BitStopper refers to two distinct high-performance devices developed for efficient buffering or acceleration in digital and photonic hardware domains. In advanced deep-learning hardware, BitStopper is a transformer-attention accelerator based on a fine-grained bit-serial algorithm-architecture co-design for dynamic sparsity attention (Wang et al., 6 Dec 2025). In photonics, BitStopper is also the term for an optical-pulse buffer leveraging concatenated Bragg gratings with nonlinear trapping and slow-light functionality (Fu et al., 2013). This entry systematically presents both the digital-accelerator and photonic-buffer concepts, their architectures, operation, and implementation characteristics.

1. Transformer-Attention Acceleration via BitStopper

BitStopper is an integrated accelerator that directly addresses compute and memory bottlenecks in LLM attention, particularly under dynamic sparsity (DS) regimes. Conventional DS accelerators rely on a dual-stage predictor-executor workflow that imposes significant additional memory accesses and compute overhead. BitStopper, by contrast, removes this explicit prediction stage and exploits fine-grained bit-serial execution and algorithmic-hardware fusion (Wang et al., 6 Dec 2025).

The architecture is driven by three interlocked strategies:

• Bit-Serial Enabled Stage Fusion (BESF)
• Lightweight and Adaptive Token Selection (LATS)
• Bit-Level Asynchronous Processing (BAP)

These elements jointly enable reduced data movement, adaptive and speculative computation, and decoupled memory access for high utilization.

2. Bit-Serial Enabled Stage Fusion (BESF)

BESF eliminates the explicit two-stage DS predictor used in previous accelerators. Traditional approaches compute candidate sparse indices by running a low-precision predictor over the entire Key matrix, followed by high-precision execution, causing duplicated memory traffic (up to 3× compute-stage power for 2K sequence length).

BESF interleaves prediction and execution in a bit-serial fashion. Each Key $K_j$ is stored as a 12-bit integer. For each Query $Q_i$ and each bit-plane $r$ (MSB to LSB), the partial dot-product $\Delta A_r(i, j) = Q_i \cdot K_j^r$ is accumulated:

$$A_r(i, j) = A_{r-1}(i, j) + \Delta A_r(i, j) \, ,\, A_{-1} = 0$$

Using an uncertainty margin calculated from the yet-unused bits, BESF prunes $K_j$ early if it cannot possibly exceed the evolving query-specific threshold, so tokens are dropped after only a subset of bit-planes are accessed. This reduces the average Key bit-plane fetch count to $\approx 4{-}6$ versus 12 (full precision). Across Llama-7B at 4K sequence length, DRAM accesses are reduced by $2.1\times$ compared with SOFA (Wang et al., 6 Dec 2025).

3. Lightweight and Adaptive Token Selection (LATS)

LATS adapts the threshold for keeping Key tokens per Query and per bit round, exploiting the observation that, in softmax, $a_j$ with $a_\mathrm{max} - a_j$ exceeding a radius $Q_i$0 contributes negligibly.

For each bit-plane round $Q_i$1, the adaptive threshold is

$Q_i$2

where $Q_i$3 is the lower bound of the maximum achievable dot-product for $Q_i$4 given the already-fetched partial sum and maximal/minimal possible contribution of the remaining bits, and $Q_i$5, $Q_i$6 by default.

The token is pruned if $Q_i$7. LATS is implemented via a small lookup table for precomputed bit-margins $Q_i$8 and $Q_i$9. This design ensures precision-controlled dynamic sparsity without fixed top-$r$0 selection.

LATS pseudocode expresses the incremental process: $$A_r(i, j) = A_{r-1}(i, j) + \Delta A_r(i, j) \, ,\, A_{-1} = 0$$9

4. Bit-Level Asynchronous Processing (BAP)

BAP addresses bandwidth and latency stalls in the bit-serial BESF scheme. A strict in-order bit-plane fetch would stall PEs on DRAM latency. BAP issues requests for the MSB plane of all Keys in parallel; as soon as any $r$1 returns, its bit-serial lane processes the partial dot and decides pruning or continued fetch.

This out-of-order fetch/compute keeps PE utilization high—rising from 48% under in-order BESF to 83% with BAP, yielding a $r$2 speedup on top of BESF alone (Wang et al., 6 Dec 2025).

5. BitStopper Hardware Architecture and Dataflow

The BitStopper chip implements:

• QK-PU: 32 bit-serial PE lanes with per-lane Scoreboard and Pruning Engine, on-chip LUTs for bit-margins, and a central LATS module.
• V-PU: 64-way, INT12 MAC array for S $r$3 V computation and LUT-based softmax.
• DRAM: HBM2, 8$r$4128 bits @2 Gbps/ch, providing $r$5GB/s per channel.
• Process: TSMC 28 nm, $r$6 GHz, $r$7 mm², $r$8 mW.

The dataflow consists of preloading $r$9, running BESF+LATS+BAP to select $\Delta A_r(i, j) = Q_i \cdot K_j^r$0 sparse indices $\Delta A_r(i, j) = Q_i \cdot K_j^r$1, then applying softmax and value aggregation.

Total overhead versus dense bit-serial engines is marginal ($\Delta A_r(i, j) = Q_i \cdot K_j^r$25–7% area, 5–7% power), yet with complete removal of external predictor datapath and major reduction in off-chip Key traffic.

6. Performance Metrics and Comparative Evaluation

Evaluation on Wikitext-2 and Dolly tasks demonstrates:

Accelerator	Speedup over Sanger	Speedup over SOFA	DRAM Power Fraction	Energy Efficiency over Sanger/SOFA
Sanger	1.0×	1.1×	67%	1.0× / 1.1×
SOFA	1.08×	1.0×	62%	1.1× / 1.0×
BitStopper	2.03×	1.89×	38%	2.4× / 2.1×

BitStopper achieves 2.03× speedup and 2.4× energy efficiency over Sanger, and 1.89×/2.1×, respectively, over SOFA. Total compute is reduced by 75%, DRAM fetches by 56% (2.1–2.9× fewer accesses). The contribution of each co-design is cumulative: 1.25× speedup for BESF, 1.63× with BAP, 2.03× with LATS/BESF/BAP combined (Wang et al., 6 Dec 2025).

7. Limitations and Future Work

BitStopper is currently demonstrated with post-training INT12 quantization. Extensions to mixed precision/training-aware quantization remain unexplored. The radius and $\Delta A_r(i, j) = Q_i \cdot K_j^r$3 parameters controlling the sparsity/adaptation trade-off may benefit from automated or layer-wise tuning. The algorithm is applied to self-attention only; cross-attention and multi-head synchronization present open challenges. Scoreboard sizing constrains the active Key set, potentially limiting very high-dimensional or large-head settings. Integrating structured sparsity or low-rank approximations into the compact bit-serial architecture is also a prospective direction (Wang et al., 6 Dec 2025).

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8. BitStopper as a Silicon Photonic Optical Pulse Buffer

Independently, BitStopper denotes an optical-pulse buffering device based on concatenated Bragg gratings with a controlled defect, designed for ultrashort pulse trapping and slow light (Fu et al., 2013).

The architecture comprises:

• A linearly chirped Bragg grating (BG) segment
• A uniform-period BG segment
• A localized defect at the junction

The optical field in the waveguide is described by coupled-mode equations including Kerr nonlinear effects: $\Delta A_r(i, j) = Q_i \cdot K_j^r$4

$\Delta A_r(i, j) = Q_i \cdot K_j^r$5

where $\Delta A_r(i, j) = Q_i \cdot K_j^r$6, $\Delta A_r(i, j) = Q_i \cdot K_j^r$7 are forward and backward envelopes; $\Delta A_r(i, j) = Q_i \cdot K_j^r$8 is local detuning; $\Delta A_r(i, j) = Q_i \cdot K_j^r$9 is the coupling, and $$A_r(i, j) = A_{r-1}(i, j) + \Delta A_r(i, j) \, ,\, A_{-1} = 0$$0 the effective Kerr coefficient.

The chirped grating introduces spatially varying detuning, slowing pulses as they approach the defect, where the group velocity is minimized. The defect introduces a narrow potential well, enabling robust trapping of Bragg solitons. The device is capable of bit rates $$A_r(i, j) = A_{r-1}(i, j) + \Delta A_r(i, j) \, ,\, A_{-1} = 0$$1–$$A_r(i, j) = A_{r-1}(i, j) + \Delta A_r(i, j) \, ,\, A_{-1} = 0$$2 Gbit/s, buffer depth $$A_r(i, j) = A_{r-1}(i, j) + \Delta A_r(i, j) \, ,\, A_{-1} = 0$$3–$$A_r(i, j) = A_{r-1}(i, j) + \Delta A_r(i, j) \, ,\, A_{-1} = 0$$4 bits (for $$A_r(i, j) = A_{r-1}(i, j) + \Delta A_r(i, j) \, ,\, A_{-1} = 0$$5–$$A_r(i, j) = A_{r-1}(i, j) + \Delta A_r(i, j) \, ,\, A_{-1} = 0$$6 ns), and slowdown factors $$A_r(i, j) = A_{r-1}(i, j) + \Delta A_r(i, j) \, ,\, A_{-1} = 0$$7–$$A_r(i, j) = A_{r-1}(i, j) + \Delta A_r(i, j) \, ,\, A_{-1} = 0$$8. The scheme is CMOS-compatible and tolerant to ±15–20% input power fluctuations (Fu et al., 2013).

Practical implementations rely on silicon-on-insulator platforms, with e-beam lithography and precisely engineered corrugations for chirped and uniform BG segments and the defect. The release mechanism involves thermal or electro-optic tuning of the defect region.

9. Summary

BitStopper, in both digital transformer acceleration and optical ultrafast buffering, denotes a set of architectural innovations that increase efficiency and performance in their respective domains. In transformer hardware, BitStopper’s fusion of bit-serial computation, dynamic adaptive sparsity, and decoupled memory-execution enables scaling with measurable speedup and energy efficiency over established baselines, without external predictors. In integrated photonics, BitStopper achieves robust, high-capacity, CMOS-compatible data buffering for ultrafast pulse streams via slow-light trapping in engineered Bragg grating structures. Both implementations reflect domain-specific optimization of bitwise dataflow and adaptive resource allocation (Wang et al., 6 Dec 2025, Fu et al., 2013).