Energon Co-Processor & Filtering Unit

• Energon Co-Processor and FU are hardware systems that implement mix-precision multi-round filtering to prune unimportant query-key pairs early, reducing computational load.
• The approach employs low-bitwidth quantized dot-products and mean-threshold pruning to achieve up to 8× speedup with less than 1% accuracy loss.
• Specialized modules like the Filtering Unit and Attention Unit optimize transformer workloads, reducing DRAM traffic and energy consumption on resource-constrained platforms.

The Energon Co-Processor and Filtering Unit (FU) are hardware components tailored for the Energon dynamic sparse attention accelerator, which targets the efficient execution of transformer models by leveraging mix-precision algorithmic pruning of attention operations. The Filtering Unit executes the Mix-Precision Multi-Round Filtering (MP-MRF) algorithm, enabling early elimination of unimportant query-key pairs and thereby reducing computational costs, memory traffic, and energy consumption with negligible accuracy loss. These components are key enablers of both algorithmic speedup and hardware efficiency for transformer workloads on resource-constrained platforms (Zhou et al., 2021).

1. Motivation and Problem Statement

Transformer models rely on attention mechanisms, whose quadratic complexity in sequence length $n$ and head-dimension $d$ makes them computationally prohibitive for large $n$ (e.g., $n≥512$). Baseline dot-product attention requires computing $A = Q·K^T$ at $O(n^2 d)$ cost, representing a dominant source of latency and memory bandwidth demands. Previous approaches such as naïve top-$k$ pruning require full $QK^T$ computation and sorting, achieving only modest savings by pruning the softmax·$V$ stage, and require costly top-$k$ hardware engines. The Energon approach aims to:

1. Reduce the number of $d$0 dot-products via early algorithmic pruning.
2. Eschew expensive sorting in favor of simple thresholding.
3. Exploit low-bitwidth operations for initial filtering rounds but retain high-precision accuracy at the final attention stage.
4. Achieve hardware-friendly implementation by ensuring pipelinability, bit-sliced data paths, and buffer efficiency, with compute and off-chip traffic reductions of up to $d$1–$d$2 and less than $d$3 accuracy loss without retraining.

2. Mix-Precision Multi-Round Filtering Algorithm

The MP-MRF algorithm is central to Energon’s architecture. It processes attention queries in $d$4 filtering rounds (default $d$5), applying progressive, low-bitwidth quantized dot-products and mean-threshold pruning to identify likely-important query-key pairs.

Given input $d$6, the algorithm proceeds by:

1. Quantizing $d$7 to INT16, storing most/least significant bits (MSBs/LSBs) separately.
2. For each query index $d$8:
   • Initialize candidate key indices $d$9
   • For each filtering round $n$0:
     • Truncate $n$1 and $n$2 to $n$3 bits (e.g., $n$4, $n$5)
     • Compute approximate scores $n$6 using INT2 or INT4 operations
     • Compute mean-max hybrid threshold $n$7 as:

   $n$8

   where $n$9, $n≥512$0, and $n≥512$1 are maximum, minimum, and mean of $n≥512$2. - Prune $n≥512$3 - Final sparse attention: - Load full-precision entries, compute $n≥512$4, apply softmax, and compute $n≥512$5.

Each filtering round typically reduces the candidate set by ~50%. For sparsity parameter $n≥512$6 (e.g., $n≥512$7), the costliest full-precision attention applies only to a fraction of possible pairs.

3. Mathematical and Computational Properties

The MP-MRF algorithm’s main computational steps and associated complexity:

• Score functions in round $n≥512$8: $n≥512$9
• Pruning via threshold $A = Q·K^T$0 controls the pruning ratio, which can be swept across $A = Q·K^T$1 by varying $A = Q·K^T$2.
• Complexity reduction:
  • Base: $A = Q·K^T$3
  • Round 0 (low-precision): $A = Q·K^T$4 (INT2; $A = Q·K^T$5)
  • Round 1 (smaller candidate set): $A = Q·K^T$6
  • Final high-precision attention: $A = Q·K^T$7
  • Aggregate: total cost $A = Q·K^T$8, empirically $A = Q·K^T$9–$O(n^2 d)$0, corresponding to $O(n^2 d)$1–$O(n^2 d)$2 savings.

Empirical error and accuracy characterization:

• On BERT-base/SQuAD ($O(n^2 d)$3): $O(n^2 d)$4 key pruning, F1 loss $O(n^2 d)$5
• On GPT-2/Wikitext2 ($O(n^2 d)$6): $O(n^2 d)$7 pruning, perplexity degradation $O(n^2 d)$8
• On ViT-B/16 ($O(n^2 d)$9): $k$0 pruning, accuracy change $k$1
• Top-$k$2 coverage remains $k$3 after filtering.

The choice of $k$4-bit first round and $k$5-bit second round (the "2–4 schedule") provides an optimal tradeoff between hardware cost and accuracy. Inferior coverage arises from insufficient (e.g., $k$6–$k$7 bit) quantization; additional rounds (e.g., $k$8–$k$9–$QK^T$0 bit) yield diminishing returns.

4. Energon Co-Processor and Filtering Unit Architecture

The Energon Co-Processor incorporates several specialized hardware modules:

• Filtering Unit (FU): Implements a mix-precision Inner-Product Unit (IPU) using result-reusable processing elements (PEs). Each PE supports $QK^T$1-bit $QK^T$2 $QK^T$3-bit operations, computing MSB×MSB dot-products and buffering intermediate results for shift-and-add recombination with LSB×LSB products in subsequent rounds. This bit-sliced approach enables high throughput with minimal area and energy overhead.
• Selector: On-the-fly computes min, max, and mean dot-product statistics for threshold estimation, and compares all candidate scores in parallel to select surviving indices.
• Attention Unit (AU): Fetches pruned $QK^T$4 and $QK^T$5 entries on demand. It executes 16-bit multiply-accumulate (MAC) operations for the exact $QK^T$6, followed by a pipelined softmax (utilizing Taylor expansion) and weighted value aggregation.
• Buffering and DRAM Bandwidth Optimizations: Double buffering hides memory latency for $QK^T$7 registers. On-demand fetching (ODF) further reduces off-chip memory transfer, with up to $QK^T$8 reduction when sparsity $QK^T$9.

Pipelined dataflow at both head and query levels ensures that, while the AU processes the current query $V$0, the FU can process the subsequent $V$1, maximizing throughput.

5. Performance and Empirical Evaluation

Comprehensive experiments on language and vision benchmarks validate the performance of Energon’s co-processor and FU:

Model/Task	Key Pruning ($V$2)	Speedup ($V$3)	Accuracy Impact ($V$4)
BERT/SQuAD	11.5	7.8	F1 $V$5
GPT-2/Wikitext2	9.25	6.5	$V$6PPL $V$7
ViT-B/16/CIFAR-100	4.8	3.9	$V$8Acc $V$9

Comparison with other hardware platforms:

• Attention throughput gain: $k$0–$k$1 over TX2 GPU, $k$2–$k$3 over ARM-A72 CPU.
• Energy savings: $k$4 vs CPU, $k$5–$k$6 vs TX2 GPU.
• MP-MRF contributes $k$7 speedup; ODF adds $k$8 speedup.

Relative to state-of-the-art accelerators:

• Compared to SpAtten: equivalent sparsity with $k$9–$d$00 higher accuracy, $d$01 higher throughput.
• Compared to $d$02: $d$03 DRAM access reduction, $d$04 lower energy, similar or better accuracy (Zhou et al., 2021).

6. Trade-Offs, Limitations, and Integration

• Reducing bit-width in early filtering rounds lowers per-round hardware cost ($d$05), but excessive quantization (e.g., to $d$06 bit) degrades top-$d$07 coverage.
• Adding filtering rounds can improve selectivity but at higher latency; two rounds is empirically optimal.
• The ODF strategy trades minor architectural complexity for substantial reductions in off-chip bandwidth and energy; buffer organization is critical.
• The system is designed for seamless integration into transformer pipelines without retraining.
• A plausible implication is that further hardware-algorithm co-optimization could enable even higher sparsity with minimal loss, though empirical coverage and accuracy suggest diminishing returns beyond the current configuration.

7. Significance and Broader Context

The Energon Co-Processor and Filtering Unit represent a hardware realization of mix-precision, mean-threshold-pruned dynamic sparse attention for accelerators targeting transformer workloads. The integration of MP-MRF filtering with energy-efficient hardware achieves order-of-magnitude improvements in speed and energy compared to CPUs, GPUs, and existing attention accelerators, while preserving model accuracy and coverage of important query-key pairs. These innovations illustrate the effectiveness of hardware-algorithm co-design for scaling transformers to longer sequences and enabling deployment on resource-limited edge platforms (Zhou et al., 2021).