Dual-Rail Encoded Erasure Qubits

• Dual-rail encoded erasure qubits are quantum memories that encode a logical qubit in the single-excitation subspace of two modes to convert amplitude-damping errors into detectable erasures.
• They leverage engineered Hamiltonians and ancilla-assisted protocols to flag leakage events, enabling reliable gate operations and higher error correction thresholds.
• Experimental realizations in superconducting transmons and high-Q cavities demonstrate scalable, fault-tolerant operations with significant bias toward erasure errors and reduced resource overheads.

A dual-rail encoded erasure qubit is a hardware-embedded quantum memory in which the logical qubit is encoded in the single-excitation subspace of two distinct quantum modes, typically implemented as either superconducting transmons or high-Q microwave cavities. This architecture is engineered such that the dominant amplitude-damping (energy-relaxation, T₁) errors transform into detectable population leakage outside the logical subspace, i.e., erasures, rather than logical bit- or phase-flip errors. The ability to reliably flag and localize such erasure events at the physical level fundamentally alters the logical error model and enables quantum error correcting codes to achieve higher thresholds and lower resource overheads compared to standard Pauli-noise-limited hardware. Modern experimental realizations demonstrate order-of-magnitude bias in favor of erasure errors and offer scalable routes toward fault-tolerant quantum computation under realistic noise and hardware constraints.

1. Dual-Rail Encoding: Logical Structure, Error Conversion, and Hamiltonians

Dual-rail encoding maps a logical qubit basis to pairs of physical quantum modes as follows:

• $|0_L\rangle \equiv |1,0\rangle_{A,B}$
• $|1_L\rangle \equiv |0,1\rangle_{A,B}$

where $|1,0\rangle_{A,B}$ ($|0,1\rangle_{A,B}$) denotes one excitation (e.g., photon or transmon excitation) in mode A (B), while all other Fock states (e.g., $|0,0\rangle$, $|1,1\rangle$) lie outside the computational subspace and are classified as erasures. Physical amplitude damping events on either rail (relaxation $|1\rangle \to |0\rangle$) result in transitions from the code space into the leakage (erasure) space, which can be detected by appropriately engineered measurement protocols (Wills et al., 18 Jun 2025, Levine et al., 2023, Violaris et al., 5 Jan 2026).

The effective Hamiltonians in various implementations are constructed to preserve total excitation number and enable universal logic gates within the code space. In transmon-based realizations, the basic Hamiltonian takes the form:

$$H = \sum_{i} [\omega_{i} a_i^\dagger a_i - \frac{1}{2}\alpha_i a_i^\dagger a_i (a_i^\dagger a_i - 1)] - \eta a_A^\dagger a_A a_B^\dagger a_B$$

where $a_i$ are annihilation operators for mode $i$, $\omega_i$ is the frequency, $\alpha_i$ is the anharmonicity, and $\eta$ the cross-Kerr coupling (Wills et al., 18 Jun 2025). For coupled transmons, the logical subspace lives within the symmetric/antisymmetric single-excitation manifold of two transmons coupled by a swap interaction (Levine et al., 2023, Huang et al., 16 Apr 2025). In cavity-based schemes, the logical subspace consists of single-photon excitations delocalized across two high-Q resonators (Koottandavida et al., 2023, Teoh et al., 2022).

The logical Pauli operators $X_L$, $Z_L$ are typically constructed as:

• $$X_L = |0_L\rangle\langle1_L| + |1_L\rangle\langle0_L|$$
• $$Z_L = |0_L\rangle\langle0_L| - |1_L\rangle\langle1_L|$$

Single-qubit and two-qubit logic operations preserve total excitation and ensure that relaxation faults manifest as detected erasures rather than logical errors.

2. Physical Implementations and Erasure Detection Mechanisms

Table: Implementation Modalities and Erasure Detection

Platform Type	Logical Basis	Erasure Detection Mechanism
Resonantly coupled transmons	Single excitation subspace	Ancilla-dispersive readout or conditional π-pulse (Levine et al., 2023, Huang et al., 16 Apr 2025)
Multimode superconducting "dimon"	Dipole/quadrupole transmon modes	Readout discriminates
Dual high-Q microwave cavities	Single photon in either cavity	Photon-number parity, QND Ramsey on ancilla (Koottandavida et al., 2023, Teoh et al., 2022)
Frequency-bin photonic qubits	Single photon in frequency pair	Heterodyne detection, photon occupancy (Wang et al., 14 Aug 2025)

In transmon-based dual-rail qubits, a pair (or pair + ancilla) of frequency-tunable transmons defines a single logical qubit. The most common detection scheme couples an ancilla transmon dispersively to both rails, and a conditional microwave π-pulse selectively flips the ancilla if both rails are in their ground state (the erasure state). Ancilla readout then signals an erasure to hardware control logic or the decoder (Levine et al., 2023, Huang et al., 16 Apr 2025).

In cavity-based architectures, dual-rail encoding is realized in two orthogonal (spatial or frequency) principal modes of a 3D cavity or two separate cavities. Erasure detection is typically implemented via QND photon-number measurements using Ramsey-like sequences on a dispersively coupled transmon. Detection of zero or two photons flags a leakage event, while exactly one photon corresponds to the logical code space (Koottandavida et al., 2023, Teoh et al., 2022, Graaf et al., 2024).

Photonic implementations in the frequency or time domain encode dual-rail qubits as single photons delocalized across two frequency bins. Erasure detection is accomplished via photon occupancy monitoring using high-efficiency heterodyne receivers (Wang et al., 14 Aug 2025).

Mid-circuit erasure detection protocols enable real-time flagging of leakage events with missed-erasure probabilities well below $10^{-3}$ and control-induced dephasing below $10^{-3}$ per check (Levine et al., 2023, Graaf et al., 2024), enabling robust integration with QEC cycles.

3. Noise Hierarchy, Error Bias, and Logical Error Rates

The defining characteristic of dual-rail encoded erasure qubits is a fundamental bias in physical error channels:

• Amplitude-damping errors (T₁ processes) manifest predominantly as transitions out of the code subspace, flagged as erasures.
• Residual in-subspace errors after erasure conversion are overwhelmingly phase errors (dephasing), with bit-flip errors suppressed by at least an order of magnitude (Koottandavida et al., 2023, Chou et al., 2023).
• The error rates hierarchy is quantified as $$p_{\mathrm{erasure}} \gg p_{\mathrm{phase}} \gg p_{\mathrm{bit-flip}}$$, with experimental ratios of $0.2\% : 0.03\% : 0.00003\%$ per μs for erasure, dephasing, and bit-flip respectively in state-of-the-art cavity systems (Chou et al., 2023).

Logical step error rates show order-of-magnitude suppression compared to physical qubits:

• For multimode dimon devices: $T_1^L\approx 3.1$ ms, $T_{2E}^L\approx 0.76$ ms (logical), compared to $T_1^{\text{phys}}\approx 0.07$ ms (Wills et al., 18 Jun 2025).
• Tunable-transmon dual-rails report $T_1^{\mathrm{DR}} = 906\,\mu$s, $T_2^{\mathrm{DR,echo}} = 0.85$–$1.25$ ms, with a noise bias $T_2^{\mathrm{DR}}/T_{\mathrm{eras}}\gtrsim 20$ (Levine et al., 2023, Huang et al., 16 Apr 2025).
• Per-gate erasure rates are routinely $0.5\%$ (two-qubit gates), with residual Pauli error $<0.1\%$, bit-flip errors bounded in the few parts per million (Mehta et al., 13 Mar 2025).

This separation admits fault-tolerant operation at physical error rates an order of magnitude higher than would be permissible with standard depolarizing noise.

4. Fault-Tolerant Quantum Error Correction with Erasure Qubits

Dual-rail erasure qubits enable a two-layer QEC architecture:

1. Inner code: The physical dual-rail encoding converts dominant T₁ (amplitude damping) errors into erasures, which are hardware-flagged and localized.
2. Outer code: A surface code, LDPC code, or other stabilizer code operates on a lattice of these erasure qubits. The decoder is supplied both stabilizer syndrome bits and time-tagged erasure flags, allowing it to trivially identify the location and timing of faults (Violaris et al., 5 Jan 2026, Chang et al., 2024).

Thresholds for QEC codes increase dramatically in the erasure-dominated regime:

• Surface-code erasure thresholds approach ~5% per operation under ideal detection ($p_\mathrm{th}^\mathrm{erasure}\approx5\%$), compared with $\sim1\%$ for depolarizing noise (Chang et al., 2024, Violaris et al., 5 Jan 2026).
• Circuit-level and experimental studies with erasure-dominated noise and realistic erasure-detection fidelity ($\geq97\%$) maintain thresholds well above 4% and effective code distances that double those for Pauli noise (Chang et al., 2024, Chadwick et al., 30 Apr 2025).

Logical error rates scale as $p_L \sim (e/e^*)^d$, with $e^*$ the erasure threshold and $d$ the code distance, a much steeper suppression than the $p_L \sim (p/p^*)^{(d+1)/2}$ scaling characteristic of surface codes under generic Pauli noise (Gu et al., 2024, Violaris et al., 5 Jan 2026).

Hybrid surface code architectures employing both standard and dual-rail erasure qubits (with erasure fraction $f_e\sim0.5$–0.6 for moderate budgets) can outperform homogeneous designs in terms of logical error rate per hardware cost (Chadwick et al., 30 Apr 2025).

5. Control, Gate Design, and Error-Reshaping

Universal logic operations within the dual-rail encoding are realized via excitation-preserving gates:

• Single-qubit: Parametric beamsplitter interactions or swap modulations implement arbitrary logical Bloch rotations, e.g., logical $X$ or Hadamard gates with gate times $\sim50$–$100$ ns and post-selected gate infidelity $<2\times10^{-4}$ (Teoh et al., 2022, Levine et al., 2023).
• Two-qubit: Logic gates such as CZ or $\sqrt{\mathrm{iSWAP}}$ are synthesized using photon-number-conserving Hamiltonians involving tunable couplers or beamsplitter plus dispersive interactions. Modern implementations achieve two-qubit gate erasure rates of $0.5\%$, residual infidelity $0.03$–$0.1\%$, and maintain the error-bias hierarchy (Mehta et al., 13 Mar 2025, Huang et al., 16 Apr 2025).

Ancilla-induced error channels in erasure detection and gates can be actively reshaped to maintain the desired erasure bias. Dynamically corrected pulse shaping (e.g., Magnus expansion constraints on pulse envelopes) reduces undetected error probabilities in erasure checks from $10^{-2}$ to $10^{-4}$, and decreases logical two-qubit gate infidelities by up to three orders of magnitude (Dakis et al., 9 Oct 2025). Such techniques ensure that measurement and control hardware errors are also rapidly pushed into the erasure channel.

Fault tolerance is further enhanced by judicious scheduling of mid-circuit erasure checks and encoder reset operations, balancing added cycle time against syndrome information for optimal logical performance (Mehta et al., 13 Mar 2025, Gu et al., 2024).

6. Experimental Results and Resource Efficiency

Recent laboratory demonstrations confirm the principal advantages of dual-rail erasure qubits:

• Multi-qubit entanglement: Bell ($98.8\%$) and three-rail GHZ ($93.9\%$) states are generated with high fidelity in fully protected erasure codes, with logical CNOT process fidelities of $96.2\%$, all with order-of-magnitude longer coherence than uncoupled transmons (Huang et al., 16 Apr 2025).
• Photon-loss erasure rates: Cavity-based implementations achieve erasure rates compatible with fault-tolerant thresholds ($\sim4\,\mathrm{ms}^{-1}$) with dephasing errors an order of magnitude lower (Koottandavida et al., 2023, Chou et al., 2023).
• Cluster states: Frequency-bin-encoded photonic dual-rail qubits yield cluster states with $>50\%$ fidelity for up to 8 logical qubits post-erasure-filtering, and localizable entanglement across up to 11 physical qubits—demonstrating robust high-dimensional entanglement in a loss-resilient encoding (Wang et al., 14 Aug 2025).

Scalability is facilitated by low hardware overhead per logical qubit—two rails (plus, optionally, a single ancilla per logical qubit or per readout row), reuse of existing readout infrastructure, compatibility with 2D lattice layouts, and tunable operation windows that minimize frequency-collision hazards in large arrays. For moderate code distances and transmon budgets, hybrid surface code layouts with $0.5<f_e<0.7$ dual-rail erasure qubit fraction offer optimal trade-offs between performance and resource consumption (Chadwick et al., 30 Apr 2025).

7. Challenges, Open Problems, and Future Directions

Despite rapid recent progress, challenges remain. Open questions include:

• Optimization of mid-circuit erasure check frequency and placement, balancing additional error sources from measurement with logical performance gains (Violaris et al., 5 Jan 2026, Dakis et al., 9 Oct 2025).
• Reducing false-positive erasure flags and misclassification due to ancilla errors, especially under increased device complexity and interconnectivity (Levine et al., 2023, Graaf et al., 2024).
• Development of decoding algorithms, resource estimation frameworks, and software toolchains capable of efficiently incorporating erasure-flagged error channels and hybrid noise models (Violaris et al., 5 Jan 2026).
• Further exploration of inner codes based on three- or four-mode encodings to enhance error bias and mitigate non-erasable error channels (Violaris et al., 5 Jan 2026).
• Scaling up to high-fidelity multi-qubit entanglement and logic operations with preserved erasure bias across large register sizes (Huang et al., 16 Apr 2025).

Near-term uses include post-selection for extended qubit coherence, ancilla error mitigation, and erasure-bias exploitation in magic-state factories (Violaris et al., 5 Jan 2026). With mid-circuit erasure detection fidelities exceeding $95$–$99\%$ and logical error suppression factors of $10$–$100\times$, dual-rail encoded erasure qubits are positioned as a leading path toward hardware-efficient, early fault-tolerant superconducting quantum processors (Violaris et al., 5 Jan 2026, Levine et al., 2023, Huang et al., 16 Apr 2025, Teoh et al., 2022, Mehta et al., 13 Mar 2025).