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Real-time decoder for a MegaQuOp quantum computer using a single CPU

Published 25 Aug 2026 in quant-ph | (2608.25027v1)

Abstract: As quantum computers advance toward the regime of MegaQuOp machines executing millions of gates, a decoding system capable of real-time error correction in such a device will be crucial. Recent efforts have been focused on decoding an error-corrected memory or a small number of logical operations. Here we demonstrate an end-to-end real-time decoding stack for a universal fault-tolerant trapped-ion quantum computer architecture capable of decoding real workloads with millions of logical gates over hundreds of logical qubits. The complete pipeline, including on the fly detector error model generation, decoding of all logical qubits, logical operations, and magic-state factories, runs on a single CPU. We benchmark the decoder on practically relevant quantum applications spanning up to 408 logical qubits, and up to one million TT gates. Assuming a trapped-ion architecture with 1 to 5 ms cycle time, the decoding delay stretches the computation by less than 0.3%0.3\% at pCNOT=10<sup>−4p_{\mathrm{CNOT}}=10<sup>{-4} and less than 12%12\% at pCNOT=5×10<sup>−4p_{\mathrm{CNOT}}=5\times 10<sup>{-4} for all workloads studied. These results demonstrate real-time decoding at MegaQuOp scale on a single conventional CPU.

Summary

  • The paper demonstrates real-time decoding for a universal trapped-ion architecture with up to 408 logical qubits using a single 12-core CPU without specialized hardware.
  • Dual sliding-window decoding and fixed-topology detector error models allow the decoder to maintain computations while processing logical measurements.
  • Memory and concurrency optimizations reduce the decoder's memory footprint, enabling concurrent processing of multiple blocks.

Problem formulation and principal claim

Real-time decoding is a systems constraint on fault-tolerant quantum computation, not merely a question of decoder throughput in isolation. A decoder must process syndrome data faster than the quantum processor generates it, while also returning logical measurement outcomes soon enough to control measurement-conditioned operations. If it falls behind, the resulting backlog inserts additional error-correction cycles into the computation and can substantially increase execution time.

"Real-time decoder for a MegaQuOp quantum computer using a single CPU" addresses this problem for a universal trapped-ion architecture based on the walking-cat architecture (WCA). The paper evaluates a complete decoding stack rather than a memory-only decoder or an isolated logical operation. The stack includes on-the-fly detector error model (DEM) generation, continuous decoding of all memory blocks, decoding of logical measurements, and processing of magic-state factories. Its central claim is that this workload can be decoded on a single conventional CPU for circuits containing hundreds of logical qubits and millions of logical operations (2608.25027).

The reported workloads contain between 102 and 408 logical qubits, up to 1,087,434 TT gates, up to 1,318,310 logical measurements, and as many as 31,548,792 syndrome-extraction cycles (SECs) summed over all code blocks. At pCNOT=10−4p_{\mathrm{CNOT}}=10^{-4}, the decoding-induced stretch is below 0.3%0.3\% for every benchmark. At pCNOT=5×10−4p_{\mathrm{CNOT}}=5\times 10^{-4}, it remains below 12%12\%. These figures are obtained using 12 cores of a 2024 Apple M4 Max CPU, with eight cores allocated to error decoding and four to outcome decoding. The result is consequential within the paper's assumptions: the classical decoding pipeline does not require dedicated FPGA, GPU, TPU, or ASIC hardware for the evaluated WCA workloads.

Architectural basis: walking-cat execution

The feasibility result depends strongly on the structure of the WCA rather than being architecture-independent. WCA logical computation is organized around state preparation, Clifford-frame tracking, and logical Pauli measurements. Accessible Clifford operations are implemented in software and therefore do not require physical transformations of encoded blocks. Other operations, including non-Clifford operations, are implemented through measurement-based procedures using cat states and magic-state factories.

This organization avoids lattice surgery, block merging, code deformation, and changes to the syndrome-extraction circuit. Each memory block instead emits a regular syndrome stream comprising ordinary SECs, with cat-state measurements inserted at known locations. A cat SEC consists of a cat measurement followed by an SEC. Memory blocks decode repeated cat measurements using an adaptive Viterbi procedure, while magic-state factories use error-detected measurement (EDM), accepting an outcome only when the relevant cat-state readouts agree.

The architectural consequence is that logical computation appears to the decoder as a sparse overlay on a memory-decoding problem. The syndrome stream remains temporally regular, and the code blocks remain structurally unchanged. This is the principal reason the authors can use a fixed decoding topology at MegaQuOp scale. The paper therefore establishes a conditional systems result: real-time decoding is tractable for a universal workload compiled to an architecture whose logical operations preserve a static qLDPC memory structure.

Dual sliding-window decoding

The decoder separates continuous Pauli-frame maintenance from low-latency logical-measurement outcome determination. The error decoder processes every SEC using a five-SEC sliding window with a three-SEC commit region. It operates continuously over ordinary and cat SECs and produces the Pauli-frame corrections required by the computation.

The outcome decoder is instantiated only when a logical measurement begins. It is initialized using the Pauli frame committed by the error decoder up to the measurement's starting SEC, and then processes the cat-state readouts using a two-SEC window with a one-SEC commit region. This shorter window is deliberately less conservative and is optimized for latency rather than for the strongest possible suppression of correctable decoding errors.

The distinction is technically justified by the different error budgets. Some physical error mechanisms produce identical syndrome patterns while differing in whether they flip the cat-measurement outcome. These mechanisms are indistinguishable from syndrome data alone and impose an intrinsic readout-error floor. Consequently, improving the outcome decoder beyond the point at which its correctable contribution is approximately one tenth of the intrinsic contribution has little practical value. The error decoder has a stricter requirement: its correctable contribution is reduced to approximately one thousandth of the intrinsic error rate because Pauli-frame errors accumulate over the full computation.

This allocation of accuracy explains why the outcome decoder can be substantially faster without materially degrading logical measurement reliability. It also identifies the critical path precisely. Error-decoder backlog delays the start of cat measurements, whereas outcome-decoder latency can delay the termination of a Viterbi measurement or the accept/reject decision of an EDM. Both effects increase the number of executed SECs, but through different mechanisms.

On-the-fly DEM generation with a fixed Tanner graph

A major implementation contribution is the elimination of per-window Tanner-graph reconstruction. A DEM specifies both the detector-incidence structure and the prior probabilities of the corresponding error mechanisms. Cat measurements appear to create a different DEM for each logical Pauli operator, since they couple the cat state to different data-qubit representatives.

The paper observes that every error mechanism introduced by a cat measurement has a counterpart in the accompanying SEC with the same detector signature. Hence, the two mechanisms correspond to identical columns of the parity-check matrix and can be merged into one error variable. If their independent probabilities are p1p_1 and p2p_2, the effective prior is updated to

pcombined=p1(1−p2)+p2(1−p1).p_{\mathrm{combined}}=p_1(1-p_2)+p_2(1-p_1).

Only the prior vector changes when a cat SEC enters or leaves a decoding window; the Tanner graph and message-passing topology remain fixed. DEM generation is therefore reduced to lightweight prior updates performed concurrently with decoding.

This construction is more than an optimization of data movement. It makes online DEM generation compatible with concurrent execution across many blocks. A decoder designed for architectures requiring graph reconstruction after each logical operation could have a fundamentally different scaling behavior. The paper's result relies on the WCA's specific equivalence between cat-measurement and SEC detector signatures, and therefore should not be generalized to arbitrary qLDPC logical-operation schemes.

Memory and concurrency optimizations

The underlying beam-search decoder retains multiple candidate decoding trajectories, each associated with belief-propagation state. In the original implementation, every candidate stores a complete copy of the Tanner-graph edge messages. Because the number of edges is substantially larger than the number of error nodes, this representation produces high memory consumption and memory traffic when many decoder instances execute concurrently.

The authors replace the stored edge-message state with one posterior log-likelihood ratio (LLR) per error node. For an error node with posterior LLR λ\lambda, prior LLR λ0\lambda_0, and degree pCNOT=10−4p_{\mathrm{CNOT}}=10^{-4}0, the incoming check-to-variable messages are approximated by their average, pCNOT=10−4p_{\mathrm{CNOT}}=10^{-4}1. The outgoing variable-to-check state is then reconstructed from these node-level quantities. This reduces the state retained per beam candidate by approximately the average Tanner-graph degree.

The reformulation was verified to produce a similar logical error rate to the original implementation. Alongside additional memory-layout and implementation-level optimizations, it reduces the decoder memory footprint by more than an order of magnitude. The practical implication is important for this experiment: the benchmark measures concurrent cache and memory-bandwidth contention across all 12 decoding processes, rather than timing a single isolated decoder instance. The paper thus attributes the single-CPU result partly to an algorithmic memory compression that is specifically valuable in multi-instance execution.

Benchmark workloads and experimental model

The evaluation uses three compiled fault-tolerant workloads.

Workload Logical qubits pCNOT=10−4p_{\mathrm{CNOT}}=10^{-4}2 gates Logical measurements WCA blocks SEC budget
MIPT 102 1,087,434 1,100,227 22 1 ms/SEC
Heisenberg n64 102 139,408 327,066 22 1 ms/SEC
Heisenberg n266 408 555,130 1,318,310 88 5 ms/SEC

The MIPT benchmark contains 40 brickwork layers of Haar-random two-qubit gates, with probabilistic pCNOT=10−4p_{\mathrm{CNOT}}=10^{-4}3 measurements at each layer. KAK decomposition and Ross–Selinger synthesis approximate the two-qubit gates with operator-norm error at most pCNOT=10−4p_{\mathrm{CNOT}}=10^{-4}4, requiring 488–580 pCNOT=10−4p_{\mathrm{CNOT}}=10^{-4}5 gates per compiled two-qubit gate, with mean 538. The Heisenberg circuits implement a sixth-order Trotter step on degree-seven random graphs and provide a size-controlled comparison between 64-site and 266-site instances.

The noise model is circuit-level and includes noise in both syndrome extraction and cat measurements. The authors use a 1 ms SEC duration for the 102-qubit workloads and 5 ms for the 408-qubit workload. These choices give the error decoder budgets of 3 ms and 15 ms per window, respectively, because its commit region is three SECs. The outcome decoder receives budgets of 1 ms and 5 ms per SEC.

The differing budgets are a significant qualification. The largest workload is not demonstrated at the 1 ms/SEC operating point; instead, its longer SEC duration compensates for the larger number of blocks assigned to each CPU core. Thus, the data establish real-time operation for 408 logical qubits under a 5 ms/SEC assumption, while the 1 ms/SEC result is demonstrated for 102 logical qubits.

Quantitative decoding performance

At pCNOT=10−4p_{\mathrm{CNOT}}=10^{-4}6, the measured total stretch is 0.24% for MIPT, 0.18% for Heisenberg n64, and 0.02% for Heisenberg n266. The larger n266 instance performs especially well because its 5 ms SEC budget provides substantially more decoding time per window despite the larger block count.

At pCNOT=10−4p_{\mathrm{CNOT}}=10^{-4}7, stretch increases to 11.53% for MIPT, 10.25% for Heisenberg n64, and 0.72% for Heisenberg n266. The gradual increase is associated with heavier-tailed decoding-time distributions. For MIPT, the mean error-decoder time rises from 0.99 ms at pCNOT=10−4p_{\mathrm{CNOT}}=10^{-4}8 to 1.89 ms at pCNOT=10−4p_{\mathrm{CNOT}}=10^{-4}9, while its 99.9th-percentile time rises from 3.32 ms to 13.68 ms. The fraction of error-decoder windows exceeding the 3 ms budget increases from 0.26% to 10.70%. Outcome-decoder mean latency increases more modestly, from 0.31 ms to 0.45 ms, but its 99.9th percentile increases from 1.35 ms to 4.05 ms.

The corresponding Heisenberg n64 statistics are similar: the error-decoder mean rises from 1.00 ms to 1.85 ms, and the 99.9th percentile from 3.38 ms to 11.62 ms. The outcome-decoder mean changes from 0.26 ms to 0.37 ms. These measurements show that stretch is driven primarily by tail latency and budget violations, not simply by average decoder throughput. A decoder whose mean runtime is below budget can still induce substantial schedule expansion if rare difficult windows create persistent backlogs.

For Heisenberg n266, the 5 ms/SEC budget yields much lower stretch across the noise sweep: 0.02%, 0.05%, 0.12%, 0.39%, and 0.72% at 0.3%0.3\%0, respectively. The error-decoder 99.9th-percentile latency reaches 41.86 ms at the highest noise rate, compared with a 15 ms budget, but only 0.50% of windows exceed that budget. This illustrates that occasional severe overruns do not necessarily translate linearly into total stretch: subsequent windows can drain the accumulated backlog.

The reported stretch-episode lengths also expose the burstiness of the effect. For MIPT at 0.3%0.3\%1, the mean episode length is 4.3 SECs and the 99.9th percentile is 105 SECs. Such episodes are operationally more relevant than average latency because they determine periods during which logical measurements may be frozen and additional SECs inserted globally.

Limitations and open questions

The evaluation is simulation-based and uses a single CPU model. It does not demonstrate integration with a physical trapped-ion control stack, real-time syndrome acquisition hardware, operating-system scheduling constraints, or network and I/O effects between the quantum processor and decoder. The CPU result is therefore an end-to-end software benchmark under a specified execution model, not a hardware-in-the-loop demonstration.

The architectural scope is also explicit. The fixed-Tanner-graph DEM method depends on the WCA's regular syndrome extraction and cat-measurement structure. It does not establish comparable performance for lattice surgery, code deformation, transversal logical gates, or other qLDPC architectures whose logical operations alter detector connectivity. The paper identifies CPU resources as scaling primarily with the number of code blocks assigned to each core, but does not provide a measured scaling study beyond 88 blocks or establish the required resources for larger machines.

The noise sweep reaches 0.3%0.3\%2, and the authors report rare convergence failures in sufficiently difficult windows. These failures are excluded from stretch because they require restarting the affected computation rather than merely inserting SECs. The paper states that they remain rare when total SEC volume is well below the inverse logical-error rate per SEC, but it does not quantify failure probabilities for each benchmark or incorporate restart overhead into the reported stretch. This distinction matters for million-operation workloads, where even low per-window failure probabilities can affect end-to-end completion probability.

Finally, the largest workload uses a 5 ms SEC duration, whereas the smaller workloads use 1 ms. The results consequently do not isolate the effect of increasing system size at a fixed physical cycle time. Whether the same single-CPU configuration remains adequate for 408 logical qubits at 1 ms/SEC remains open within the presented data.

Conclusion

The paper demonstrates a complete software decoding pipeline for WCA fault-tolerant workloads at MegaQuOp scale using 12 cores of a single Apple M4 Max CPU. Its main technical mechanisms are dual sliding-window decoding, fixed-topology DEMs with dynamically updated priors, and compressed beam-search state. For workloads spanning 102–408 logical qubits and millions of logical operations, decoding-induced stretch is below 0.3% at 0.3%0.3\%3 and below 12% at 0.3%0.3\%4 under the stated SEC budgets. The result supports the narrower but substantive conclusion that, for the WCA architecture and simulated workloads studied, conventional CPU decoding can keep pace with fault-tolerant execution without specialized decoder hardware.

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1. What is this paper about?

Quantum computers are very sensitive to errors. To make them reliable, they use quantum error correction. This means spreading information across many physical qubits and constantly checking for signs that something went wrong.

A computer program that examines these checks and figures out what errors happened is called a decoder. The decoder must work almost immediately. If it is too slow, the quantum computer has to wait, making the whole calculation longer.

This paper presents a decoder that can keep up with very large quantum-computing tasks using only one ordinary computer processor. The authors tested it on programs using up to:

  • 408 logical qubits — reliable qubits made from many physical qubits.
  • More than one million quantum operations.
  • More than 31 million error-checking cycles.

The paper’s main claim is that real-time error decoding does not necessarily require special hardware such as GPUs, FPGAs, or custom chips.

2. What questions were the researchers asking?

The researchers wanted to find out:

  1. Can one normal CPU decode errors quickly enough for a large, universal quantum computer?
  2. Can the decoder handle different kinds of quantum operations, including measurements and special operations called TT gates?
  3. Can the decoder update itself during a calculation when the quantum computer changes what it is doing?
  4. How much extra time does decoding add to a large quantum computation?
  5. Does the decoder still work when the physical qubits become noisier?

In simple terms, they were asking:

Can a regular computer watch a large quantum computer, correct its mistakes, and keep up without creating a growing waiting line?

3. How did they do the research?

Quantum error correction

The paper uses a type of error-correcting system called a quantum low-density parity-check code, or qLDPC code. A logical qubit is stored using many physical qubits.

The system repeatedly performs checks called syndrome-extraction cycles, or SECs. These checks do not directly reveal the stored quantum information. Instead, they provide clues about whether an error occurred.

This is similar to checking a long row of light bulbs using tests that tell you which parts might be broken, without turning the whole system off.

The walking-cat architecture

The quantum computer design used in the study is called the walking-cat architecture.

In this design:

  • Most ordinary operations can be tracked by software rather than physically changing the qubit layout.
  • Special measurements are performed using temporary groups of entangled qubits called cat states.
  • These measurements are repeated when necessary to make the result more trustworthy.
  • Special TT gates use prepared resources called magic states.

A magic-state factory is like a small workshop that continually prepares these special ingredients for the main computation.

Two decoders working together

The researchers created a dual-decoder system, meaning that two related decoders work at the same time.

The first is the error decoder. It runs continuously and keeps track of errors in the stored logical qubits. It uses a moving group of recent SECs, called a sliding window, instead of waiting until the entire computation is finished.

The second is the outcome decoder. It works only when the computer performs an important logical measurement. Its job is to quickly decide the measurement’s result, because later operations may depend on that result.

The two decoders have different goals:

  • The error decoder aims for very high accuracy.
  • The outcome decoder aims to produce an answer quickly, while keeping its errors acceptably low.

Detector error models

To decode the data, the system uses a detector error model, or DEM. A DEM is like a map showing how different possible mistakes would appear in the error-checking results.

Normally, changing the type of operation might require rebuilding this map. That would be slow. The researchers found that, in their architecture, the basic map can stay the same. Only the probabilities of certain errors need to be changed.

This is similar to using the same road map while updating traffic predictions instead of drawing a completely new map every time traffic conditions change.

The decoder uses a method called beam search. It considers several possible explanations for the observed errors and keeps the most promising ones.

For example, if several different repair plans could explain the clues, the decoder keeps a shortlist of the best plans rather than checking every possible plan. This saves time.

The researchers also changed how the decoder stores information. Instead of saving a large amount of data for every possible error explanation, they saved a smaller summary. This reduced memory use by more than ten times.

Test programs and computer

They tested three large quantum workloads:

Workload Logical qubits Important scale
Measurement-induced phase transition 102 Over 1 million TT gates
Heisenberg model, 64-site version 102 Hundreds of thousands of measurements
Heisenberg model, 266-site version 408 Over 1.3 million measurements

All tests ran on a single 2024 Apple M4 Max CPU. The researchers used 12 CPU cores: eight for the continuous error decoder and four for the faster outcome decoder.

They tested different physical error rates. The symbol pCNOTp_{\mathrm{CNOT}} represents the chance that a two-qubit CNOT operation has an error.

4. What did they find?

The main result was that one CPU could decode all the tested workloads in real time, or nearly in real time.

At a relatively low error rate of pCNOT=10−4p_{\mathrm{CNOT}} = 10^{-4}:

  • The extra time added by decoding was less than 0.3%.
  • For the largest 408-logical-qubit workload, the extra time was only about 0.02%.

This means that, under these conditions, decoding barely slowed down the quantum computation.

At a higher error rate of pCNOT=5×10−4p_{\mathrm{CNOT}} = 5\times10^{-4}:

  • The slowdowns were larger.
  • However, they stayed below about 12% for every tested workload.
  • For the largest workload, the slowdown was still below 1%.

The slowdown happens when decoding takes longer than the time available before the next batch of quantum data arrives. This creates a backlog, like a line of unfinished homework. If the decoder cannot catch up quickly, the quantum computer inserts extra error-checking cycles and waits.

The tests showed that:

  • The decoder usually finished within its time limit.
  • Occasional slow periods caused short delays.
  • The delays generally disappeared as the decoder caught up.
  • The system did not become a major bottleneck for the tested workloads.

The researchers also reported that very difficult decoding cases can sometimes fail to reach a solution and require the affected computation to restart. These failures were rare under the conditions studied.

5. Why are these results important?

Large quantum computers will need error correction all the time. It is not enough for the quantum hardware to perform operations quickly; a classical computer must also process the error information quickly enough.

This paper suggests that:

  • A large trapped-ion quantum computer might not need a large collection of specialized decoding chips.
  • Ordinary CPUs could handle the decoding for substantial workloads.
  • The decoder can process information as the computation happens, instead of waiting until the end.
  • The architecture’s simple design makes real-time decoding easier.
  • Larger systems could be supported by adding more regular CPU cores or additional CPUs.

Conclusion and possible impact

The paper shows a promising way to solve one of the biggest practical problems in quantum computing: keeping up with errors while a large calculation is running.

The researchers demonstrated this in computer simulations rather than on a complete working MegaQuOp quantum machine. Therefore, the results do not prove that every future quantum computer will work this way. Real hardware may have additional problems, such as communication delays, unexpected noise, or different processor limitations.

Still, the results are encouraging. They show that error correction for a quantum computer with hundreds of logical qubits and millions of operations might be manageable using ordinary computing hardware. If this approach continues to work as quantum computers grow, it could make large fault-tolerant quantum computers simpler, cheaper, and easier to build.

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Knowledge Gaps

The paper leaves the following knowledge gaps, limitations, and open questions unresolved:

  • No experimental hardware validation: The decoder is evaluated entirely through simulation; its behavior on a physical trapped-ion processor, including real syndrome-data acquisition, communication, timing jitter, and control-system integration, is not demonstrated.
  • Limited architecture generality: The approach is specifically tailored to the walking-cat architecture and its Q70/CH2 components. It is unclear whether the dual-decoder design or static-Tanner-graph DEM update applies to lattice surgery, code deformation, merging-based qLDPC architectures, or other fault-tolerant implementations.
  • Unverified assumptions about the noise model: The benchmarks use the circuit-level noise model from prior work, but do not assess robustness to correlated, non-Markovian, leakage, crosstalk, measurement, reset, motional, calibration-drift, or time-varying errors expected in real trapped-ion systems.
  • Unclear validity of the identical-signature DEM reduction under realistic noise: The combination of cat-measurement and SEC error mechanisms relies on identical detector signatures and independent error probabilities. The paper does not establish whether this equivalence remains valid for correlated errors or hardware-specific noise processes.
  • Narrow physical-error-rate range: Results are reported only for pCNOTp_{\mathrm{CNOT}} between 10−410^{-4} and 5×10−45\times10^{-4}. Decoder performance, logical failure rates, and computational feasibility outside this range—especially near threshold or at lower future hardware error rates—remain unknown.
  • Insufficient characterization of decoding correctness: The paper reports timing and stretch but does not provide comprehensive logical error rates, measurement-outcome error rates, Pauli-frame failure rates, or end-to-end algorithmic fidelity for the benchmark workloads.
  • Accuracy claims for the memory-state reformulation are underdocumented: The reduced-state belief-propagation initialization is said to produce a “similar” logical error rate, but no quantitative comparison, confidence intervals, workload dependence, or worst-case degradation is given.
  • Unresolved convergence-failure behavior: Rare beam-search convergence failures are acknowledged, but their measured frequency, dependence on circuit size and noise rate, restart cost, and impact on total computation reliability are not reported.
  • No formal reliability guarantee for million-operation computations: The statement that convergence failures remain rare when total SEC volume is below the inverse logical error rate is not developed into a quantitative end-to-end failure model or validated over repeated full-computation trials.
  • Limited workload diversity: Only one MIPT circuit and two related Heisenberg circuits are studied. The results may not generalize to algorithms with different measurement densities, entanglement patterns, factory utilization, branching structures, circuit depths, or logical-qubit layouts.
  • No stress test of highly adaptive computation: The benchmarks do not systematically evaluate workloads in which measurement outcomes frequently alter future operations, create many simultaneous decoder instances, or generate severe bursts of cat measurements.
  • Scalability beyond 408 logical qubits is extrapolated rather than demonstrated: The proposed provisioning rule is based on assigning blocks to CPU cores, but no benchmarks establish performance for thousands of logical qubits, larger numbers of factories, or multi-CPU systems.
  • Potential synchronization bottlenecks are not analyzed: All blocks are assumed to advance on a synchronized SEC clock. The paper does not examine whether this global synchronization causes unnecessary stalls or how performance changes under asynchronous scheduling.
  • CPU dependence is not generalized: Results are tied to one 2024 Apple M4 Max processor and a specific 12-core allocation. Performance across x86 CPUs, ARM CPUs, cloud processors, older systems, and different cache or memory-bandwidth configurations is not evaluated.
  • Resource and power costs are incomplete: The study reports CPU cores and timing but does not quantify CPU utilization, memory consumption per decoder instance, energy, thermal throttling, sustained performance, or the practical power cost of single-CPU decoding.
  • Input/output and data-transfer overheads are excluded or unclear: It is not established whether transferring raw syndrome data from the quantum control system to the CPU and returning frame updates fits within the stated timing budgets.
  • Real-time scheduling robustness is not tested: The simulations do not investigate operating-system interference, process scheduling, interrupts, background load, or worst-case rather than average/p99.9 latency guarantees.
  • Decoder parameter selection is not optimized systematically: The fixed window sizes, commit regions, beam widths, iteration counts, and four-to-eight core allocation are adopted from particular configurations without a systematic latency–accuracy–stretch optimization.
  • Tail-latency behavior remains insufficiently bounded: The reported p99.9 statistics do not establish p99.99 or worst-case decoding latency, which may be more relevant for long computations containing millions of windows.
  • Stretch is not connected to application-level performance: The paper quantifies additional SECs but does not analyze how stretch affects wall-clock runtime, factory throughput, resource wastage, algorithmic success probability, or the scheduling of dependent operations.
  • Magic-state factory effects are incompletely characterized: The impact of decoder delays and EDM decisions on factory rejection rates, magic-state supply, pipeline utilization, and overall non-Clifford throughput is not separately quantified.
  • The intrinsic cat-readout error floor is not numerically characterized: The paper explains that some error mechanisms are indistinguishable, but does not report the floor for each code, measurement type, operator weight, or noise rate.
  • The trade-off between outcome-decoder speed and logical accuracy is not fully validated: The claim that the shorter-window outcome decoder adds negligible error is not supported with detailed end-to-end comparisons against the more accurate error decoder.
  • Operator-dependent decoding costs are unexplored: Since cat-measurement DEM priors depend on the logical Pauli operator, the paper does not quantify how operator weight, geometry, or measurement frequency affects DEM-generation and decoding time.
  • Compiler overhead is not separated from decoder performance: The benchmarks use specific Clifford+TT compilations and approximate synthesis, but do not examine how alternative compilers, synthesis tolerances, or circuit optimizations change the number and temporal distribution of measurements and factory operations.
  • Approximation errors in benchmark circuits are not incorporated into the evaluation: For the MIPT workload, the operator-norm synthesis error is bounded by $0.01$, but its effect on the physical algorithm, phase-transition observables, and overall computational correctness is not assessed.
  • Comparative decoder evaluation is absent: The paper does not compare the proposed system against alternative software decoders, hardware decoders, different beam-search configurations, or hybrid CPU/GPU/FPGA implementations under identical workloads and accuracy targets.
  • Reproducibility is incomplete: The full circuit instances, noise-model parameters, decoder source code, hardware measurement methodology, random seeds, and detailed implementation settings needed to independently reproduce the timing and stretch results are not provided in the paper.
  • Long-duration stability is untested: The simulations cover large SEC volumes, but do not assess performance degradation from memory fragmentation, cache-state evolution, thermal effects, resource leaks, or numerical instability over substantially longer executions.
  • Fault tolerance of the classical control path is not addressed: The consequences of CPU faults, software bugs, corrupted syndrome packets, lost measurement results, or incorrect frame updates are outside the analysis.
  • The boundary-condition treatment is underexplained: The impact of initialization, termination, decoder-window boundaries, and transitions between ordinary, cat, and factory-specific decoding regimes on both latency and accuracy is not systematically quantified.
  • The relationship between decoder backlog and global scheduling is architecture-dependent: The reported stretch assumes a particular synchronized execution policy; alternative scheduling strategies that allow independent blocks to progress or prioritize critical blocks are not investigated.
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Practical Applications

Immediate Applications

The paper’s main practical contribution is a software decoding stack for the walking-cat architecture (WCA) that combines on-the-fly detector error model generation, dual sliding-window decoding, and memory-optimized beam search. Although the results are simulation-based rather than a demonstrated deployment on a functioning MegaQuOp processor, several applications are immediately feasible as software, design, and benchmarking tools.

  • Fault-tolerant quantum-computer control software (quantum computing, software; Immediate Application) The dual-decoder architecture can be integrated into a trapped-ion quantum-control stack to process syndrome streams continuously while a circuit executes. The error decoder can maintain Pauli-frame corrections, while the lower-latency outcome decoder can return measurement results needed for feed-forward operations, magic-state consumption, and conditional branching. Potential product/workflow: a CPU-based real-time decoding service connected to the quantum controller through a streaming syndrome-data interface. Dependencies: compatibility with the target code, WCA schedule, detector format, operating system, I/O latency, and actual trapped-ion cycle time.
  • Decoder-in-the-loop simulation and benchmarking (academia and quantum-software engineering; Immediate Application) Researchers can use the implementation strategy to evaluate complete fault-tolerant workloads rather than isolated memory experiments. The benchmark methodology supports measurements of decoding latency, backlog, stretch, convergence failures, logical measurements, and magic-state-factory performance. Potential tools: a simulator plug-in that reports wall-clock decoding time and schedule stretch for circuits compiled into WCA-compatible blocks. Dependencies: realistic circuit-level noise models and accurate modeling of CPU contention, memory bandwidth, data-transfer overhead, and controller scheduling.
  • CPU-based prototyping for quantum-computing startups and laboratories (industry and academia; Immediate Application) A conventional multicore CPU can serve as an initial decoder platform, avoiding the need for custom FPGAs, GPUs, TPUs, or ASICs during early system development. The paper reports less than approximately 0.3%0.3\% stretch at pCNOT=10−4p_{\mathrm{CNOT}}=10^{-4} and less than approximately 12%12\% at 5×10−45\times10^{-4} for the tested workloads. Potential workflow: prototype the full fault-tolerant control loop on commodity CPUs, then migrate only proven bottlenecks to specialized hardware. Dependencies: the reported performance was obtained on a 2024 Apple M4 Max using 12 cores and may not transfer directly to x86 servers, embedded CPUs, or future architectures.
  • Resource provisioning and capacity planning (quantum-cloud infrastructure and system architecture; Immediate Application) The measured relationship between code-block count, decoding time, CPU allocation, and schedule stretch can inform estimates of the classical compute required per quantum processor. Operators can use the reported budgets—approximately 3τSEC3\tau_{\mathrm{SEC}} for the error decoder and τSEC\tau_{\mathrm{SEC}} for the outcome decoder—to determine whether a workload is likely to develop a backlog. Potential product: a decoder capacity-planning tool that predicts CPU-core requirements, tail latency, stretch episodes, and restart risk from a compiled circuit and hardware noise parameters. Dependencies: workload structure, physical error rate, SEC duration, block-to-core assignment, and acceptable tail-latency targets.
  • Software-defined optimization of fault-tolerant execution (compiler technology; Immediate Application) Since many Clifford operations in WCA are handled through frame tracking, compilers can reduce physical operations and simplify the decoder’s input stream. The fixed Tanner graph with dynamically updated priors also enables efficient compilation and runtime scheduling of logical Pauli measurements without rebuilding the decoding graph. Potential tools: compiler passes that minimize cat-state insertions, balance code blocks across CPU cores, schedule magic-state consumption, and flag decoder-critical measurement regions. Dependencies: availability of a WCA-compatible compiler and preservation of circuit fidelity when using approximate Clifford+TT synthesis.
  • Real-time monitoring and adaptive scheduling (quantum hardware operations; Immediate Application) Decoder backlog and stretch episodes can be monitored during execution. A controller could use these signals to delay noncritical measurements, rebalance decoding processes, alter workload admission, or trigger a controlled pause before a backlog becomes operationally significant. Potential workflow: telemetry dashboards showing per-block decoding time, p99.9 latency, backlog depth, convergence failures, and projected computation stretch. Dependencies: the controller must tolerate the synchronization behavior described in the paper, in which a delayed block can extend the global SEC schedule.
  • Training and curriculum material for fault-tolerant quantum computing (education and research; Immediate Application) The paper provides a concrete example linking quantum architecture, detector error models, Tanner graphs, beam-search decoding, streaming measurements, and classical scheduling. It can support laboratory exercises in which students compare fixed-graph/dynamic-prior decoding with graph reconstruction or offline decoding. Dependencies: access to an executable implementation or a sufficiently faithful open simulation environment.
  • Policy and infrastructure assessment for quantum-computing deployment (science policy and technology strategy; Immediate Application) Policymakers and funding agencies can use the results to evaluate the classical-computing infrastructure required by future fault-tolerant quantum systems. The paper suggests that early MegaQuOp-scale trapped-ion systems may not require dedicated decoder accelerators if their SEC times and physical error rates remain within the tested regime. Dependencies: the result should not be generalized to superconducting systems with microsecond-scale cycles, different codes, or substantially different noise distributions without new benchmarks.
  • Daily-life relevance through enabling infrastructure rather than direct consumer use (daily life; Immediate Application) There is no direct household or consumer application demonstrated by the paper. However, the availability of a lower-cost CPU-based decoder could reduce the infrastructure barrier for organizations developing quantum services, potentially supporting future applications in chemistry, materials science, optimization, and cryptanalysis. Dependencies: useful consumer outcomes depend on the eventual availability, reliability, and economic value of large fault-tolerant quantum computers.

Long-Term Applications

The following applications require hardware validation, larger-scale experiments, architectural co-design, or further research into performance and reliability.

  • Deployment in a full MegaQuOp trapped-ion quantum computer (quantum-computing hardware; Long-Term Application) The decoder could become the classical real-time error-correction layer for processors with hundreds of logical qubits and millions of logical operations. The paper’s largest simulated workload uses 408 logical qubits, 88 memory blocks, 20 magic-state factories, and more than one million logical measurements. Potential product: an integrated fault-tolerant trapped-ion system in which CPUs decode syndrome data while the quantum controller executes the next SEC or measurement. Dependencies: experimental validation of the WCA, Q70 code, CH2 factories, cat-state measurement protocol, physical error rates, SEC durations, data links, and synchronization mechanisms.
  • Scaling to thousands or more logical qubits (quantum-computer architecture; Long-Term Application) The proposed provisioning rule—scaling resources primarily with the number of code blocks per core—could support larger machines by adding CPU cores or additional CPUs. The static Tanner graph and dynamic-prior approach may simplify distributed decoding across many blocks. Dependencies: inter-core communication, NUMA and memory-bandwidth effects, scheduling imbalance, synchronization overhead, and whether decoding tails grow faster than the available execution budget.
  • Hybrid CPU/accelerator decoder architectures (hardware design; Long-Term Application) The memory optimizations could be transferred to FPGA, GPU, ASIC, or specialized inference hardware. CPUs could handle dynamic DEM generation, control flow, and rare branches, while accelerators process repetitive belief-propagation or beam-search operations. Potential product: a heterogeneous decoder with CPU-managed dynamic priors and accelerator-based Tanner-graph computation. Dependencies: hardware implementation must preserve the low-latency outcome-decoding path and justify its engineering cost relative to commodity CPUs.
  • Fault-tolerant quantum simulation for chemistry and materials (science and industrial R&D; Long-Term Application) The Heisenberg benchmarks indicate a route toward executing large Hamiltonian-simulation workloads with real-time decoding. Once hardware is available, similar workflows could be applied to electronic-structure calculations, material-property prediction, catalyst design, and strongly correlated systems. Dependencies: the decoder is only one component; useful simulations also require sufficiently low logical error rates, adequate magic-state throughput, accurate compilation, state-preparation methods, and practical runtime.
  • Large-scale quantum many-body and measurement-induced-transition experiments (academic physics; Long-Term Application) The MIPT benchmark demonstrates that circuits with frequent logical measurements and more than one million TT gates can be evaluated within the proposed decoding framework. This could enable experimental studies of phase transitions, entanglement dynamics, and monitored quantum systems at sizes beyond current noisy-device capabilities. Dependencies: measurement fidelity, reliable adaptive feed-forward, sufficiently long coherence and computation times, and validation that approximate gate synthesis does not obscure the physical phenomenon being studied.
  • Adaptive fault-tolerant runtime systems (quantum operating systems; Long-Term Application) A future quantum operating system could use decoder confidence, Viterbi stopping decisions, EDM acceptance, and backlog telemetry to adapt measurement repetition, magic-state consumption, circuit scheduling, and error-management policies during execution. Potential tools: runtime APIs exposing decoder confidence and latency, adaptive repetition controllers, and schedulers that trade computation time against logical reliability. Dependencies: formal guarantees are needed so that adaptive behavior does not introduce bias, alter algorithmic semantics, or compromise fault tolerance.
  • Reliability-aware quantum-cloud scheduling (cloud computing and finance/operations research; Long-Term Application) Quantum-cloud providers could schedule jobs according to predicted decoder load, physical error rate, magic-state demand, and acceptable stretch. Workloads with many measurements or large numbers of TT gates could be assigned additional CPU capacity or reserved execution slots. Dependencies: this requires validated performance models, reproducible cross-platform benchmarks, and service-level agreements that account for probabilistic decoder latency and possible convergence-triggered restarts.
  • Formal verification and safety certification of real-time decoders (policy, standards, and critical infrastructure; Long-Term Application) Because decoder decisions affect conditional quantum operations and computation correctness, future standards could require verification of streaming behavior, bounded latency, convergence-failure handling, and reproducibility across hardware platforms. Potential outputs: certified decoder modules, standardized DEM interfaces, latency-testing protocols, and audit logs for fault-tolerant quantum executions. Dependencies: agreement on logical-error, latency, stretch, and restart-risk metrics, together with experimental evidence beyond the paper’s simulated noise model.
  • Energy-efficient classical control for quantum data centers (energy and sustainable computing; Long-Term Application) If commodity CPUs can decode large trapped-ion workloads with acceptable stretch, quantum data centers may avoid always-on specialized accelerators for some operating regimes. This could reduce capital cost and potentially improve energy proportionality by scaling classical resources with active code blocks and workload demand. Dependencies: actual power measurements are absent from the paper; energy benefits must be demonstrated against FPGA, GPU, ASIC, and alternative CPU implementations, including cooling and data-movement costs.
  • Broader application to other codes and quantum architectures (cross-platform quantum engineering; Long-Term Application) The dual-decoder concept—continuous high-accuracy error decoding plus a separate low-latency measurement-outcome decoder—could inspire analogous designs for other qLDPC or topological-code architectures. The fixed-Tanner-graph/dynamic-prior technique may also be reusable whenever operations alter error probabilities without changing detector connectivity. Dependencies: this is not automatic. Lattice surgery, code deformation, different syndrome schedules, superconducting microsecond cycles, correlated noise, and architecture-specific detector signatures may require new graph representations or specialized hardware.
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Glossary

  • Adaptive Viterbi scheme: A Viterbi-based decoding method that updates its estimate as new measurement data arrive and stops after reaching a confidence criterion. “these repeated CMs are processed using an adaptive Viterbi scheme that updates a likelihood over measurement histories and terminates once a prescribed confidence threshold is reached.”
  • Ancilla patch: An auxiliary encoded region used to support operations on logical qubits. “quantum architectures performing logical operations by merging memory blocks with complex ancilla patches”
  • Beam search decoder: A heuristic decoder that retains only a fixed number of the most promising candidate states during probabilistic search. “Our decoding system is based on a dual sliding-window decoder built around the beam search decoder”
  • Belief propagation: An iterative algorithm for estimating variables in a graphical model by passing probability-related messages between connected nodes. “we reinitialize each outgoing variable-to-check message as λ−λ−λ0d\lambda-\frac{\lambda-\lambda_0}{d}.”
  • Cat state: A multipartite entangled state used here to perform a logical Pauli measurement. “A cat state is used to measure a chosen physical representative of the logical operator and is then read out.”
  • Cat-based measurement (CM): A measurement that uses a cat state to measure an encoded logical operator. “Since an individual cat-based measurement (CM) is noisy, measurements are repeated to reach higher reliability”
  • Cat SEC: A syndrome-extraction cycle consisting of a cat-based measurement followed by an ordinary syndrome-extraction cycle. “We call the interval consisting of a CM followed by this SEC a cat SEC”
  • Circuit-level noise model: A noise model that assigns errors to operations and measurement processes within a quantum circuit. “We simulate all three benchmark workloads using the circuit-level noise model”
  • Clifford frame: Classical information tracking the effective Pauli or Clifford transformation associated with an encoded quantum state. “These are consumed through sequences of logical Pauli measurements and measurement-conditioned updates of the Clifford frame.”
  • Code deformation: A change in the geometry or stabilizer structure of an error-correcting code to implement a logical operation. “logical computation adds CMs to otherwise unchanged syndrome extraction, without requiring operations such as lattice surgery or code deformation.”
  • Code block: An independently encoded collection of physical qubits representing one or more logical qubits. “Each decoder core is assigned a fixed subset of code blocks and processes those blocks sequentially”
  • Conditional logical operation: A logical quantum operation selected according to a measurement outcome obtained during computation. “To allow for magic state injection and conditional logical operations”
  • Convergence failure: A failure of an iterative decoding procedure to produce a valid decoding result. “a convergence failure requires restarting the affected computation.”
  • Detector error model (DEM): A model specifying how elementary error mechanisms trigger detection events and the prior probabilities of those mechanisms. “A sliding-window decoder operates on a detector error model, which specifies how elementary error mechanisms affect the observed detectors.”
  • Dual sliding-window decoder: A decoding system that uses two concurrently operating decoders over finite, overlapping portions of a syndrome stream. “Our decoding system is based on a dual sliding-window decoder built around the beam search decoder”
  • Error-detected measurement (EDM): A measurement procedure that accepts an outcome only when constituent measurements agree. “magic-state factory blocks use the error-detected measurement (EDM) scheme, which post-selects on agreement of all constituent CMs before accepting the outcome.”
  • Fault-tolerant: Designed to continue functioning correctly despite a limited number of physical errors. “a universal fault-tolerant trapped-ion architecture”
  • Frame tracking: The classical tracking of corrections so that many logical operations can be implemented without physically applying them. “accessible logical Clifford gates are implemented entirely in software via Clifford-frame tracking”
  • Haar-random: Distributed according to the uniform probability measure over unitary transformations. “40 one-dimensional brickwork layers of Haar-random two-qubit gates”
  • Intrinsic error floor: A lower bound on the achievable error rate caused by indistinguishable error mechanisms rather than decoder limitations. “They therefore impose an intrinsic error floor on the corrected cat-state readout.”
  • Logical qubit: An error-protected qubit encoded using multiple physical qubits. “a device capable of executing millions of operations on hundreds of logical qubits”
  • Logical Pauli measurement: A measurement of a Pauli operator acting on an encoded quantum state. “Logical Pauli measurements are implemented physically using cat states.”
  • Magic state: A specially prepared non-stabilizer quantum state used to implement non-Clifford gates fault-tolerantly. “Non-Clifford resources, in particular TT gates, are introduced via magic states prepared in dedicated factory blocks.”
  • Magic-state factory: A fault-tolerant circuit that produces purified magic states for use in non-Clifford operations. “The complete pipeline, including on the fly detector error model generation, decoding of all logical qubits, logical operations, and magic-state factories”
  • Measurement-induced phase transition (MIPT): A transition in quantum dynamics caused by the competition between unitary evolution and measurements. “The MIPT circuit realizes the measurement-induced phase-transition model”
  • Message-passing topology: The connectivity structure governing the exchange of messages in a graphical-model decoder. “they require restructuring the message-passing topology and associated decoder data structures during execution.”
  • Non-Clifford gate: A quantum gate that does not belong to the Clifford group and generally requires additional fault-tolerant resources. “Non-Clifford resources, in particular TT gates”
  • Operator-norm error: The maximum deviation between operators measured using the operator norm. “with operator-norm error at most $0.01$.”
  • Pauli frame: A classical record of pending Pauli corrections that need not be physically applied immediately. “The error decoder runs continuously over both ordinary and cat SECs.”
  • Parity-check matrix: A binary matrix describing which error variables affect which parity checks or detectors. “a Tanner graph, equivalently a parity-check matrix”
  • Post-selection: Conditioning on selected measurement outcomes and discarding all other outcomes. “which post-selects on agreement of all constituent CMs before accepting the outcome.”
  • Quantum error correction (QEC): The protection of quantum information against noise through encoding, syndrome measurement, and correction. “Thus the decoding problem retains the structure of QEC memory experiments”
  • Quantum low-density parity-check (qLDPC) code: A quantum error-correcting code represented by sparse parity checks involving relatively few qubits. “Previous work focuses on increasing the speed and throughput of surface code and quantum low-density parity-check (LDPC) memory decoders”
  • Real-time decoding: Decoding measurement data quickly enough to keep pace with an ongoing quantum computation. “These results demonstrate real-time decoding at MegaQuOp scale on a single conventional CPU.”
  • Ross–Selinger synthesis: A method for approximating single-qubit unitaries using Clifford and TT gates. “Each Haar-random two-qubit gate is compiled to Clifford+T+T using the KAK decomposition and Ross--Selinger synthesis”
  • Syndrome extraction cycle (SEC): A repeated procedure that measures error syndromes to detect faults in encoded quantum data. “The error decoder, with a 3-SEC commit region, has a budget of $3\tau_{\mathrm{SEC}$ per window”
  • Tanner graph: A bipartite graph representing variables and parity checks in an error-correcting code. “The two mechanisms therefore correspond to identical columns of the parity-check matrix”
  • Trotter step: One iteration of a product-formula approximation to time evolution under a Hamiltonian. “Both implement a single sixth-order Trotter step”
  • Viterbi margin: A confidence difference or criterion used to determine when a Viterbi decoder can commit to an outcome. “Viterbi margin is reached if c1⊕d1c_1{\oplus}d_1 = c2⊕d2= c3⊕d3=\,c_2{\oplus}d_2 =\, c_3{\oplus}d_3”
  • Walking cat architecture (WCA): The fault-tolerant architecture described in the paper, which uses cat-based measurements and software frame tracking. “A key ingredient in the realization of a single-CPU real-time MegaQuOp decoder is the simplicity of the walking cat architecture (WCA)”
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