Breakeven demonstration of quantum low-density parity-check codes

Abstract: High-rate quantum low-density parity-check (qLDPC) codes are a leading candidate for fault-tolerant quantum computing. They feature higher encoding rates than planar alternatives such as the surface code, but their implementation often entails significant hardware hurdles like the need for long-range couplers. We leverage the flexibility of a trapped-ion quantum computer to demonstrate nine quantum error-correcting codes with starkly different qubit connectivity requirements on a single device without any hardware reconfiguration. These experiments span three families of quantum error-correcting codes: qLDPC codes, topological codes, and concatenated codes. With a qLDPC code encoding 4 logical qubits into 18 physical qubits, we achieve a logical error rate up to $9\times$ better than a previous demonstration of a similar code on superconducting solid-state qubits. Moreover, our implementation exhibits breakeven performance, with some instances achieving qubit lifetimes comparable to or slightly exceeding that of our trapped-ion qubits. We use a novel implementation of the optical-metastable-ground (OMG) architecture for addressable mid-circuit measurement and reset, which enables us to perform these experiments without any ion transport or dedicated coolant ions, requirements that typically consume a large fraction of the runtime or ion count of trapped-ion quantum computers.

• The paper demonstrates breakeven operation by achieving logical qubit lifetimes that exceed physical qubit limits using high-rate qLDPC codes.
• It introduces an advanced mid-circuit measurement (MCM) protocol with all-to-all connectivity, enabling flexible, efficient error correction cycles.
• Logical error rates improve by 4x to 9x over previous implementations, highlighting the scalability and potential of qLDPC codes for fault-tolerant quantum computing.

Breakeven Demonstration of Quantum Low-Density Parity-Check Codes

Overview

The paper "Breakeven demonstration of quantum low-density parity-check codes" (2606.06455) presents the first experimental demonstration of multiple high-rate quantum LDPC (qLDPC) codes on a fully programmable trapped-ion quantum computer, achieving breakeven logical qubit lifetimes relative to physical qubits. The experimental platform allows the implementation of diverse quantum error correction (QEC) codes, including multiple families of qLDPC, topological, and concatenated codes, without hardware reconfiguration—highlighting the versatility of the underlying hardware and control architecture.

Significance of qLDPC Codes in Fault-Tolerant Quantum Computing

qLDPC codes are currently a leading candidate for scalable, qubit-efficient fault-tolerant quantum computation (FTQC) due to their high encoding rates, reducing the physical qubit overhead compared to surface codes. However, the typical requirement for long-range gates and non-local connectivity makes their experimental realization considerably more challenging than planar stabilizer codes. Previous experimental efforts on qLDPC codes, especially the BB5 and related bicycle codes, relied on custom superconducting hardware with architecture-tailored long-range couplers [wang_demonstration_2026].

This work leverages a 40-ion chain trapped-ion platform, which offers native all-to-all connectivity, to implement distinct qLDPC codes with up to 30 data qubits and variable ancilla configurations, as well as topological (toric) and concatenated code families. Notably, these implementations required no hardware reconfiguration at the level of gate calibration or device layout. The authors introduce a novel realization of the optical-metastable-ground (OMG) protocol for addressable, high-throughput mid-circuit measurements (MCM) and reset operations, enabling QEC cycles with efficient syndrome extraction and no need for separate coolant ions—unprecedented in the scale and fidelity for fully functional, entangling trapped-ion quantum computation.

Experimental Methodology and Hardware Architecture

The trapped-ion QPU employs steerable Raman beams with acousto-optic deflectors (AODs), offering precise single and two-qubit gates between any pair of ions in the stationary chain, avoiding qubit transport.

The critical functionality for syndrome extraction is made possible by an advanced implementation of the OMG architecture, which supports coherent shelving/deshelving to atomic metastable manifolds, allowing parallel MCM across variable numbers of ancillae. The design circumvents longstanding limitations of mid-circuit measurement and active ancilla reset by using the internal structure of $^{133}$Ba$^+$ and tailored laser control, enabling execution of QEC cycles with minimal idle errors or decoherence of data qubits.

Figure 2: Executed syndrome circuits and gate operations for all implemented codes, grouped by code distance and syndrome cycle.

The modularity and all-to-all connectivity enable optimized qubit-to-ion mappings for each code instance. The authors detail a mapping optimization strategy leveraging DRB-characterized two-qubit gate fidelities, minimizing logically weighted infidelity for every syndrome circuit.

Figure 4: Distribution of two-qubit gate fidelities for used ion pairs in each syndrome circuit, illustrating optimization gains over default mappings.

Logical Qubit Performance and Error Correction

Quantum memory experiments encode logical eigenstates of multiple logical qubits, perform repeated syndrome cycles using pipelined ancilla and MCM, and decode outcomes with a beam search decoder optimized for qLDPC codes [ye_beam_2025]. Survival probabilities and logical error rates are extracted by fitting logical state relaxation data to exponential decay forms, and compared to destructive measurement without decoding.

Key results:

• For the BB5 $[[18,4,3]]$ code (encoding $k=4$ logical qubits using $n=18$ physical qubits), the logical $X$ and $Z$ error rates per cycle are $2.01\times 10^{-2}$ and $1.08\times 10^{-2}$ respectively, representing 4x and 9x improvements over prior state-of-the-art superconducting implementations [wang_demonstration_2026].
• Logical qubit lifetimes (defined via channel decay speed) in the best code instances marginally exceed the measured $T_2^*$-limited lifetime ($^+$0–$^+$1 s) of the physical qubits, establishing operation in the breakeven regime—a critical FTQC milestone.
• Implementation of toric and concatenated codes further demonstrates the flexibility of the architecture.

  Figure 6: Total durations of syndrome circuits for all codes, showing linear scaling with number of syndrome cycles and code parameters.

A detailed analysis of leakage, post-selection, and potential erasure conversion quantifies the impact of leakage events and post-selection strategies on logical error rates. Active leakage erasure/initialization would degrade logical performance by no more than 10–20% under current operational regimes.

Syndrome Extraction, MCM Performance, and Circuit Timing

The OMG-based MCM protocol supports simultaneous readout of up to 20 ancillae, with total protocol time increasing weakly with ancilla number. The syndrome circuit and MCM durations are analyzed and clearly scale sublinearly with code weight—enabling execution of substantial QLDPC code blocks within feasible coherence windows.

Figure 8: MCM protocol duration as a function of number of ancillae measured; nearly flat scaling highlights high practical parallelism.

Implications and Outlook

The experimental results establish several critical points for the future of FTQC with qLDPC codes on scalable quantum hardware:

• High-rate LDPC codes are no longer limited to theoretical or small-scale demonstrations; practical codes of moderate distance and multiple logical qubits perform at or beyond the breakeven threshold.
• Trapped-ion platforms, given their gate reconfigurability and native all-to-all interactions, are distinctly suited for the flexible implementation of high-weight, non-local stabilizer circuits characterizing qLDPC and advanced codes. The modularity in qubit/ancilla mapping directly results in lower logically weighted infidelity, as experimentally evidenced.
• The OMG architecture for MCM, if scaled, obviates ancillary hardware complexity associated with coolant species and mechanical shuttling, marking a significant step toward reduction of overhead and operational complexity in realistic FTQC architectures.
• The methodology here is compatible with further enhancements such as increased parallelization (multiple Raman interaction zones or all-electronic controls [malinowski2023wire, loschnauer2025scalable]), improved physical gate fidelities [hughes2025trapped], and dynamical decoupling for physical and logical qubits, all of which are likely to extend logical qubit lifetimes beyond current hardware limits.

The work positions high-rate qLDPC codes as not only a theoretical but also a practical foundation for future, resource-efficient FTQC architectures, and it provides a blueprint for subsequent scaling and algorithmic demonstrations in this direction.

Conclusion

This work demonstrates—for the first time—the breakeven operation of multiple families of qLDPC codes on a single, reconfigurable trapped-ion QPU, exceeding the logical error rates of prior experiments by substantial factors. These results directly address fundamental challenges in hardware-code co-design for FTQC by exploiting the flexibility of all-to-all connectivity and advanced MCM control. As hardware parallelism, gate fidelities, and error mitigation stack improve, implementations of qLDPC codes of increasing distance and number of logical qubits on general-purpose quantum hardware are now on a rapid practical trajectory toward scalable, fault-tolerant quantum computation.