Real-Time Quantum Error Correction System Stack: Architecture, Algorithms, and Engineering Practice

Abstract: Quantum error correction (QEC) is transitioning from physical feasibility demonstrations to systems engineering challenges. Google has achieved below-threshold performance on distance-5/7 surface codes, while Riverlane and Rigetti have demonstrated hardware-integrated low-latency feedback loops. These milestones indicate that the core challenge of real-time decoding has shifted from algorithmic capability to system-level engineering. However, a substantial engineering gap remains between laboratory demonstrations and scalable fault-tolerant quantum computing (FTQC). This white paper addresses three questions: (1) Where are the real bottlenecks in real-time QEC: beyond average decoder speed, the constraints lie in QEC round time, tail latency, and end-to-end data path coordination; (2) How mature are mainstream decoder algorithms: we benchmark the major decoders for both surface codes and quantum low-density parity-check (qLDPC) codes, evaluating their real-time readiness; (3) What system stack do we propose: a six-layer reference architecture from syndrome acquisition to logical operations, with interface definitions and latency budget models. Our results quantify the gap between current decoder performance and real-time requirements, and identify the architectural choices needed to close it.

• The paper shows that real-time QEC depends on sustained throughput, tail latency, backlog control, and feedforward deadlines—not average decoder speed alone, with MWPM meeting a 1 μs round budget only at modest surface-code distances.
• The paper benchmarks heterogeneous decoders, finding that windowed MWPM incurs 2–4× batch overhead while GPU-batched BP+OSD achieves 8.2–239.5 μs per round for tested qLDPC codes with near-bounded tail latency.
• The paper proposes a six-layer architecture spanning the QPU, readout, transport, decoding, frame management, and logical scheduling, alongside structured syndrome data, adaptive dispatch, hardware acceleration, and speculative decoding.

Overview and thesis

This white paper argues that the central challenge of real-time quantum error correction (QEC) has shifted from decoder algorithm design to system-level engineering. The authors—drawn from FieldQuantum, China Mobile Research Institute, Xoherence, CAS Cold Atom Technology, and Beijing Taichu Yuanxin—organize their argument around six claims: (1) the bottleneck is now systems rather than algorithms; (2) most QEC closed loops operate in Pauli-frame tracking mode without physical correction, with hard deadlines arising only at feedforward synchronization points; (3) a decoder that falls behind suffers compounding consequences through idle-error accumulation and stalled logical progress; (4) tail latency, not average latency, is the operationally relevant metric; (5) surface codes and qLDPC codes impose fundamentally different system requirements; and (6) heterogeneous compute architecture and end-to-end integration will be the next differentiators. The paper supports these claims with a formal system model, a survey of codes and decoders across platforms, original benchmarks of MWPM and BP+OSD decoders under circuit-level noise, and a proposed six-layer reference architecture.

Motivation from recent experimental milestones

The paper situates itself against four distinct experimental milestones: Google's below-threshold demonstration on the Willow processor, where logical error rates decrease exponentially with distance ($\Lambda = 2.14 \pm 0.02$) and the $d=7$ logical qubit exceeds the best physical qubit lifetime by $2.4\times$; Riverlane and Rigetti's hardware-integrated Union-Find decoding on FPGA with sub-microsecond latency; Quantinuum's real-time fault-tolerant logical teleportation on trapped ions using the Steane code, extended to fault-tolerant T-gates with infidelity as low as $\sim 2.6 \times 10^{-3}$; and QuEra's 48-logical-qubit error-detected processor on neutral atoms. The authors emphasize that none of these constitutes a scalable fault-tolerant system: Google's primary result used offline decoding, Riverlane/Rigetti's was limited to small-distance memory experiments with an accuracy-inferior decoder, and QuEra's processor detects but does not correct errors. The gap between these demonstrations and continuous operation at $d \geq 17$ over millions of rounds is characterized as an engineering gap.

System model: two operating regimes

A key conceptual contribution is the decomposition of real-time decoding into two timing regimes. In the streaming regime (Clifford-only computation), corrections accumulate in the classical Pauli frame and no per-round deadline exists; the requirement is only sustained throughput stability, $\mu \geq \lambda$, where $\lambda = 1/T_\text{round}$ is the syndrome arrival rate and $\mu$ the decoder's steady-state throughput. Violation produces linearly growing backlog $B(t) \approx (\lambda - \mu)t$. In the synchronization regime (non-Clifford gates, adaptive measurements), the frame must be fully resolved before feedforward decisions are fixed, giving synchronization latency

$$T_\text{sync} = \frac{B_\text{sync}}{\mu} + T_\text{sync}^{(0)},$$

where $d=7$0 is irreducible pipeline overhead and $d=7$1 is avoidable stall. During stalls, data qubits accumulate idle errors that can push the effective error rate toward threshold, making error correction counterproductive. This framing yields four metrics—sustained throughput, $d=7$2 tail latency, backlog at synchronization, and fixed pipeline overhead—and a bound on logical operation rate $d=7$3.

The model is instantiated per platform. Superconducting systems face the tightest constraint: $d=7$4s with coherence times of only tens of microseconds, demanding sustained throughput $d=7$5 MHz with low tail latency. Trapped ions and neutral atoms have millisecond-scale cycles and much longer coherence, relaxing throughput requirements by three orders of magnitude ($d=7$6 kHz)—but the paper notes this relaxation may be partially offset if such platforms adopt large-block qLDPC codes decoded by super-linear-scaling algorithms like BP+OSD, and explicitly leaves open whether the relaxed budget suffices for large-distance qLDPC decoding. For neutral atoms, atom movement and image-based readout dominate the round budget (roughly $d=7$7s to several milliseconds), and algorithm runtime scales linearly with $d=7$8: Cain et al.'s estimate of ~97 days for RSA-2048 assumes a 1 ms round time, so an order-of-magnitude slowdown would push runtime toward years.

Code families and hardware co-design

The code survey contrasts three families along dimensions relevant to system design. The rotated surface code offers a ~1% circuit-level threshold, weight-4 local stabilizers, mature graph-based decoders, but vanishing encoding rate $d=7$9. Color codes permit transversal Clifford gates but carry a much lower threshold (~0.08%) and hypergraph syndrome structure requiring restriction or Möbius decoders. Bivariate bicycle qLDPC codes achieve constant rate—the $2.4\times$0 code encodes at ~8.3% versus ~2% for $2.4\times$1 surface code—with a comparable threshold (~0.7–0.8%, conditional on native degree-6 connectivity), but demand non-local connectivity, deeper extraction circuits, and slower BP+OSD-style decoding; universal fault-tolerant gate sets for qLDPC codes remain less developed, which the paper flags as an important open direction.

The co-design analysis maps codes to platforms: surface codes align naturally with fixed nearest-neighbor superconducting layouts; trapped ions suit compact color/Steane blocks exploiting flexible connectivity but face shuttling, recooling, and motional-mode crowding at scale; neutral atoms favor erasure-aware decoding and potentially high-rate codes, provided readout exports loss-location metadata so decoders can exploit known-location erasures rather than treating all faults as unknown Pauli errors.

Decoder landscape

The decoder survey evaluates candidates along six axes including accuracy, tail latency, scalability, hardware mapping, code generality, and metadata adaptability. Sparse Blossom MWPM (PyMatching v2) achieves near-linear average-case performance (~1 million errors per core-second) but exhibits heavy-tailed latency on dense syndromes. Union-Find offers almost-linear complexity $2.4\times$2 with predictable latency but lower accuracy near threshold, and has been demonstrated on FPGA at sub-microsecond latencies. BP+OSD remains the standard general-purpose qLDPC baseline, with OSD-0 costing ~100 μs on CPU for the $2.4\times$3 code and higher-order OSD adding exponential overhead in the enumeration order. Neural decoders are notable on two counts: AlphaQubit achieved $2.4\times$4 on Google's $2.4\times$5 code, exceeding correlated matching ($2.4\times$6), though its original inference latency (~24 μs/cycle) exceeded real-time budgets; AlphaQubit 2 reportedly achieves sub-microsecond per-cycle latency up to $2.4\times$7 surface code and $2.4\times$8 color code on TPU/GPU. Sliding-window decoding wraps any inner decoder, bounding per-step computation independent of total experiment length, at the cost of committing only $2.4\times$9 rounds while decoding a $\sim 2.6 \times 10^{-3}$0 window.

Benchmark results

All benchmarks use Stim circuit-level depolarizing noise (uniform rate $\sim 2.6 \times 10^{-3}$1 across Clifford, reset, measurement, and idle channels), $\sim 2.6 \times 10^{-3}$2 shots for accuracy sweeps, and single-core-pinned CPU or A100 GPU execution. The noise model's scope is stated plainly: it excludes leakage, atom loss, mid-circuit crosstalk, coherent errors, and temporal drift.

Surface code accuracy and latency

The accuracy sweep over $\sim 2.6 \times 10^{-3}$3–17 reproduces the expected threshold crossing at $\sim 2.6 \times 10^{-3}$4–0.8%, with $\sim 2.6 \times 10^{-3}$5 yielding ~15× lower logical error rate than $\sim 2.6 \times 10^{-3}$6 at $\sim 2.6 \times 10^{-3}$7. The latency results are the paper's sharpest quantitative findings:

Configuration ($\sim 2.6 \times 10^{-3}$8, single CPU core)	Meets 1 μs/round?
Batch mean, $\sim 2.6 \times 10^{-3}$9	Yes (0.10–0.67 μs/round)
Batch mean, $d \geq 17$0	No (up to 5.4 μs/round at $d \geq 17$1)
Window mean, any $d \geq 17$2	No (1.0–11.2 μs/round)
Batch $d \geq 17$3, $d \geq 17$4	Yes (0.20–0.61 μs/round)
Batch $d \geq 17$5, $d \geq 17$6	No

Window decoding is consistently 2–4× more expensive than batch for $d \geq 17$7, an inherent overhead of the $d \geq 17$8-round window required for correct boundary matching. The $d \geq 17$9/mean ratio is 1.7–3× for both modes, confirming that rare heavy-syndrome configurations dominate worst-case behavior. The overall gap between current software performance and the superconducting real-time deadline ranges from 1.2× (batch mean at $\mu \geq \lambda$0) to ~24× (window $\mu \geq \lambda$1 at $\mu \geq \lambda$2). The measurements cross-validate against NVIDIA's Ising-decoder benchmark (~2.75 vs ~2.5 μs/round at $\mu \geq \lambda$3, $\mu \geq \lambda$4). Three implications follow directly: hardware acceleration is essential beyond moderate distances; window decoding carries a fundamental overhead; and mitigation requires either relaxed deadlines (longer coherence, lower $\mu \geq \lambda$5 reduces syndrome density and improves batch latency 2–4×) or algorithmic shortcuts such as CNN pre-decoding to shrink the matching graph.

qLDPC latency

For bivariate bicycle codes $\mu \geq \lambda$6, $\mu \geq \lambda$7, and $\mu \geq \lambda$8 under a 1 ms/round budget appropriate to neutral-atom cycles, GPU-batched BP+OSD-0 (cudaq-qec, batch size 256) achieves 8.2, 42.5, and 239.5 μs/round at $\mu \geq \lambda$9 respectively ($\lambda = 1/T_\text{round}$0), versus 332.8 and 1040.7 μs/round for single-core CPU at $\lambda = 1/T_\text{round}$1—a 25–40× speedup at low noise growing to 150–230× at $\lambda = 1/T_\text{round}$2. The CPU implementation cannot even complete $\lambda = 1/T_\text{round}$3 within practical time (>5 min/shot for the OSD step). The tail behavior contrast is stark: the CPU decoder's $\lambda = 1/T_\text{round}$4 reaches ~45.5 ms/round at $\lambda = 1/T_\text{round}$5 for $\lambda = 1/T_\text{round}$6, roughly 10× its already-high mean, while the GPU decoder is essentially tail-free ($\lambda = 1/T_\text{round}$7/mean ≈ 1.1–1.2×) due to bounded BP iterations and synchronous batched OSD. The paper concludes that GPU batching closes most of the qLDPC real-time gap at moderate distances, but notes that scaling from $\lambda = 1/T_\text{round}$8 to $\lambda = 1/T_\text{round}$9 multiplies GPU latency by ~5.2× versus ~3.1× on CPU, indicating GPU acceleration benefits both stages yet does not flatten asymptotic growth.

Six-layer reference architecture

The proposed stack decomposes the data path into six layers: (1) QPU, (2) readout processing, (3) data transport, (4) decode engine, (5) frame manager, and (6) logical scheduler. Layers 1–4 form a real-time data plane converting physical readout into decoded corrections; layers 5–6 form a control plane handling frame resolution and logical scheduling. Two design choices deserve emphasis. First, the Layer-2 output interface is generalized beyond binary syndrome bits to a structured record carrying measurement confidence, erasure/loss-location flags, timestamps, block identifiers, and round indices—necessary for atomic platforms where erasure information materially improves decoding. Second, clock synchronization is treated as a cross-cutting concern requiring sub-microsecond alignment between QPU round counters and decoder timestamps, achievable via shared clock domains on integrated FPGA designs or PTP/PPS when the decoder runs on a separate host.

The decode engine receives the deepest treatment, decomposed into dispatch, backlog management, and deadline enforcement. The dispatch policy adaptively selects backends based on code family, backlog depth, and proximity to the next feedforward barrier—for example, switching from accurate CPU-MWPM to fast FPGA-UF as deadlines approach, with reduced confidence flagged to the frame manager. Backlog monitoring triggers escalation via batching, faster decoders, or scheduler-initiated pauses. The paper also proposes speculative decoding: run a fast decoder whose result is accepted immediately to meet streaming deadlines, while an accurate decoder runs concurrently and retroactively overrides the fast result before the next barrier if they disagree. At $\mu$0 disagreements are rare, so this bounds worst-case latency at the fast decoder's speed while preserving most of the accurate decoder's quality—an appealing proposal that remains unvalidated experimentally.

Scaling to $\mu$1 combines FPGA acceleration for surface-code UF (sub-microsecond at $\mu$2, requiring larger devices or multi-FPGA graph partitioning beyond), GPU pipelining of BP and OSD stages, Relay-BP variants that reduce or eliminate OSD (with FPGA Relay-BP achieving sub-microsecond per-cycle decoding of the $\mu$3 gross code at $\mu$4), two-layer parallel window decoding with reported order-of-magnitude speedups at 16-way parallelism, and distributed decoder sharding across logical patches with boundary coordination.

From decoding to application viability

The application chapter quantifies why decoder throughput is a first-order determinant of computational capability. Using RSA-2048 factoring (~$\mu$5 Toffoli gates) with one Toffoli magic-state factory consuming ~85 QEC rounds per cycle at $\mu$6 and $\mu$7s, the serial runtime lower bound is ~3.6 days—and the decoder must sustain full syndrome throughput without accumulating backlog across that entire multi-day run. The authors state plainly that this estimate oversimplifies by assuming perfect Clifford parallelization and ignoring routing overhead, but it illustrates the scale of sustained performance required. Even small sustained throughput deficits compound into hours of additional runtime at feedforward barriers.

The middleware analysis identifies three gaps: the absence of a community-accepted real-time benchmark suite (most papers report only average decode time at a single distance); ad hoc, vendor-specific QPU–decoder interfaces, with NVIDIA's NVQLink cited as a case study rather than an open standard; and immature qLDPC decoder pipelines relative to surface-code counterparts. Notably, the paper argues these gaps require systems engineering—deterministic networking, precision timing, heterogeneous orchestration, telemetry—rather than quantum physics breakthroughs, positioning telecom and cloud-infrastructure expertise as directly relevant to FTQC.

Limitations and open questions

The benchmark evidence rests on uniform circuit-level depolarizing noise, which the authors acknowledge understates real-device decoding load: coherent errors, leakage, readout crosstalk, and temporal drift produce correlated error patterns that disproportionately inflate the tail of the decode-time distribution governing hard-deadline compliance. The six-layer architecture is a design proposal without end-to-end validation on co-designed QPU, control electronics, and decoder hardware. Specific open problems include hardware-accelerated and specialized qLDPC decoding beyond BP+OSD; community-standardized syndrome packet formats and decoder APIs; platform-specific closed-loop benchmarks incorporating shuttling, atom movement, erasure-aware decoding, and full feedforward budgets; and experimental characterization of dynamic dispatch policies and speculative decoding under realistic device drift.

Conclusion

This white paper makes a disciplined case that real-time QEC readiness should be measured by sustained throughput, tail latency, backlog behavior, and end-to-end integration rather than average decode speed alone. Its quantitative contributions—single-core MWPM meeting the 1 μs deadline only in batch mode at $\mu$8 (and only at $\mu$9 for $B(t) \approx (\lambda - \mu)t$0), window-mode overhead of 2–4×, and GPU-batched BP+OSD sustaining sub-millisecond per-round decoding up to $B(t) \approx (\lambda - \mu)t$1 with bounded tails—sharpen the boundary between what commodity software achieves today and what scalable FTQC demands. The six-layer architecture, structured readout interface, and speculative decoding proposal provide a concrete engineering vocabulary for closing that gap, while the identified middleware and standardization gaps define where subsequent work is most needed.